TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate structure capable of reducing metal short circuit risk

Abstract

The utility model provides a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) array substrate structure capable of reducing metal short circuit risk, which comprises a substrate, a grid metal layer is prepared on the substrate in a patterning manner, an ITO (Indium Tin Oxide) film layer is plated on the grid metal layer, and a part of the ITO film layer is positioned above the grid metal layer and covers the grid metal layer to form a protective layer through yellow light and an etching process. The other part of the ITO film layer is positioned on the substrate and is designed on the same layer as the gate metal layer to form a pixel electrode layer; a gate insulating layer is formed above the ITO film layer by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, a connecting hole is formed in the gate insulating layer, and the connecting hole is positioned above the pixel electrode layer and exposes the pixel electrode layer; a semiconductor layer, a source and drain electrode layer, a passivation layer and a common electrode layer are sequentially prepared above the gate insulating layer, and the source electrode is in lap joint with the pixel electrode layer through a connecting hole. According to the utility model, the risk of metal short circuit between the gate metal layer and the source / drain electrode layer can be effectively reduced, an insulating layer coating and mask process is reduced, and the production cost is reduced.

Description

Technical Field

[0001] The utility model relates to the field of a TFT-LCD array substrate structure, in particular to a TFT-LCD array substrate structure capable of reducing the risk of metal short circuit. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is still the mainstream technology in the display industry due to its low production cost, high yield rate, mature process technology, etc. Metal oxide TFT (IGZO-TFT) technology has gradually developed, and its field effect mobility is 20 to 30 times that of a-Si TFT, which can achieve ultra-high resolution. At the same time, it has the advantages of small leakage current and low temperature process, and is widely favored in industrial production.

[0003] like Figure 1 The structure of the TFT array substrate 100' in the prior art is shown. The display area (AA area) of the array substrate 100' generally adopts a 7MaskMid-Com architecture. The structure of the display area of ​​the array substrate 100' includes, from bottom to top, a substrate 1', a gate metal layer 2', a gate insulating layer 3', a semiconductor layer 4', a source-drain electrode layer 5', a passivation layer 6', a common electrode layer 7', a planar layer 8' and a pixel electrode layer 9'. The gate metal layer 2' usually uses a three-layer metal structure of Mo / Al / Mo, in which the metal Al will expand due to high temperature in the subsequent process, thereby forming a bulge. In severe cases, the top Mo of the gate metal layer 2' and the gate insulation layer 3' will be broken, resulting in a short circuit between the gate metal layer 2' and the source and drain electrode layer 5'. In addition, in the structure of the existing array substrate 100', there is a flat layer 8' between the pixel electrode layer 9' and the common electrode layer 7'. In actual production, such as Figure 2 As shown, the metal Taper angle α of the gate metal layer 2' is generally difficult to control below 60°. When α of the gate metal layer 2' is greater than 90° to form an obtuse angle, the metal coverage of the gate insulating layer 3' on the gate metal layer 2' becomes poor, and cracks are easily formed in the gate insulating layer 3' at the Taper angle. When the source 51' metal (source) (data line) in the source-drain electrode layer 5' climbs the gate metal layer 2' Taper, it is easy to cause a short circuit between the gate metal layer 2' and the source-drain electrode layer 5' due to poor film morphology at the climbing location and cracks in the gate insulating layer 3', and the source routing is very likely to be broken due to abnormal climbing, which will cause defects such as bright spots and reduce the production yield. Summary of the invention

[0004] The technical problem to be solved by the utility model is to provide a TFT-LCD array substrate structure, which can effectively reduce the risk of metal short circuit between the gate metal layer and the source and drain electrode layer, and reduce an insulating layer coating and mask process, thereby reducing production costs.

[0005] The utility model is implemented as follows: a TFT-LCD array substrate structure for reducing the risk of metal short circuit, which is divided into a display area and a non-display area, wherein the display area structure comprises a substrate, a gate metal layer is patterned on the substrate, an ITO film layer is plated on the gate metal layer, and through yellow light and etching processes, part of the ITO film layer is located above the gate metal layer and covers the gate metal layer to form a protective layer, and another part of the ITO film layer is located on the substrate and is designed to be in the same layer as the gate metal layer to form a pixel electrode layer; a gate insulating layer is formed above the ITO film layer by a PECVD process, and a connection hole is opened on the gate insulating layer, the connection hole is located above the pixel electrode layer and exposes the pixel electrode layer; a semiconductor layer, a source-drain electrode layer, a passivation layer and a common electrode layer are sequentially prepared above the gate insulating layer, the source and drain electrodes of the source-drain electrode layer are both overlapped with the semiconductor layer, and the source electrode is also overlapped with the pixel electrode layer through the connection hole.

[0006] Furthermore, the gate insulating layer is SiOx.

[0007] Furthermore, the passivation layer is an insulating material.

[0008] Furthermore, the semiconductor layer is IGZO.

[0009] Furthermore, the source-drain electrode layer is Mo, Mo / Al / Mo or Ti / Al / Ti.

[0010] The advantages of the utility model are as follows: the utility model plates an ITO film layer on the gate metal layer. Since the ITO film layer is plated by magnetron sputtering (PVD), its density and hardness far exceed the original gate insulating layer. A protective layer is formed outside the gate metal layer, which can effectively reduce the risk that Al in the gate metal layer will expand due to heat in the subsequent thermal process, causing bulges, and the gate insulating layer will be broken, resulting in a metal short circuit between the gate metal layer and the source and drain electrode layer. When the ITO film layer is plated, a pixel electrode layer is prepared at the same time, which is designed on the same layer as the gate metal layer. Subsequently, a hole is formed in the gate insulating layer through a hole-opening process, so that the source and drain electrode layer metal is connected to the pixel electrode layer. This method reduces one insulating layer plating and mask process, thereby reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0012] Figure 1 The figure is a schematic diagram of the display area structure of a TFT-LCD array substrate in the prior art.

[0013] Figure 2The present invention is a schematic diagram of the Taper angle structure of the gate metal layer in the display area of ​​the TFT-LCD array substrate in the prior art.

[0014] Figure 3 The utility model is a schematic diagram of an ITO film layer structure plated in a display area of ​​a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0015] Figure 4 The utility model is a schematic diagram of a gate insulating layer opening structure in a display area of ​​a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0016] Figure 5 The utility model is a schematic diagram of the display area structure of a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0017] Explanation of the accompanying drawings: array substrate 100', substrate 1', gate metal layer 2', gate insulating layer 3', semiconductor layer 4', source-drain electrode layer 5', source 51', passivation layer 6', common electrode layer 7', flat layer 8', pixel electrode layer 9', Taper angle α, array substrate 100, substrate 1, gate metal layer 2, ITO film layer 3, protective layer 31, pixel electrode layer 32, gate insulating layer 4, connection hole 41, semiconductor layer 5, source-drain electrode layer 6, source 61, drain 62, passivation layer 7, common electrode layer 8. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0019] like Figures 3 to 5As shown, a TFT-LCD array substrate 100 structure for reducing the risk of metal short circuit is divided into a display area and a non-display area. The display area structure includes a substrate 1, a gate metal layer 2 is prepared on the substrate 1 by a PVD process, and then the gate metal layer 2 is subjected to a yellow light and etching process to form a pattern, and the film quality of the gate metal layer 2 is Mo / Al / Mo; an ITO film layer 3 is plated on the gate metal layer 2 by a magnetron sputtering (PVD) method, and through a yellow light and etching process, a part of the ITO film layer 3 is located above the gate metal layer 2 and covers the gate metal layer 2 to form a protective layer 31, and another part of the ITO film layer 3 is located on the substrate 1 and is designed to be in the same layer as the gate metal layer 2 to form a pixel electrode layer 32; a gate insulating layer 4 is formed above the ITO film layer 3 by a PECVD process, and the gate insulating layer 4 is SiOx or SiNx. A connection hole 41 is formed on the gate insulating layer 4 by a hole-forming process, and the connection hole 41 is located above the pixel electrode layer 32 and exposes the pixel electrode layer 32; a semiconductor layer 5, a source-drain electrode layer 6, a passivation layer 7 and a common electrode layer 8 are sequentially prepared above the gate insulating layer 4, and the passivation layer 7 is an insulating material, and the source 61 and the drain 62 of the source-drain electrode layer 6 are both overlapped on the semiconductor layer 5, and the source 61 is also overlapped with the pixel electrode layer 32 through the connection hole 41. The semiconductor layer is IGZO. The source-drain electrode layer 6 is Mo, Mo / Al / Mo or Ti / Al / Ti.

[0020] The utility model plates an ITO film layer 3 on the gate metal layer 2. Since the ITO film layer 3 is plated by magnetron sputtering (PVD), its density and hardness far exceed those of the gate insulating layer. A protective layer 31 is formed on the outside of the gate metal layer 2, which can effectively reduce the risk that the Al in the gate metal layer 2 expands due to heat during the subsequent thermal process and causes a bulge, which breaks the gate insulating layer 4 and causes a metal short circuit between the gate metal layer 2 and the source-drain electrode layer 6. When the ITO film layer 3 is plated, a pixel electrode layer 32 is prepared at the same time, which is designed on the same layer as the gate metal layer 2. Subsequently, a connection hole 41 is formed in the gate insulating layer 4 through a hole-opening process, so that the metal of the source-drain electrode layer 6 is connected to the pixel electrode layer 32. This method reduces the plating and masking processes of a flat layer, thereby reducing production costs.

[0021] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A TFT-LCD array substrate structure for reducing the risk of metal short circuit, which is divided into a display area and a non-display area, wherein the display area structure comprises a substrate, and a gate metal layer is patterned on the substrate, characterized in that: An ITO film layer is plated on the gate metal layer in the display area, and through yellow light and etching processes, part of the ITO film layer is located above the gate metal layer and covers the gate metal layer to form a protective layer, and another part of the ITO film layer is located on the substrate and is designed to be on the same layer as the gate metal layer to form a pixel electrode layer; A gate insulating layer is formed above the ITO film layer by using a PECVD process, and a connection hole is provided on the gate insulating layer, wherein the connection hole is located above the pixel electrode layer and exposes the pixel electrode layer; A semiconductor layer, a source-drain electrode layer, a passivation layer and a common electrode layer are sequentially prepared above the gate insulating layer. The source and drain of the source-drain electrode layer are both overlapped with the semiconductor layer, and the source is also overlapped with the pixel electrode layer through the connection hole.

2. The TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, characterized in that: The gate insulating layer is SiOx.

3. The TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, characterized in that: The passivation layer is made of insulating material.

4. The TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, characterized in that: The semiconductor layer is IGZO.

5. The TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, characterized in that: The source-drain electrode layer is Mo, Mo / Al / Mo or Ti / Al / Ti.

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