Electrostatic discharge protection structure and chip

Abstract

The utility model discloses an electrostatic discharge protection structure and a chip, and belongs to the technical field of integrated circuits. The electrostatic discharge protection structure comprises a substrate; the first drain region, the first source region and the second drain region are formed on the first side of the substrate in the first direction; the first grid electrode is arranged on the first side of the substrate, at least part of orthographic projection of the first grid electrode on the substrate is located between the first drain region and the first source region, and the first grid electrode, the first drain region and the first source region form a first pull-down tube; the second grid electrode is arranged on the first side of the substrate, at least part of orthographic projection of the second grid electrode on the substrate is located between the first source region and the second drain region, and the second grid electrode, the second drain region and the first source region form a discharge tube; the conductive structure is electrically connected with the first drain region and the second grid respectively; the first source region is used for being electrically connected with a grounding node, and the second drain region is used for being electrically connected with a discharge node. By shortening the routing, the routing resistance between the pull-down tube and the discharge tube and the stray capacitance between the routing are reduced, and the pull-down capability is improved.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit technology, and in particular, relates to an electrostatic discharge protection structure and a chip. Background Art

[0002] In order to prevent the chip pins from being affected by human static electricity, N-type metal oxide semiconductor devices (NMOS) are usually selected as discharge tubes for power pins, and the electrostatic discharge circuit is formed based on the resistor and capacitor triggering the NMOS tube to discharge static electricity. However, if there are burrs on the power pins and the voltage jumps up and down, it is easy to pull up the gate voltage of the NMOS, making the discharge tube conductive, so that when the chip is working normally, there is a path between the chip power supply and the ground.

[0003] At present, in order to prevent the discharge tube from being mis-conducted due to voltage glitches, a pull-down tube is usually added to the electrostatic discharge circuit to stabilize the gate voltage of the NMOS tube at a lower voltage. However, the wiring between the pull-down tube and the NMOS tube is usually long, which reduces the pull-down capability. Utility Model Content

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a technical field of integrated circuits, in which the wiring distance between the pull-down tube and the discharge tube is short, the wiring resistance between the pull-down tube and the discharge tube is reduced, and the parasitic capacitance formed by the wiring between the pull-down tube and the discharge tube and the substrate or the metal wire of other circuits is reduced, thereby improving the pull-down capability.

[0005] In a first aspect, the present application provides an electrostatic discharge protection structure, comprising:

[0006] substrate;

[0007] A first drain region, a first source region, and a second drain region formed on a first side of the substrate along a first direction;

[0008] A first gate is disposed on a first side of the substrate, an orthographic projection of the first gate on the substrate is at least partially located between the first drain region and the first source region, and the first gate, the first drain region and the first source region form a first pull-down tube;

[0009] A second gate is disposed on the first side of the substrate, an orthographic projection of the second gate on the substrate is at least partially located between the first source region and the second drain region, and the second gate, the second drain region and the first source region form a discharge tube;

[0010] A conductive structure electrically connected to the first drain region and the second gate, respectively;

[0011] The first source region is used to be electrically connected to the ground node, and the second drain region is used to be electrically connected to the discharge node.

[0012] According to the electrostatic discharge protection structure of the present application, the first drain region, the first gate and the first source region form a pull-down tube, the first source region, the second gate and the second drain region form a discharge tube, the pull-down tube and the discharge tube are formed on the same substrate and share the source region, so that the wiring distance between the pull-down tube and the discharge tube can be shortened, the wiring resistance between the pull-down tube and the discharge tube is reduced, and the parasitic capacitance formed by the wiring between the pull-down tube and the discharge tube and the metal wire of the substrate or other circuits is reduced, thereby improving the pull-down capability.

[0013] According to one embodiment of the present application, the conductive structure includes:

[0014] A first conductive member is located in a first conductive layer, the first conductive layer is located on a first side of the substrate and is electrically connected to the substrate, and the first conductive member is arranged around an active area of ​​the substrate in an orthographic projection of the substrate;

[0015] A second conductive member is located in the first conductive layer, the orthographic projection of the second conductive member on the substrate is located in the active region, and is electrically connected to the first drain region;

[0016] A third conductive member is located in the first conductive layer and on a side of the first conductive member away from the active region, and the third conductive member is electrically connected to the second gate;

[0017] The fourth conductive element is located in the second conductive layer and on a side of the first conductive layer away from the substrate. The fourth conductive element is electrically connected to the second conductive element and the third conductive element through contact holes.

[0018] According to one embodiment of the present application, the electrostatic discharge protection structure further includes:

[0019] A plurality of doped semiconductor regions are arranged along the first direction on a side of the second drain region away from the first source region and located in the active region, wherein the doping type of the doped semiconductor regions is opposite to the doping type of the substrate;

[0020] A plurality of third gates are provided on the first side of the substrate and arranged between two adjacent doped semiconductor regions along the first direction. The third gates are electrically connected to the third conductive member. Each third gate and the two adjacent doped semiconductor regions form a discharge tube.

[0021] According to one embodiment of the present application, the conductive structure further includes:

[0022] A fifth conductive member is located in the first conductive layer and between the first conductive member and the active region, and the fifth conductive member is electrically connected to the second gate and the third gate through the contact hole;

[0023] At least one sixth conductive element is located in the second conductive layer and is electrically connected to the fifth conductive element and the third conductive element through the contact holes.

[0024] According to an embodiment of the present application, the third conductive member and the fifth conductive member both extend along the first direction, the second conductive member, the fourth conductive member and the sixth conductive member all extend along the second direction, and the first direction is perpendicular to the second direction.

[0025] According to one embodiment of the present application, the number of sixth conductive members is one, and the connection portions between the fifth conductive member and the second gate and the third gate are arranged on a side of the connection portion between the sixth conductive member and the fifth conductive member away from the first end of the fifth conductive member, and the first end of the fifth conductive member is an end close to the first gate.

[0026] According to an embodiment of the present application, there are multiple sixth conductive elements, and each sixth conductive element is symmetrically arranged relative to the center line of the third conductive element.

[0027] According to one embodiment of the present application, the electrostatic discharge protection structure further includes:

[0028] a fourth gate, disposed on the first side of the substrate and located on a side of the reference doped semiconductor region far from the second drain region, the reference doped semiconductor region being the doped semiconductor region farthest from the second drain region;

[0029] The third drain region is formed on the first side of the substrate and is located on the side of the fourth gate away from the reference doped semiconductor region. The third drain region is electrically connected to the third conductive member. The fourth gate, the third drain region and the reference doped semiconductor region form a second pull-down tube.

[0030] According to one embodiment of the present application, the electrostatic discharge protection structure further includes:

[0031] a fifth gate, disposed on the first side of the substrate and located on a side of the first drain region away from the first gate;

[0032] The second source region is formed on the first side of the substrate and is located on the side of the fifth gate away from the first drain region. The fifth gate, the second source region and the first drain region form a third pull-down tube.

[0033] In a second aspect, the present application provides a chip comprising the aforementioned electrostatic discharge protection structure.

[0034] According to the chip of the present application, the first drain region, the first gate region and the first source region in the electrostatic discharge protection structure form a pull-down tube, the first source region, the second gate region and the second drain region form a discharge tube, and the pull-down tube and the discharge tube are formed on the same substrate and share the source region, which can shorten the wiring distance between the pull-down tube and the discharge tube, reduce the wiring resistance between the pull-down tube and the discharge tube, and reduce the parasitic capacitance formed by the wiring between the pull-down tube and the discharge tube and the metal wire of the substrate or other circuits, thereby improving the pull-down capability.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 It is one of the schematic diagrams of an electrostatic discharge circuit in the related art;

[0038] Figure 2 This is the second schematic diagram of an electrostatic discharge circuit in the related art;

[0039] Figure 3 It is one of the schematic diagrams of the electrostatic discharge protection structure provided in the embodiment of the present application;

[0040] Figure 4 This is the second schematic diagram of the electrostatic discharge protection structure provided in the embodiment of the present application;

[0041] Figure 5 This is the third schematic diagram of the electrostatic discharge protection structure provided in the embodiment of the present application.

[0042] Reference numerals:

[0043] Substrate 110, first drain region 121, second drain region 122, third drain region 123, first source region 131, second source region 132, first gate 141, second gate 142, third gate 143, fourth gate 144, fifth gate 145, conductive structure 150, first conductive member 151, second conductive member 152, third conductive member 153, fourth conductive member 154, fifth conductive member 155, sixth conductive member 156, doped semiconductor region 160, reference doped semiconductor region 161, resistor R, capacitor C, discharge tube Q, first pull-down tube S1. DETAILED DESCRIPTION

[0044] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0045] In the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "coupled to" or "connected to" another element or an element / circuit is said to be "coupled to" or "connected to" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0046] In the description, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the numerical descriptors used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0047] In addition, descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0048] Reference Figure 1 In order to prevent the chip pins from being affected by human static electricity, for the power pins, NMOS tubes are usually selected as discharge tubes Q. Based on the resistor R and capacitor C, the NMOS tube is triggered to form an electrostatic discharge circuit to discharge static electricity. The first end of capacitor C is electrically connected to the drain of the discharge tube Q, the second end of capacitor C is electrically connected to the gate of the discharge tube Q, the first end of resistor R is electrically connected to the second end of capacitor C, and the second end of resistor R is electrically connected to the discharge node. When the static electricity on the power pin is large, capacitor C is charged, and the voltage of the gate of the discharge tube Q is pulled up, so that the discharge tube Q is turned on and the voltage of capacitor C is discharged to the discharge node. However, if there are glitches on the power pin and the voltage jumps up and down, it is easy to pull up the gate voltage of the NMOS tube, so that the discharge tube Q is turned on, resulting in a path between the chip power supply and the ground when the chip is working normally.

[0049] Reference Figure 2In the related art, in order to avoid voltage glitches causing mis-conduction of the discharge tube Q, a first pull-down tube S1 is usually added to the electrostatic discharge circuit to stabilize the gate voltage of the NMOS tube at a lower voltage. However, the wiring between the first pull-down tube S1 and the NMOS tube is usually long, the wiring resistance is large, and parasitic capacitance is formed between the wiring between the first pull-down tube S1 and the NMOS tube and the metal wires of the substrate 110 and other circuits. The parasitic capacitance will interfere with each other and reduce the pull-down capability.

[0050] Reference Figure 3 An embodiment of the present application proposes an electrostatic discharge protection structure, including: a substrate 110, a first drain region 121 formed on a first side of the substrate 110 along a first direction, a first source region 131, a second drain region 122, a first gate 141, a second gate 142 and a conductive structure 150. The first gate 141 is arranged on the first side of the substrate 110, and the orthographic projection of the first gate 141 on the substrate 110 is at least partially located between the first drain region 121 and the first source region 131, and the first gate 141, the first drain region 121 and the first source region 131 form a first pull-down tube S1; the second gate 142 is arranged on the first side of the substrate 110, and the orthographic projection of the second gate 142 on the substrate 110 is at least partially located between the first source region 131 and the second drain region 122, and the second gate 142, the second drain region 122 and the first source region 131 form a discharge tube; the conductive structure 150 is electrically connected to the first drain region 121 and the second gate 142 respectively; wherein the first source region 131 is used to be electrically connected to the ground node, and the second drain region 122 is used to be electrically connected to the discharge node.

[0051] The substrate 110 may be formed of a P-type silicon semiconductor material. A plurality of N-type doped regions are formed along a first direction on a first side of the substrate 110, namely a first drain region 121, a first source region 131, and a second drain region 122. The first direction may be the X direction shown in the figure.

[0052] The first gate 141 and the second gate 142 may be formed respectively on the first side of the substrate 110 by photolithography and etching techniques. The first gate 141 and the second gate 142 may be made of materials such as metal or polysilicon.

[0053] The orthographic projection of the first gate 141 on the substrate 110 is at least partially located between the first drain region 121 and the first source region 131. The first drain region 121, the first gate 141 and the first source region 131 form a first pull-down tube S1. The first source region 131 forms the source of the first pull-down tube S1, and the first drain region 121 forms the drain of the first pull-down tube S1. The orthographic projection of the second gate 142 on the substrate 110 is at least partially located between the first source region 131 and the second drain region 122. The first source region 131, the second gate 142 and the second drain region 122 form a discharge tube Q. The first source region 131 forms the source of the discharge tube Q, and the second drain region 122 forms the drain of the discharge tube Q.

[0054] The first drain region 121, the first source region 131, the second drain region 122, the first gate 141 and the second gate 142 are all formed on the first side of the substrate 110, that is, the first pull-down tube S1 and the discharge tube Q are formed on the same substrate 110. The first source region 131 is used to form both the source of the first pull-down tube S1 and the source of the discharge tube Q, that is, the first pull-down tube S1 and the discharge tube Q share a source.

[0055] The electrostatic discharge protection structure is electrically connected to the power pin, the drain of the first pull-down tube S1 and the gate of the discharge tube Q are electrically connected through the conductive structure 150, the source of the first pull-down tube S1 is used to be electrically connected to the ground node, and the drain of the discharge tube Q is used to be electrically connected to the discharge node.

[0056] The discharge node can be a ground node. When the power signal changes, the first pull-down tube S1 is turned on, and the gate voltage of the discharge tube Q is maintained at a lower voltage, so that the discharge tube Q remains turned off. When the static electricity of the power pin is large, the first pull-down tube S1 is turned off, the discharge tube Q is turned on, and the static electricity is discharged to the discharge node through the discharge tube Q. That is, the static electricity discharge of the power pin can be achieved, and the discharge tube Q can be prevented from being turned on by mistake when the chip is working normally due to the change of the power signal.

[0057] According to the electrostatic discharge protection structure of the present application, the first drain region 121, the first gate 141 and the first source region 131 form a first pull-down tube S1, the first source region 131, the second gate 142 and the second drain region 122 form a discharge tube Q, and the first pull-down tube S1 and the discharge tube Q are formed on the same substrate 110 and share the source region, which can shorten the wiring distance between the first pull-down tube S1 and the discharge tube Q, reduce the wiring resistance between the first pull-down tube S1 and the discharge tube Q, and reduce the parasitic capacitance formed by the wiring between the first pull-down tube S1 and the discharge tube Q and the substrate 110 or the metal wire of other circuits, thereby improving the pull-down capability.

[0058] Reference Figure 4In some embodiments, the conductive structure 150 includes: a first conductive member 151, a second conductive member 152, a third conductive member 153, and a fourth conductive member 154. The first conductive member 151 is located in the first conductive layer, the first conductive layer is located on the first side of the substrate 110, and is electrically connected to the substrate 110. The orthographic projection of the first conductive member 151 on the substrate 110 is arranged around the active region of the substrate 110; the second conductive member 152 is located in the first conductive layer, the orthographic projection of the second conductive member 152 on the substrate 110 is located in the active region, and is electrically connected to the first drain region 121; the third conductive member 153 is located in the first conductive layer, and is located on the side of the first conductive member 151 away from the active region, and the third conductive member 153 is electrically connected to the second gate 142; the fourth conductive member 154 is located in the second conductive layer, and is located on the side of the first conductive layer away from the substrate 110, and the fourth conductive member 154 is electrically connected to the second conductive member 152 and the third conductive member 153 through contact holes.

[0059] The first conductive member 151, the second conductive member 152, the third conductive member 153 and the fourth conductive member 154 are mainly used to realize the electrical connection of each part in the electrostatic discharge protection structure. The first conductive member 151, the second conductive member 152, the third conductive member 153 and the fourth conductive member 154 can all be formed of metal materials. The specific materials of the first conductive member 151, the second conductive member 152, the third conductive member 153 and the fourth conductive member 154 can be selected according to the actual application scenario and are not limited here. For example, the first conductive member 151, the second conductive member 152, the third conductive member 153 and the fourth conductive member 154 can all be formed of copper.

[0060] The active area of ​​the substrate 110 includes drain regions, source regions, and gates that form the first pull-down tube S1 and the discharge tube Q. The first conductive member 151 is mainly used to connect the substrate 110 of each first pull-down tube S1 and the discharge tube Q. The second conductive member 152 and the third conductive member 153 electrically connect the first drain region 121 and the second gate 142 through the fourth conductive member 154, that is, the electrical connection of the drain of the first pull-down tube S1 and the gate of the discharge tube Q is realized. The source and drain of the pull-down tube and the discharge tube can be electrically connected to the substrate through the second conductive member.

[0061] The third conductive member 153 is located on a side of the first conductive member 151 away from the active region, so that the active region is closer to the first conductive member 151 in all directions, thereby reducing the resistance between the first pull-down tube S1 and the discharge tube Q and the substrate 110, and reducing the latching risk of devices around the active region.

[0062] Continue to refer to Figure 4In some embodiments, the electrostatic discharge protection structure further includes: a plurality of doped semiconductor regions 160 and a plurality of third gates 143. The plurality of doped semiconductor regions 160 are arranged along the first direction on a side of the second drain region 122 away from the first source region 131 and are located in the active region. The doping type of the doped semiconductor region 160 is opposite to the doping type of the substrate 110. The plurality of third gates 143 are provided on the first side of the substrate 110 and are arranged between two adjacent doped semiconductor regions 160 along the first direction. The third gates 143 are electrically connected to the third conductive member 153. Each third gate 143 and the two adjacent doped semiconductor regions 160 form a discharge tube.

[0063] It should be noted that, due to the limitation of device size, a plurality of discharge tubes Q are usually connected in parallel and then electrically connected to the first pull-down tube S1.

[0064] As an example, the total width of the active area is 480 um, and the width of a single discharge tube Q is 30 um, so 16 discharge tubes Q need to be connected in parallel and electrically connected to the first pull-down tube S1.

[0065] The substrate 110 may be formed of a P-type silicon semiconductor material, and an N-type doped material may be introduced into the doped semiconductor region 160. The multiple doped semiconductor regions 160 form multiple source regions and multiple drain regions, and the drain regions and the source regions are arranged in sequence. A third gate 143 is formed between each drain region and the source region, and the third gate 143 and the doped semiconductor regions 160 on both sides thereof form a discharge tube Q.

[0066] The third grid 143 is electrically connected to the third conductive member 153, that is, the grids of the discharge tubes Q are connected in parallel through the third conductive member 153. The fourth conductive member 154 is electrically connected to the second conductive member 152 and the third conductive member 153 through the contact hole, so the grids of the discharge tubes Q are connected in parallel and electrically connected to the drain of the first pull-down tube S1.

[0067] In some embodiments, the conductive structure 150 further includes: a fifth conductive member 155 and at least one sixth conductive member 156. The fifth conductive member 155 is located in the first conductive layer and between the first conductive member 151 and the active region, and the fifth conductive member 155 is electrically connected to the second gate 142 and the third gate 143 through the contact hole; the sixth conductive member 156 is located in the second conductive layer and is electrically connected to the fifth conductive member 155 and the third conductive member 153 through the contact hole.

[0068] The second grid 142 and the third grid 143 are connected together through the fifth conductive member 155, so that the grids of the discharge tubes Q are connected in parallel. The second grid 142 and the third grid 143 are electrically connected to the third conductive member 153 through the sixth conductive member 156, and the third conductive member 153 is electrically connected to the drain of the first pull-down tube S1. Therefore, the grids of the discharge tubes Q are connected in parallel and are electrically connected to the drain of the first pull-down tube S1, so that when the first pull-down tube S1 is turned on, the grid voltage of the discharge tube Q is maintained at a relatively low voltage.

[0069] In some embodiments, the third conductive member 153 and the fifth conductive member 155 extend along a first direction, the second conductive member 152 , the fourth conductive member 154 and the sixth conductive member 156 extend along a second direction, and the first direction is perpendicular to the second direction.

[0070] The second direction may be the Y direction shown in the figure.

[0071] Each third gate 143 is arranged along the first direction, and the fifth conductive member 155 extends along the first direction. Each third gate 143 is electrically connected to the fifth conductive member 155 through a contact hole, shortening the wiring between the third gate 143 and the fifth conductive member 155, and reducing the parasitic capacitance generated between the conductive members of the same layer. The sixth conductive member 156 extends along the second direction, connecting the third conductive member 153 and the fifth conductive member 155 extending along the first direction, shortening the wiring distance connecting the third conductive member 153 and the fifth conductive member 155, reducing the wiring resistance and parasitic capacitance, and improving the pull-down capability.

[0072] In some embodiments, the number of the sixth conductive member 156 is one, and the connection portions between the fifth conductive member 155 and the second gate 142 and the third gate 143 are located on the side of the connection portion between the sixth conductive member 156 and the fifth conductive member 155 away from the first end of the fifth conductive member 155, and the first end of the fifth conductive member 155 is an end close to the first gate 141.

[0073] The sixth conductive member 156 is used to connect the third conductive member 153 and the fifth conductive member 155. The connection parts between the fifth conductive member 155 and the second grid 142 and the third grid 143 are located on a side of the connection part between the sixth conductive member 156 and the fifth conductive member 155 away from the first end of the fifth conductive member 155, ensuring that the grids of the discharge tubes Q are electrically connected to the third conductive member 153 through the sixth conductive member 156 after being connected in parallel.

[0074] In some embodiments, there are multiple sixth conductive elements 156 , and each sixth conductive element 156 is symmetrically arranged relative to the center line of the third conductive element 153 .

[0075] The specific number of the sixth conductive members 156 is not limited here, and can be selected according to the actual application scenario. For example, there can be two sixth conductive members 156, which are arranged at the first end and the second end of the fifth conductive member 155 respectively.

[0076] The sixth conductive members 156 are symmetrically arranged relative to the center line of the third conductive member 153, so that the electrostatic discharge protection structure as a whole is a symmetrical structure, which can keep the discharge performance of each discharge tube Q consistent and improve the discharge capacity.

[0077] In some embodiments, the electrostatic discharge protection structure further includes: a fourth gate 144 and a third drain region 123. The fourth gate 144 is disposed on the first side of the substrate 110 and is located on the side of the reference doped semiconductor region 161 away from the second drain region 122, and the reference doped semiconductor region 161 is the doped semiconductor region 160 farthest from the second drain region 122; the third drain region 123 is formed on the first side of the substrate 110 and is located on the side of the fourth gate 144 away from the reference doped semiconductor region 161, the third drain region 123 is electrically connected to the third conductive member 153, and the fourth gate 144, the third drain region 123 and the reference doped semiconductor region 161 form a second pull-down tube.

[0078] The third drain region 123 forms the drain of the second pull-down tube, and the reference doped semiconductor region 161 forms the source of the second pull-down tube. The drain of the second pull-down tube is electrically connected to the gate of each discharge tube Q through the third conductive member 153.

[0079] The second pull-down tube and the first pull-down tube are symmetrically distributed in the middle of the active area, so that the electrostatic discharge protection structure is symmetrical with the midline as the symmetry axis. When the power supply is negative relative to the ground node voltage, the drain end of the discharge tube Q forms a parasitic diode with the substrate 110 respectively, and this parasitic diode is forward-conducted to discharge the negative electricity to the ground. When the power supply is positive relative to the ground node voltage, the capacitor C will pull up the gate voltage of the discharge tube Q, so that the discharge tube Q is turned on and the positive electricity is quickly discharged to the discharge node. Since the electrostatic discharge protection structure is symmetrical in the middle with respect to the substrate 110, the discharge performance of each discharge tube Q remains consistent.

[0080] Reference Figure 5 In some embodiments, the electrostatic discharge protection structure further includes: a fifth gate 145 and a second source region 132. The fifth gate 145 is disposed on the first side of the substrate 110 and is located on the side of the first drain region 121 away from the first gate 141; the second source region 132 is formed on the first side of the substrate 110 and is located on the side of the fifth gate 145 away from the first drain region 121, and the fifth gate 145, the second source region 132 and the first drain region 121 form a third pull-down tube.

[0081] The third pull-down tube and the first pull-down tube are arranged on the same side of the discharge tube Q. The source end of the first pull-down tube and the source end of the discharge tube Q are both close to the first conductive member 151, so that the resistance between the pull-down tube and the discharge tube Q and the substrate 110 is small, thereby improving the discharge capacity.

[0082] An embodiment of the present application provides a chip, which includes the aforementioned electrostatic discharge protection structure.

[0083] The electrostatic discharge protection structure is electrically connected to the power pin of the chip to discharge the static electricity of the power pin and protect the internal components of the chip.

[0084] According to the chip of the present application, the first drain region 121, the first gate 141 and the first source region 131 in the electrostatic discharge protection structure form a pull-down tube, the first source region 131, the second gate 142 and the second drain region 122 form a discharge tube Q, and the pull-down tube and the discharge tube Q are formed on the same substrate 110 and share the source region, which can shorten the wiring distance between the pull-down tube and the discharge tube Q, reduce the wiring resistance between the pull-down tube and the discharge tube Q, and reduce the parasitic capacitance formed by the wiring between the pull-down tube and the discharge tube Q and the substrate 110 or the metal wire of other circuits, thereby improving the pull-down capability.

[0085] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. An electrostatic discharge protection structure, characterized in that: include: substrate; A first drain region, a first source region, and a second drain region formed on a first side of the substrate along a first direction; A first gate is disposed on a first side of the substrate, an orthographic projection of the first gate on the substrate is at least partially located between the first drain region and the first source region, and the first gate, the first drain region and the first source region form a first pull-down tube; a second gate, disposed on the first side of the substrate, wherein an orthographic projection of the second gate on the substrate is at least partially located between the first source region and the second drain region, and the second gate, the second drain region and the first source region form a discharge tube; a conductive structure electrically connected to the first drain region and the second gate, respectively; The first source region is used to be electrically connected to a ground node, and the second drain region is used to be electrically connected to a discharge node.

2. The electrostatic discharge protection structure according to claim 1, characterized in that: The conductive structure comprises: A first conductive member is located in a first conductive layer, the first conductive layer is located on a first side of the substrate and is electrically connected to the substrate, and the first conductive member is arranged around an active area of ​​the substrate in an orthographic projection of the substrate; A second conductive member is located in the first conductive layer, the orthographic projection of the second conductive member on the substrate is located in the active region, and is electrically connected to the first drain region; A third conductive member is located in the first conductive layer and on a side of the first conductive member away from the active region, and the third conductive member is electrically connected to the second gate; The fourth conductive member is located in the second conductive layer and on a side of the first conductive layer away from the substrate. The fourth conductive member is electrically connected to the second conductive member and the third conductive member through contact holes.

3. The electrostatic discharge protection structure according to claim 2, characterized in that: The electrostatic discharge protection structure also includes: a plurality of doped semiconductor regions, arranged along the first direction on a side of the second drain region away from the first source region and located in the active region, wherein the doping type of the doped semiconductor regions is opposite to the doping type of the substrate; A plurality of third gates are provided on the first side of the substrate and arranged between two adjacent doped semiconductor regions along the first direction. The third gates are electrically connected to the third conductive member. Each of the third gates and the two adjacent doped semiconductor regions form a discharge tube.

4. The electrostatic discharge protection structure according to claim 3, characterized in that: The conductive structure further comprises: a fifth conductive member, located in the first conductive layer and between the first conductive member and the active region, the fifth conductive member being electrically connected to the second gate and the third gate through a contact hole; At least one sixth conductive element is located in the second conductive layer and is electrically connected to the fifth conductive element and the third conductive element through contact holes.

5. The electrostatic discharge protection structure according to claim 4, characterized in that: The third conductive element and the fifth conductive element both extend along the first direction, the second conductive element, the fourth conductive element and the sixth conductive element all extend along the second direction, and the first direction is perpendicular to the second direction.

6. The electrostatic discharge protection structure according to claim 5, characterized in that: The number of the sixth conductive member is one, and the connection parts between the fifth conductive member and the second gate and the third gate are arranged on a side of the connection part between the sixth conductive member and the fifth conductive member away from the first end of the fifth conductive member, and the first end of the fifth conductive member is an end close to the first gate.

7. The electrostatic discharge protection structure according to claim 5, characterized in that: There are multiple sixth conductive elements, and each of the sixth conductive elements is symmetrically arranged relative to the center line of the third conductive element.

8. The electrostatic discharge protection structure according to any one of claims 3 to 7, characterized in that: The electrostatic discharge protection structure also includes: a fourth gate, disposed on the first side of the substrate and located on a side of a reference doped semiconductor region far from the second drain region, wherein the reference doped semiconductor region is the doped semiconductor region farthest from the second drain region; A third drain region is formed on the first side of the substrate and is located on a side of the fourth gate away from the reference doped semiconductor region. The third drain region is electrically connected to the third conductive member. The fourth gate, the third drain region and the reference doped semiconductor region form a second pull-down tube.

9. The electrostatic discharge protection structure according to any one of claims 3 to 7, characterized in that: The electrostatic discharge protection structure also includes: a fifth gate, disposed on the first side of the substrate and located on a side of the first drain region away from the first gate; The second source region is formed on the first side of the substrate and is located on a side of the fifth gate away from the first drain region. The fifth gate, the second source region and the first drain region form a third pull-down tube.

10. A chip, characterized in that: The chip comprises an electrostatic discharge protection structure according to any one of claims 1-9.

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