Low-inductance power module

Abstract

The utility model discloses a low-inductance power module, which comprises an insulating shell, a heat dissipation bottom plate and a plurality of power conversion units, and is characterized in that the heat dissipation bottom plate is connected with the insulating shell; the plurality of power conversion units are arranged on the heat dissipation bottom plate, each power conversion unit comprises a substrate, a plurality of copper clamps and a plurality of chips, the front surfaces of the plurality of chips are provided with source electrodes and are respectively connected with the first conductive layer through the copper clamps, and the back surfaces of the plurality of chips are provided with drain electrodes and are connected with the second conductive layer; grid electrodes of a plurality of chips are connected with the third conductive layer through metal leads, the adopted chips are metal oxide semiconductor field effect transistors, source electrodes of the chips adopt copper clamp structures to achieve electrical interconnection between the chips and the substrate, and compared with a connection mode of the metal leads, the copper clamps can offset more magnetic flux generated by current, so that the reliability of the device is improved. The chip and the substrate, the chip and the copper clamp, and the copper clamp and the substrate are interconnected by adopting a nano-metal sintering process, so that the thermal reliability of the interconnection part is improved, the copper clamp and nano-metal sintering process is conveniently realized through the overall layout design of the substrate, the effect of low parasitic inductance of the module is realized, and the reliability of the module is improved. And module reliability is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a low-inductance power module. Background Art

[0002] Power devices are the core of electronic power technology and play an important role in the development of power electronics technology towards high frequency and high power density. At present, the first generation of power semiconductor devices based on silicon (Si) materials dominate the market, but with the development of technology, silicon-based power semiconductors have approached the physical limit of their materials and it is difficult to meet the application requirements of today's power electronic devices for power device breakdown voltage, operating temperature, on-state characteristics and switching characteristics. As a typical representative of the third generation of semiconductor materials, silicon carbide (SiC) has a wide bandgap, high breakdown electric field, high thermal conductivity, high electron saturation rate and higher radiation resistance. It is an extremely ideal semiconductor material for high temperature, high pressure and high frequency applications.

[0003] In order to meet the application requirements of high voltage and high current in power electronic systems, a multi-SiC chip series-parallel solution is generally adopted. In the power module, the interconnected metal bodies between chips, chips and substrates, and substrates and electrical terminals have inherent parasitic parameters, such as parasitic capacitance and parasitic inductance. Among them, parasitic inductance has a more significant impact on the working performance of the power module.

[0004] At present, most commercial power modules use traditional welding and wire bonding processes. The back of the chip uses solder paste welding to achieve interconnection with the substrate, and the front of the chip uses wire bonding to achieve interconnection with the substrate and electrical terminals. Finally, the chip is electrically insulated and protected by plastic encapsulation or glue potting. Wire bonding technology is mature, low-cost and widely used, but it will introduce a large parasitic inductance, which can easily cause voltage overshoot, oscillation, electromagnetic compatibility and other problems under large di / dt, reducing the performance of the module. Utility Model Content

[0005] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the utility model proposes a low-inductance power module, which can effectively reduce parasitic inductance, improve switching characteristics, and enhance the overall performance and reliability of the power module.

[0006] According to the power module of the first aspect of the utility model, the embodiment comprises: an insulating shell, a heat dissipation base plate and a plurality of power conversion units, the heat dissipation base plate is connected to the insulating shell; the plurality of power conversion units are arranged on the heat dissipation base plate, each of the power conversion units comprises a substrate, a plurality of copper clips and a plurality of chips, the front side of the substrate is provided with a first conductive layer, a second conductive layer and a third conductive layer, the back side of the substrate is connected to the heat dissipation base plate, the front sides of the plurality of chips are provided with source electrodes and are respectively connected to the first conductive layer through the copper clips, the back sides of the plurality of chips are provided with drain electrodes and are connected to the second conductive layer, the gate electrodes of the plurality of chips are connected to the third conductive layer through metal leads, the chips are metal oxide semiconductor field effect transistors, and the plurality of chips are divided into two groups and respectively constitute an upper bridge arm and a lower bridge arm.

[0007] The power module according to the embodiment of the utility model has at least the following beneficial effects:

[0008] By arranging multiple power conversion units on a heat dissipation base plate, the heat dissipation requirements of the power module are met. Each power conversion unit constitutes a half-bridge topology circuit. The power conversion unit includes a substrate, multiple copper clips and multiple chips, wherein the back of the substrate is connected to the heat dissipation base plate, the front of the multiple chips is provided with a source electrode and is respectively connected to the first conductive layer through the copper clips, the back of the multiple chips is provided with a drain electrode and is connected to the second conductive layer, and the gates of the multiple chips are connected to the third conductive layer through metal leads. The chips used are metal oxide semiconductor field effect transistors. The multiple chips are divided into two groups, and the two groups of chips respectively constitute an upper bridge arm and a lower bridge arm, so that the circuit has a symmetrical structure, and the source of the chip adopts a copper clip structure to realize the electrical interconnection between the chip and the substrate. Compared with the connection method of the metal lead, the copper clip can offset more magnetic flux generated by the current, thereby effectively reducing the parasitic inductance of the power module and improving the module reliability.

[0009] According to some embodiments of the present invention, the first conductive layer includes a first connection layer and a second connection layer, the source electrodes of the multiple chips in the upper bridge arm are connected to the first connection layer, and the source electrodes of the multiple chips in the lower bridge arm are connected to the second connection layer, and the first connection layer and the second connection layer are respectively used to connect peripheral circuits.

[0010] According to some embodiments of the utility model, the power module also includes a first source lead terminal and a second source lead terminal, one end of the first source lead terminal is connected to the first connecting layer, and the other end is constructed to be exposed to the outside of the insulating shell; one end of the second source lead terminal is connected to the second connecting layer, and the other end is constructed to be exposed to the outside of the insulating shell.

[0011] According to some embodiments of the present invention, the power module further includes a drain lead-out terminal, one end of the drain lead-out terminal is connected to the second conductive layer, and the other end is configured to be exposed outside the insulating housing.

[0012] According to some embodiments of the present invention, the chip is a silicon carbide metal oxide semiconductor field effect transistor, each power conversion unit is provided with twelve of the chips, and the upper bridge arm and the lower bridge arm are respectively provided with six of the chips.

[0013] According to some embodiments of the present invention, the substrate is an AMB substrate, a DBC substrate or a DBA substrate, and the first conductive layer, the second conductive layer and the third conductive layer are all copper layers formed on the surface of the substrate.

[0014] According to some embodiments of the present invention, the source electrode of the chip and the copper clip, as well as the copper clip and the first conductive layer are connected respectively by metal nano-sintering.

[0015] According to some embodiments of the present invention, the drain electrode of the chip is connected to the second conductive layer by metal nano-sintering.

[0016] According to some embodiments of the present utility model, three power conversion units are provided, and the topology circuit formed by the three power conversion units is a three-phase full-bridge topology circuit.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention is further described below with reference to the accompanying drawings and embodiments, wherein:

[0019] Figure 1 This is an overall schematic diagram of a power module according to an embodiment of the utility model;

[0020] Figure 2 This is a schematic structural diagram of an insulating housing and a top cover according to an embodiment of the utility model;

[0021] Figure 3 It is a schematic diagram of the assembly of the insulating housing and the power conversion unit according to one embodiment of the utility model;

[0022] Figure 4 It is a front view schematic diagram of a power conversion unit according to an embodiment of the utility model;

[0023] Figure 5 It is a three-dimensional schematic diagram of a power conversion unit according to an embodiment of the utility model.

[0024] Figure Number:

[0025] Insulating housing 100; inner cavity 110;

[0026] Heat dissipation base plate 200;

[0027] Power conversion unit 300; upper bridge arm 301; lower bridge arm 302; substrate 310; chip 320; copper clip 330; first conductive layer 340; first connection layer 341; second connection layer 342; second conductive layer 350; third conductive layer 360; first source lead terminal 370; second source lead terminal 380; drain lead terminal 390;

[0028] Power module 1000. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0030] In the description of the present invention, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0031] In the description of the utility model, if there is a description of first and second, it is only for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0032] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0033] In the related technology, in order to meet the application requirements of high voltage and high current in power electronic systems, a multi-SiC chip series-parallel solution is generally adopted. Power modules using SiC chips are also called SiC modules. In SiC modules, there are inherent parasitic parameters such as parasitic capacitance and parasitic inductance in the interconnected metal bodies between chips, chips and substrates, and substrates and electrical terminals. Among them, parasitic inductance has a more significant impact on the working performance of power modules. The reliability of SiC modules is directly related to the safe operation of power electronic systems, and parasitic inductance is also one of the key factors affecting the reliability of power modules.

[0034] In the power system, its high operating frequency and fast switching speed make the impact of parasitic inductance on SiC modules more significant. When the SiC module is turned off, the combined effect of large parasitic inductance and high di / dt will cause the power module to generate a large overvoltage, which may exceed the safe operating range of the module in severe cases, causing the module to fail. At present, most SiC modules use wire bonding technology, which will introduce a large parasitic inductance. In addition, wire bonding failure accounts for 49% of all device failure modes and is one of the main modes of power module failure. In actual work, the power module will cause thermal fatigue of the leads and solder layers due to thermal cycles, resulting in loose or falling leads and delamination and falling off of the chip solder layer. Therefore, the optimization of parasitic inductance is crucial to reducing electromagnetic interference and other problems caused by the high di / dt of SiC modules.

[0035] In view of the large parasitic inductance problem of SiC modules in related technologies, the utility model adopts a new interconnection method and optimizes the chip layout to effectively reduce the parasitic inductance and improve the overall performance of the module.

[0036] Reference Figures 1 to 5 As shown, the power module 1000 of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It is applicable to power electronic equipment in the fields of rail transportation, industrial control, power grid transmission, photovoltaic power generation, etc. The power module 1000 is explained below with a specific example.

[0037] Reference Figure 1 , Figure 2 and Figure 3As shown, the power module 1000 of the embodiment of the utility model includes an insulating shell 100, a heat dissipation base plate 200 and a plurality of power conversion units 300, the heat dissipation base plate 200 is connected to the insulating shell 100, the plurality of power conversion units 300 are arranged in the inner cavity 110 of the insulating shell 100, and are respectively connected to the heat dissipation base plate 200, each power conversion unit 300 includes a substrate 310, a plurality of chips 320 and a plurality of copper clips 330, the plurality of chips 320 are connected to the front side of the substrate 310, and the back side of the substrate 310 is connected to the heat dissipation base plate 200, the heat generated by the chip 320 can be transferred to the heat dissipation base plate 200, and the heat is transferred to the outside through the heat dissipation base plate 200, so as to realize rapid heat dissipation of the power module 1000 and meet the heat dissipation requirements.

[0038] Reference Figure 4 As shown, specifically, the front side of the substrate 310 is provided with a first conductive layer 340, a second conductive layer 350 and a third conductive layer 360, and the first conductive layer 340, the second conductive layer 350 and the third conductive layer 360 are spaced apart and distributed on the front side of the substrate 310, wherein the first conductive layer 340 is a source conductive copper layer, the second conductive layer 350 is a drain conductive copper layer, and the third conductive layer 360 is a gate conductive copper layer. The chip 320 used in the embodiment is a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), also known as a MOSFET chip, and the MOSFET chip is provided with a source on the front side and a drain on the back side. The MOSFET chip is also provided with a gate, and the gate is provided on the front side of the chip 320. The source of each MOSFET chip is connected to the source conductive copper layer through the copper clip 330, the drain of each MOSFET chip is connected to the drain conductive copper layer, and the gate of each MOSFET chip is connected to the gate conductive copper layer through a metal lead (not shown in the drawings), so that multiple MOSFET chips are distributed on the substrate 310. The front side of the substrate 310 is the upper surface of the substrate 310, and the back side of the substrate 310 is the lower surface of the substrate 310.

[0039] Reference Figure 4 and Figure 5As shown, in the embodiment, each power conversion unit 300 is provided with 12 MOSFET chips, and 6 MOSFET chips form a group, that is, the 12 MOSFET chips are divided into two groups, and the two groups are arranged in parallel to form the upper bridge arm 301 and the lower bridge arm 302 of the power conversion unit 300. The upper bridge arm 301 and the lower bridge arm 302 both use MOSFET chips. In the upper bridge arm 301, the source of the MOSFET chip is connected to the source conductive copper layer through the copper clip 330, the drain of the MOSFET chip is connected to the drain conductive copper layer, and the gate of the MOSFET chip is connected to the gate conductive copper layer; in the lower bridge arm 302, the source of the MOSFET chip is connected to the source conductive copper layer through the copper clip 330, the drain of the MOSFET chip is connected to the drain conductive copper layer, and the gate of the MOSFET chip is connected to the gate conductive copper layer. Figure 4 The areas where the two dotted boxes are located are the upper bridge arm 301 and the lower bridge arm 302 respectively.

[0040] It should be noted that the copper clip 330 in the embodiment is a curved copper sheet structure, and the copper sheet has a certain width, which not only has excellent electrical conductivity, but also has a wider structure width than the metal lead. The wider the conductor, the more obvious the magnetic flux cancellation generated by the current, and the smaller the parasitic inductance. In addition, copper has better electrical conductivity than aluminum, and the copper clip 330 material has excellent electrical conductivity, ensuring that the current is transmitted at an extremely high speed, thereby reducing power loss, reducing loop resistance, and improving current transmission efficiency.

[0041] Since the upper bridge arm 301 and the lower bridge arm 302 are arranged in pairs on the substrate 310, the topological circuit has a symmetrical distribution structure, which is beneficial to reducing the loop inductance. In addition, the source of the MOSFET chip is interconnected with the source conductive copper layer of the substrate 310 using a copper clip 330. Compared with the connection method of the metal lead, the copper clip 330 has a wider size and can offset more magnetic flux generated by the current, thereby effectively reducing the parasitic inductance of the power module 1000, achieving the effect of low parasitic inductance of the module, and the connection structure is also more reliable.

[0042] MOSFET chips are composed of metals, oxides and semiconductors, and have the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown, and wide safe working area. Its working principle is to use UGS to control the amount of "induced charge" to change the state of the conductive channel formed by these "induced charges" and then achieve the purpose of controlling the drain current. When the gate voltage changes, the amount of induced charge in the channel also changes, and the width of the conductive channel also changes accordingly, so the drain current I D Varies with gate voltage.

[0043] Specifically, in the embodiment of the utility model, the MOSFET chip used is specifically a SiC MOSFET chip, each power conversion unit 300 is provided with 12 SiC MOSFET chips, and the upper bridge arm 301 and the lower bridge arm 302 are respectively provided with 6 SiC MOSFET chips. Compared with Si MOSFET, the parasitic capacitance of SiC MOSFET is smaller, and SiC MOSFET is more sensitive to the parasitic parameters of the driving circuit. On the other hand, the driving voltage range of SiC MOSFET is -5V to +25V, while the driving voltage range of traditional Si MOSFET is -30V to +30V. Therefore, compared with traditional Si MOSFET, the safety threshold of SiC MOSFET is very small, and a voltage spike of the driving circuit is likely to break through the oxide layer between GS.

[0044] It is understandable that the number of SiC MOSFET chips in the embodiment is not limited to 12, but can also be 8, 16, 20, etc., so that the SiC MOSFET chips can be divided into two groups to form an upper bridge arm 301 and a lower bridge arm 302. The upper bridge arm 301 and the lower bridge arm 302 can have 4, 8, and 10 SiC MOSFET chips, respectively.

[0045] Reference Figure 5 As shown, the first conductive layer 340 includes a first connection layer 341 and a second connection layer 342, that is, the source conductive copper layer is divided into a first connection layer 341 and a second connection layer 342, and the first connection layer 341 and the second connection layer 342 are arranged at intervals, wherein the sources of the six chips 320 in the upper bridge arm 301 are connected to the first connection layer 341, and the sources of the six chips 320 in the lower bridge arm 302 are connected to the second connection layer 342, and the first connection layer 341 and the second connection layer 342 are respectively used to connect peripheral circuits, so that the peripheral application circuits can be connected to the sources of the upper bridge arm 301 and the lower bridge arm 302.

[0046] Reference Figure 3 , Figure 4 and Figure 5As shown, specifically, the power module 1000 also includes a first source lead-out terminal 370 and a second source lead-out terminal 380, one end of the first source lead-out terminal 370 is connected to the first connection layer 341, and the other end of the first source lead-out terminal 370 is constructed to be exposed to the outside of the insulating housing 100; one end of the second source lead-out terminal 380 is connected to the second connection layer 342, and the other end of the second source lead-out terminal 380 is constructed to be exposed to the outside of the insulating housing 100, that is, both the first source lead-out terminal 370 and the second source lead-out terminal 380 have a portion exposed to the outside of the insulating housing 100, which is convenient for connection with the peripheral application circuit, and the first source lead-out terminal 370 and the second source lead-out terminal 380 can be connected to the peripheral application circuit by welding, screw connection, etc.

[0047] It should be noted that the first source lead-out terminal 370 and the second source lead-out terminal 380 may be copper sheets, aluminum sheets or metal sheets made of other conductive materials, and are not further limited in detail.

[0048] Reference Figure 3 , Figure 4 and Figure 5 As shown, the power module 1000 also includes a drain lead terminal 390, one end of the drain lead terminal 390 is connected to the second conductive layer 350, and the other end of the drain lead terminal 390 is constructed to be exposed outside the insulating housing 100. Since the upper bridge arm 301 and the lower bridge arm 302 are connected in parallel, the drain of the MOSFET chip is connected to the peripheral application circuit through a drain lead terminal after the upper bridge arm 301 and the lower bridge arm 302 are connected in parallel in the embodiment, and the structure is simple. The drain lead terminal 390 can be a copper sheet, an aluminum sheet, or a metal sheet of other conductive materials, and is not further limited in detail.

[0049] It should be noted that, in the embodiment, since the upper bridge arm 301 and the lower bridge arm 302 are sequentially distributed along the length direction of the insulating housing 100, for the convenience of connection, the drain lead terminal 390 and the second source lead terminal 380 are arranged on the same side of the insulating housing 100, and the first source lead terminal 370 is arranged on the other side of the insulating housing 100. Of course, this is only an example, and the specific layout structure of the first source lead terminal 370, the second source lead terminal 380 and the drain lead terminal 390 can be selected according to actual requirements. The gate of the chip 320 in the upper bridge arm 301 and the lower bridge arm 302 is led out through the pin needle (not shown in the drawings) welded on the substrate to achieve electrical connection with the outside.

[0050] The structure and manufacturing method of the power module 1000 of the present invention are described below with reference to specific examples.

[0051] Reference Figure 3As shown, the circuit topology of the power module 1000 of the utility model is a three-phase full-bridge structure composed of three half-bridge circuits. The insulating housing 100 is connected to the heat dissipation base plate 200 through a sealant, and the module structure is provided with three power conversion units 300; each power conversion unit 300 is composed of a half-bridge topology circuit, and each power conversion unit 300 is composed of a substrate 310, a copper clip 330 and a SiC MOSFET chip. The substrate 310 is an active metal brazing substrate (Active Metal Brazing, AMB), which is developed on the basis of DBC technology. At a high temperature of about 800°C, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby realizing heterogeneous bonding between ceramic and metal.

[0052] A conductive copper layer is provided on the front and back of each AMB substrate 310. The copper layer on the back of the AMB substrate 310 is connected to the heat dissipation base plate 200 by welding. The conductive copper layer on the front of the AMB substrate 310 is formed into a pre-designed electrode pattern by an etching process. The electrode pattern includes a source conductive copper layer, a drain conductive copper layer and a gate conductive copper layer. Twelve SiC MOSFET chips are provided on the conductive copper layer of each AMB substrate 310, and six chips are connected in parallel to form an upper bridge arm 301 and a lower bridge arm 302 of the power conversion unit 300.

[0053] Specifically, the drain electrode on the back of the MOSFET chip is connected to the drain electrode conductive copper layer on the front of the AMB substrate 310 through a nano-metal sintering process, and the source electrode on the front of the MOSFET chip is electrically connected to the source electrode conductive copper layer on the front of the AMB substrate 310 through a copper clip 330. The copper clip 330 and the source electrode of the chip 320, and the copper clip 330 and the source electrode conductive copper layer on the front of the AMB substrate 310 are interconnected through a metal nano-sintering process. The gate electrode of the MOSFET chip is electrically interconnected with the gate conductive copper layer on the front of the AMB substrate 310 through a metal wire bonding process.

[0054] Compared with the SiC module of the related art, the power module 1000 of the utility model has the following advantages: the source electrode on the front of the SiC MOSFET chip is interconnected by a copper clip 330. Compared with the narrower metal bonding wire, the wider copper clip 330 structure can offset more magnetic flux generated by the current, so it can effectively reduce the parasitic inductance of the SiC module. Since the interconnection between the MOSFET chip and the substrate 310, the chip 320 and the copper clip 330, and the copper clip 330 and the substrate 310 adopts the nano-metal sintering process, the thermal reliability of the interconnection is improved. The layout design of the AMB substrate 310 is simple, compact, and symmetrical, which facilitates the combination of the copper clip 330 structure and the nano-metal sintering process, making the internal structure of the module simple, achieving the effect of low parasitic inductance of the module.

[0055] By using a structure combining copper clip 330 with nano-metal sintering process to replace the traditional wire bonding and welding process, a wider copper clip 330 is introduced to effectively reduce the parasitic inductance. The utility model finds that the parasitic inductance of SiC modules of the same specification is generally about 15nH. The utility model reduces the parasitic inductance of the SiC module to 11nH by optimizing the layout design of the AMB substrate 310 and combining the copper clip 330 with the nano-metal sintering process, with better results. The SiC power module 1000 is composed of three power conversion units 300 arranged in parallel to form a three-phase full-bridge topology circuit.

[0056] It should be noted that, in the embodiment, the conductive copper layer is not limited to copper metal, and other conductive metals may also be selected. The AMB substrate 310 can be replaced by a direct bonding copper (DBC) ceramic substrate or a direct bonding aluminum (DBA) ceramic substrate. Of course, this is only an example, and ceramic substrates of other process types may also be used. The substrate 310 is composed of a ceramic insulating layer and a front and back metal layer, which provides mechanical support for the chip 320 and conducts the heat generated by the chip 320 to the heat dissipation base plate 200. The front metal layer of the substrate 310 is interconnected with the gate, source, and drain of the chip 320 to realize the electrical connection between the chip 320 and the electrical terminal, and the back metal layer of the substrate 310 is connected to the heat dissipation base plate 200.

[0057] The SiC power module 1000 designed in the utility model can be used in rail transportation, industrial control, power grid transmission, photovoltaic power generation and other fields. It can be understood that the parasitic inductance inside the power module 1000 is mainly composed of three parts: the front copper layer of the AMB substrate 310, the bonding wire and the parasitic inductance at the power terminal. From the perspective of bonding wire optimization, the parasitic inductance is generally reduced from two aspects. On the one hand, the length of the bonding wire can be reduced, and on the other hand, the interconnection method can be changed. Since the inductance value of the conductor is its inherent property, which is determined by the characteristics of the material and geometry, for a single-layer conductor, reducing the length of the path through which the current flows or increasing the cross-sectional area through which the current flows can effectively reduce the parasitic inductance.

[0058] Compared with bonding wires, the copper clip 330 structure has a wider width. The wider the conductor, the more obvious the magnetic flux cancellation generated by the current, and the smaller the parasitic inductance. In addition, copper has better conductivity than aluminum. The copper clip 330 material has excellent conductivity, ensuring that the current is transmitted at a very high speed, thereby reducing power loss, reducing loop resistance, and improving current transmission efficiency.

[0059] In addition, wire bonding failure is one of the main failure modes of power module 1000. Since the elastic modulus of SiC is three times that of Si, the leads are more likely to fail under thermomechanical stress. Studies have shown that under the same package structure, the stress of SiC chip 320 is twice that of Si chip 320, which is more likely to cause module fatigue failure. The power device structure is divided into many layers, among which the factor affecting long-term reliability is the coefficient of thermal expansion (CTE) mismatch. The stress caused by CTE mismatch has a huge impact on reliability. Generally, aluminum bonding wires are used for interconnection between electrodes. Due to the large difference in CTE between aluminum bonding wires and semiconductor materials (aluminum: 23ppm / K, Si: 3ppm / K, SiC: 4.7ppm / K), the detachment of aluminum bonding wires will have a huge impact on device reliability. The CTE of copper is 16.5ppm / K, which can effectively reduce the thermomechanical stress problem caused by CTE mismatch compared to aluminum bonding wires.

[0060] Reference Figure 3 , Figure 4 and Figure 5 As shown, the utility model uses a copper clip 330 structure to realize the interconnection between the chip 320 and the substrate 310, which increases the cross-sectional area of ​​the overcurrent circuit, improves the module's current carrying capacity, and effectively reduces the loop parasitic inductance. Moreover, the layout design structure of the AMB substrate 310 is compact, which is conducive to the use of the copper clip 330 process. In addition, based on cost optimization, the chip 320 area becomes smaller and smaller, which limits the number of bonding wires to a certain extent. The copper clip 330 structure of the utility model is flexible in design and is suitable for most module packaging forms, which can solve the problem of insufficient module current carrying capacity caused by insufficient number of bonding wires.

[0061] In the related art, the chip 320 and the substrate 310 of most power modules 1000 are interconnected by a traditional welding process, and the source of the chip 320 is interconnected with the substrate 310 by an ultrasonic welding process. The utility model adopts a nano-metal sintering process to realize the interconnection between the chip 320 and the copper clip 330, and the copper clip 330 and the AMB substrate 310. Nano-metal materials have excellent electrical conductivity, thermal conductivity, high bonding strength and high-temperature reliability. The use of nano-metal sintering technology can improve the thermal reliability of the chip 320, reduce contact thermal resistance and contact resistance, increase the life of the SiC MOSFET chip, improve the long-term reliability of the SiC module, and meet the requirements of high-power device packaging and its high-temperature application.

[0062] Since the copper clip 330 structure is used to realize the electrical interconnection between the chip 320 and the substrate 310, it can offset more magnetic flux generated by the current, thereby effectively reducing the parasitic inductance of the SiC module. The interconnection between the chip 320 and the substrate 310, the chip 320 and the copper clip 330, and the copper clip 330 and the substrate 310 adopts the nano-metal sintering process, which improves the thermal reliability of the interconnection. The layout design of the AMB substrate 310 is simple, compact, and symmetrical, which facilitates the combination of the copper clip 330 structure and the nano-metal sintering process, making the internal structure of the module simple, achieving the effect of realizing low parasitic inductance of the module, and improving the overall reliability of the module.

[0063] Reference Figure 3 , Figure 4 and Figure 5 As shown, since the source of the chip 320 in the power module 1000 adopts a copper clip 330 structure to realize the electrical interconnection between the chip 320 and the substrate 310, the wider copper clip 330 structure can offset more magnetic flux generated by the current relative to the narrower metal bonding wire, so the parasitic inductance of the SiC module can be effectively reduced. Since the interconnection between the MOSFET chip and the substrate 310, the chip 320 and the copper clip 330, and the copper clip 330 and the substrate 310 adopts a nano-metal sintering process, the thermal reliability of the interconnection is improved. The layout design of the AMB substrate 310 is simple, compact, and symmetrical, which is convenient for realizing the combination of the copper clip 330 structure and the nano-metal sintering process, so that the internal structure of the module is simple, achieving the effect of realizing low parasitic inductance of the module. It is suitable for power electronic equipment in the fields of rail transportation, industrial control, power grid transmission, photovoltaic power generation, etc., to improve the reliability of power electronic equipment.

[0064] Of course, the present invention is not limited to the above-mentioned embodiments, and technicians familiar with the field may make equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A low inductance power module, characterized in that: include: Insulation housing; A heat dissipation base plate connected to the insulating shell; A plurality of power conversion units are arranged on the heat dissipation base plate, each of the power conversion units includes a substrate, a plurality of copper clips and a plurality of chips, the front side of the substrate is provided with a first conductive layer, a second conductive layer and a third conductive layer, the back side of the substrate is connected to the heat dissipation base plate, the front sides of the plurality of chips are provided with source electrodes and are respectively connected to the first conductive layer through the copper clips, the back sides of the plurality of chips are provided with drain electrodes and are connected to the second conductive layer, the gate electrodes of the plurality of chips are connected to the third conductive layer through metal leads, the chips are metal oxide semiconductor field effect transistors, and the plurality of chips are divided into two groups and respectively constitute an upper bridge arm and a lower bridge arm.

2. The power module according to claim 1, characterized in that: The first conductive layer includes a first connection layer and a second connection layer. The source electrodes of the multiple chips in the upper bridge arm are connected to the first connection layer, and the source electrodes of the multiple chips in the lower bridge arm are connected to the second connection layer. The first connection layer and the second connection layer are respectively used to connect peripheral circuits.

3. The power module according to claim 2, characterized in that: The power module also includes a first source lead terminal and a second source lead terminal, one end of the first source lead terminal is connected to the first connection layer, and the other end is constructed to be exposed outside the insulating shell; one end of the second source lead terminal is connected to the second connection layer, and the other end is constructed to be exposed outside the insulating shell.

4. The power module according to claim 1, characterized in that: The power module further includes a drain lead-out terminal, one end of which is connected to the second conductive layer, and the other end of which is configured to be exposed outside the insulating housing.

5. The power module according to claim 1, characterized in that: The chip is a silicon carbide metal oxide semiconductor field effect transistor, each power conversion unit is provided with twelve chips, and the upper bridge arm and the lower bridge arm are respectively provided with six chips.

6. The power module according to claim 1, characterized in that: The substrate is an AMB substrate, a DBC substrate or a DBA substrate, and the first conductive layer, the second conductive layer and the third conductive layer are all copper layers formed on the surface of the substrate.

7. The power module according to claim 1, characterized in that: The source electrode of the chip and the copper clip, as well as the copper clip and the first conductive layer are connected respectively by metal nano-sintering.

8. The power module according to claim 1, characterized in that: The drain electrode of the chip is connected to the second conductive layer by metal nano-sintering.

9. The power module according to claim 1, characterized in that: There are three power conversion units, and the topology circuit formed by the three power conversion units is a three-phase full-bridge topology circuit.

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