Package structure

Abstract

The utility model discloses a packaging structure. The package structure includes a semiconductor chip, a dielectric structure, a protective layer, and a redistribution structure. The dielectric structure is laterally spaced from the semiconductor chip, wherein the dielectric structure has a first dielectric constant. The protection layer surrounds the semiconductor chip and the dielectric structure and has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. The redistribution structure is over the semiconductor chip, the dielectric structure and the protective layer.

Description

Technical Field

[0001] The embodiments of the utility model relate to a packaging structure, and more particularly to a packaging structure with a capacitor. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer components and / or higher degrees of integration. Functional density (that is, the number of interconnected devices per chip area) has generally increased, and component size (that is, the smallest component that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] The package structure not only provides protection for the semiconductor device from environmental contamination, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that occupy less space or are lower in height have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further increase the density and functionality of semiconductor chips. These relatively new packaging technologies for semiconductor dies face manufacturing challenges. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] According to some embodiments, a packaging structure is provided. The packaging structure includes a semiconductor chip and a dielectric structure laterally spaced from the semiconductor chip. The dielectric structure has a first dielectric constant. The packaging structure also includes a protective layer surrounding the semiconductor chip and the dielectric structure. The protective layer has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. The packaging structure also includes a redistribution structure above the semiconductor chip, the dielectric structure, and the protective layer.

[0007] According to one embodiment of the present invention, the dielectric structure is substantially as thick as the protective layer.

[0008] According to one embodiment of the utility model, it also includes: a second dielectric structure, which is laterally spaced apart from the dielectric structure, wherein a portion of the protective layer is between the dielectric structure and the second dielectric structure, and the second dielectric structure has a third dielectric constant, and the third dielectric constant is higher than the second dielectric constant of the protective layer.

[0009] According to one embodiment of the present invention, the first dielectric constant is equal to the third dielectric constant, and the dielectric structure is wider than the second dielectric structure.

[0010] According to one embodiment of the present invention, an angle between a side wall and a bottom of the dielectric structure is in a range of 60 degrees to 90 degrees.

[0011] According to one embodiment of the utility model, it also includes: a ground layer, below the dielectric structure and the second dielectric structure, wherein the redistribution structure has a first conductive component formed on the dielectric structure and a second conductive component formed on the second dielectric structure; and a conductive column, and the protective layer surrounds the conductive column, wherein the conductive column is electrically connected to the ground layer.

[0012] According to some embodiments, a packaging structure is provided. The packaging structure includes a semiconductor chip and a capacitor element laterally spaced apart from the semiconductor chip. The capacitor element has a first conductive component, a dielectric structure, and a second conductive component. The dielectric structure is between the first conductive component and the second conductive component. The packaging structure also includes a protective layer of the dielectric structure surrounding the semiconductor chip and the capacitor element. The packaging structure also includes a redistribution structure above the semiconductor chip, the capacitor element, and the protective layer.

[0013] According to one embodiment of the present invention, it further includes: a second capacitor element, which is laterally spaced apart from the capacitor element, wherein the second capacitor element has a third conductive component, a second dielectric structure and a fourth conductive component, and the second dielectric structure is between the third conductive component and the fourth conductive component.

[0014] According to one embodiment of the present invention, the device further includes: a grounding bump formed on the redistribution structure, wherein the grounding bump is electrically connected to the second conductive component of the capacitor element and the fourth conductive component of the second capacitor element.

[0015] According to one embodiment of the present invention, the dielectric structure and the second dielectric structure have the same dielectric constant, and the dielectric structure is larger than the second dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention is best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various components may not be drawn to scale. In fact, the dimensions of the various components may be arbitrarily enlarged or reduced to provide clarity of illustration.

[0017] Figure 1A to Figure 1V are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0018] Figures 2A to 2L are plan views each showing a portion of a capacitor element of a package structure according to some embodiments.

[0019] Figure 3 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0020] FIG. 4A to FIG. 4G are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0021] FIG. 5A to FIG. 5G are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0022] 6A to 6F are cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0023] Figure 7 is a plan view of a portion of a package structure according to some embodiments.

[0024] The reference numerals are as follows:

[0025] 100: Carrier substrate

[0026] 102a, 102b, 126, 138, 144a, 144b, 144c, 602a, 602b, 602c: insulation layer

[0027] 104,106,142A,142B,142C,146,148: Conductive parts

[0028] 108,134,402,404: Mask element

[0029] 110,136A,136A',136B,136B',136C,136C': Open

[0030] 112: Seed layer

[0031] 114: Conductive layer

[0032] 116: Conductive structure

[0033] 118: Adhesive layer

[0034] 120: Semiconductor Chip

[0035] 122:Semiconductor substrate

[0036] 124: Top metal layer

[0037] 128: passivation layer

[0038] 130: Conductive gasket

[0039] 132: Protective layer

[0040] 140,140A,140B,140C,740A,740B,740C,740D: Dielectric structure

[0041] 150: Under-bump metallization structure

[0042] 152A, 152B, 152C: Conductive bumps

[0043] W1,W1',W2,W2',W3,W3': Width

[0044] θ,θ1,θ2,θ3: angle DETAILED DESCRIPTION

[0045] The following disclosure provides many different embodiments or examples to implement different components of the subject matter provided. The following describes specific examples of components and arrangements to simplify the present invention. Of course, these specific examples are only examples and are not intended to be limiting. For example, if the present invention describes forming a first component over or on a second component, it means that it may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which other components are formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat component symbols and / or characters in various examples. This repetition itself does not limit the relationship between the various embodiments and / or configurations discussed, but is for the purpose of simplification and clarity.

[0046] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship between one element or component and another element or components as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0047] The term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", is understood by a person skilled in the art. In some embodiments, the adjective may be substantially removed. Where applicable, the term "substantially" may also include embodiments with "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also relate to 90% or more of the specified content, such as 95% or more, in particular 99% or more, and including 100%. In addition, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding deviations from the specified arrangement, and may include, for example, deviations of up to 10 degrees. The word "substantially" does not exclude "completely", for example a composition "substantially free" of Y may be completely free of Y.

[0048] Terms such as "about" in relation to a specific distance or dimension should be interpreted as not excluding insignificant deviations from the specific distance or dimension and may include, for example, deviations of up to 10%. The term "about" in relation to a numerical value x may mean x±5% or 10%.

[0049] Embodiments of the utility model are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the stages described may be replaced or removed. Other components may be added to the semiconductor device structure and / or the packaging structure. For different embodiments, some of the components described below may be replaced or removed. Although some embodiments discuss operations performed in a specific order, these operations may be performed in another logical order.

[0050] The present invention may be directed to packaging structures such as 3D packaging, 3D-IC devices, and 2.5D packaging. The present invention may be directed to a packaging structure including a substrate that carries one or more dies or packages and a protective element (such as a protective lid) located beside the dies or packages. The protective element may also be used as a warpage-control element and / or a heat dissipation element.

[0051] Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages, 3DIC devices, and / or 2.5D packages. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allow testing using probes or probe cards or the like. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods combined with intermediate verification of known good dies to increase yield and reduce costs.

[0052] Figure 1A to Figure 1V is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. Figure 1A As shown, a carrier substrate 100 is provided or received. The carrier substrate 100 may include a glass substrate (e.g., a glass wafer), a semiconductor substrate (e.g., a silicon wafer), a metal substrate, an insulating substrate, one or more other suitable substrates or a combination thereof.

[0053] Then, according to some embodiments, Figure 1A As shown, an insulating layer 102a is formed above the carrier substrate 100. The insulating layer 102a can be made of or include a polymer material. The polymer material can be made of polybenzoxazole (PBO), polyimide, epoxy-based resin (PBO), other suitable polymer materials or their combination processes, or include polybenzoxazole, polyimide, epoxy resin, other suitable polymer materials or their combination. In some other embodiments, the insulating layer 102a is made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, other suitable dielectric materials or their combination, or includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, other suitable dielectric materials or their combination. In some embodiments, the insulating layer 102 a is formed by using a spin-on process, a spray coating process, a chemical vapor deposition (CVD) process, other suitable processes or a combination thereof.

[0054] In some embodiments, before forming the insulating layer 102a, an adhesive film is formed or disposed on the carrier substrate 100. The adhesive film may be a detachable film, such as a light transfer heat conversion (LTHC) film. Therefore, in subsequent processes, the adhesive film and the carrier substrate 100 may be detachable.

[0055] like Figure 1B As shown, according to some embodiments, a plurality of conductive components 104 are formed over the insulating layer 102a. The conductive components 104 may be made of copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials, or combinations thereof, or may include copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials, or combinations thereof. Each conductive component 104 may have a thickness in a range from about 7um to about 9um. In some embodiments, Figure 1B The rightmost conductive component 104 in FIG. 1 is used as a grounding layer. In some embodiments, multiple grounding layers are formed.

[0056] In some embodiments, a seed layer is deposited over the insulating layer 102a. The seed layer may include a plurality of sub-layers. The sub-layers may include a titanium layer and a copper layer. The titanium layer may have a thickness in the range of about 50nm to about 150nm. The copper layer may have a thickness in the range of about 450nm to about 550nm. Then, an electroplated conductive layer is formed on the seed layer. Then, a photolithography process and an etching process are used to partially remove the conductive layer and the seed layer. As a result, the remaining portions of the seed layer and the conductive layer form the conductive component 104.

[0057] like Figure 1C As shown, according to some embodiments, an insulating layer 102b is formed over the insulating layer 102a and the conductive component 104. The material and formation method of the insulating layer 102b may be the same as or similar to the material and formation method of the insulating layer 102a.

[0058] Afterwards, the insulating layer 102b is patterned to form a plurality of openings partially exposing the conductive components. In some embodiments, the insulating layer 102b is made of a photosensitive material. A photolithography process may be used to form the openings.

[0059] Then, according to some embodiments, Figure 1C As shown, a conductive component 106 is formed in the opening. The conductive component 106 can be used as a conductive via for forming an electrical connection between an underlying component and an overlying component to be formed later. The insulating layers 102a and 102b and the conductive components 104 and 106 can work together to form a redistribution structure for routing.

[0060] The conductive component 106 may be made of or include copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials, or combinations thereof. The conductive component 106 may be formed using an electroplating process, an electrochemical plating process, a CVD process, a physical vapor deposition (PVD) process, other suitable processes, or combinations thereof.

[0061] like Figure 1DAs shown, according to some embodiments, a patterned mask element 108 is formed over the insulating layer 102b and the conductive components 106. The patterned mask element 108 has a plurality of openings 110 that expose some of the conductive components 106. In some embodiments, the patterned mask element 108 is a patterned photoresist layer. In some other embodiments, the patterned mask element 108 is a photosensitive dry film. The photosensitive dry film can be laminated onto the insulating layer 102b and the conductive components 106. Thereafter, the photosensitive dry film is partially irradiated and partially removed. As a result, the photosensitive dry film is patterned and the openings 110 are formed. The openings 110 can be used to contain conductive structures (such as through insulator vias) that will be formed later.

[0062] like Figure 1E As shown, according to some embodiments, a seed layer 112 is deposited over the patterned mask element 108. The seed layer 112 extends along the sidewalls and bottom of the opening 110. In some embodiments, the seed layer 112 is in direct contact with some of the conductive features 106. The seed layer 112 can be made of copper, titanium, other suitable materials, or a combination thereof, or include copper, titanium, other suitable materials, or a combination thereof. The seed layer 112 can be deposited using a PVD process, a CVD process, other suitable processes, or a combination thereof.

[0063] Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, the seed layer 112 is not formed.

[0064] like Figure 1F As shown, according to some embodiments, a conductive layer 114 is formed on the seed layer 112. In some embodiments, the conductive layer 114 overfills the opening 110. The conductive layer 114 may be made of copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials, or combinations thereof, or may include copper, titanium, aluminum, gold, platinum, cobalt, tungsten, other suitable materials, or combinations thereof. The conductive layer 114 may be formed using an electroplating process, an electrochemical plating process, other suitable processes, or combinations thereof.

[0065] like Figure 1G As shown, according to some embodiments, the seed layer 112 and the conductive layer 114 are partially removed. As a result, the remaining portion of the seed layer 112 and the conductive layer 114 together form a plurality of conductive structures 116. The conductive structures 116 may be used as through insulator vias (TIVs).

[0066] In some embodiments, a planarization process is used to partially remove the seed layer 112 and the conductive layer 114. Therefore, a portion of the seed layer 112 and the conductive layer 114 outside the opening 110 is removed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, other suitable processes, or a combination thereof.

[0067] like Figure 1H As shown, according to some embodiments, after forming the conductive structure 116, the patterned mask element 108 is removed. Thus, the sidewalls of the conductive structure 116 are exposed. Figure 1H As shown, some of the conductive features 106 are also exposed.

[0068] like Fig. 1I As shown, a semiconductor chip 120 is disposed above the insulating layer 102b. The semiconductor chip 120 may be a single semiconductor chip, a system-on-intergrated-chip (SoIC) and / or a package including one or more encapsulated or protected semiconductor chips. For a system-integrated chip, a plurality of semiconductor chiplets may be stacked and combined together to form an electrical connection between these semiconductor chiplets. These semiconductor chiplets may be bonded to each other through hybrid bonding, which may include dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, a plurality of semiconductor chips are disposed above the insulating layer 102b. For simplicity, Fig. 1I Only one semiconductor chip 120 is shown.

[0069] In some embodiments, the semiconductor chip 120 includes a semiconductor substrate 122, a top metal layer 124, an insulating layer 126, a passivation layer 128, and a conductive pad 130 of the semiconductor chip 120. In some embodiments, the semiconductor chip 120 is attached to the insulating layer 102b using an adhesive layer 118. The adhesive layer 118 may be a die attach film (DAF). The adhesive layer 118 may have a thickness in the range of about 5um to about 15um.

[0070] like Figure 1JAs shown, according to some embodiments, a protective layer 132 is formed over the semiconductor chip 120, the conductive structure 116, and the insulating layer 102b. In some embodiments, the protective layer 132 is made of an insulating material such as a molding material, or includes an insulating material. The molding material may include a polymer material, such as an epoxy resin with fillers dispersed therein. The filler may include fibers (such as silica fibers and / or carbon-containing fibers), particles (such as silica particles and / or carbon-containing particles), or a combination thereof. In some embodiments, the dielectric constant of the protective layer 132 is approximately 2.8.

[0071] In some embodiments, a molding material (such as a flowable molding material) is introduced or injected to cover the semiconductor chip 120, the conductive structure 116, and the insulating layer 102b. In some embodiments, a heat treatment is then used to cure the flowable molding material and transform it into a protective layer 132.

[0072] like Figure 1K As shown, according to some embodiments, a planarization process is performed on the protective layer 132 to improve the flatness of the protective layer 132. For example, the planarization process may include a grinding process, a CMP process, a dry polishing process, other suitable processes or a combination thereof. In some embodiments, after the planarization process, the surface of the semiconductor chip 120 and the conductive structure 116 are exposed. Figure 1K As shown, the conductive pad 130 of the semiconductor chip 120 is exposed. In some embodiments, the top surface of the protection layer 132 is substantially level with the surface of the semiconductor chip 120 and the conductive structure 116.

[0073] like Figure 1L As shown, according to some embodiments, a patterned mask element 134 is formed above the protective layer 132, the semiconductor chip 120, and the conductive structure 116. The patterned mask element 134 can be a patterned photoresist layer. The patterned mask element 134 has a plurality of openings, which define the positions and contours of a plurality of dielectric structures to be formed later. These dielectric structures can be used as capacitor dielectric structures of a plurality of capacitors. By fine-tuning the size, contour, and / or shape of the openings, the capacitance of the capacitor can be adjusted accordingly.

[0074] Then, according to some embodiments, Figure 1L As shown, the protective layer 132 is partially removed using one or more etching processes using the patterned mask element 134 as an etching mask. As a result, openings 136A, 136B, and 136C are formed. Figure 1L As shown, openings 136A, 136B, and 136C have widths W1, W2, and W3, respectively. In some embodiments, opening 136A is wider than opening 136B, and opening 136B is wider than opening 136C.

[0075] Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, the openings 136A-136C are formed using an energy beam drilling process. The energy beam used in the energy beam drilling process may include a laser beam, an electron beam, an ion beam, or a combination thereof. In some embodiments, the patterned mask element 134 is not formed.

[0076] like Figure 1M As shown, according to some embodiments, the patterned mask element 134 is stripped. Figure 1M As shown, openings 136A-136C expose conductive component 106, which is electrically connected to conductive component 104 that can be used as a ground layer. In some embodiments, Figure 1M The rightmost conductive structure 116 is also electrically connected to the conductive member 104 which may be used as a ground layer.

[0077] like Figure 1N As shown, according to some embodiments, an insulating layer 138 is formed to overfill the openings 136A to 136C. In some embodiments, the dielectric constant of the insulating layer 138 is higher than the dielectric constant of the protective layer 132. The insulating layer 138 may be made of a polymer material, an oxide material, a nitride material, other suitable materials, or a combination thereof, or may include a polymer material, an oxide material, a nitride material, other suitable materials, or a combination thereof.

[0078] In some embodiments, the insulating layer 138 is formed of a liquid-phase polymer having a high dielectric constant. For example, a liquid-phase polymer material including polybenzoxazole (PBO) and / or polyimide may be applied, spin-coated, or dispensed to overfill the openings 136A to 136C. Thereafter, a low-temperature curing operation is used to harden the liquid-phase polymer material. As a result, the insulating layer 138 is formed. The curing temperature of the low-temperature curing operation may be in the range of about 50 degrees Celsius to about 300 degrees Celsius.

[0079] In some embodiments, the insulating layer 138 includes a polymer material having a filler dispersed therein. The polymer material may include an epoxy resin. The filler has a high dielectric constant. The filler may include an oxide material. The filler may be made of zirconium oxide, aluminum oxide, hafnium oxide, zirconium titanium oxide, titanium oxide, tantalum oxide, other suitable materials or combinations thereof, or include zirconium oxide, aluminum oxide, hafnium oxide, zirconium titanium oxide, titanium oxide, tantalum oxide, other suitable materials or combinations thereof. The filler may include fibers, particles or combinations thereof. In some embodiments, the filler is introduced into the liquid polymer material. Thereafter, the liquid polymer material and the filler are applied, dispensed or spin-coated to overfill the openings 136A to 136C. Thereafter, a low temperature curing operation is used to harden the liquid polymer material. As a result, an insulating layer 138 is formed. The curing temperature of the low temperature curing operation may be in the range of about 50 degrees Celsius to about 300 degrees Celsius.

[0080] In some embodiments, the insulating layer 138 is made of a high dielectric constant (high k) material, such as titanium oxide, strontium titanium oxide (STO), barium titanium oxide (BTO), barium strontium titanium oxide (BST), lead zirconium titanium oxide (PZT), silicon nitride, silicon oxide, silicon oxynitride, other suitable materials or combinations thereof, or includes a high dielectric constant material. The insulating layer 138 can be formed using a vapor deposition process. The vapor deposition process may include an atmospheric pressure chemical vapor deposition (APCVD) process, a sub-atmospheric chemical vapor deposition (SACVD) process, a microwave CVD process, a plasma-enhanced chemical vapor deposition (PECVD) process, a metal-organic chemical vapor deposition (MOCVD) process, an atomic layer deposition (ALD) process, other suitable processes or combinations thereof. The deposition temperature may be in the range of about 150 degrees Celsius to about 250 degrees Celsius.

[0081] In some other embodiments, a liquid slurry containing high-k material particles is applied, spin-coated, or dispensed to overfill the openings 136A-136C. A low temperature curing operation is then used to harden and remove the solvent of the liquid slurry. As a result, an insulating layer 138 is formed. The curing temperature of the low temperature curing operation may be in the range of about 50 degrees Celsius to about 300 degrees Celsius.

[0082] Then, according to some embodiments, Fig.1O As shown, the insulating layer 138 is planarized. As a result, the remaining portion of the insulating layer 138 forms a plurality of dielectric structures 140A, 140B, and 140C in the opening. In some embodiments, the dielectric structure 140A is wider and larger than the dielectric structure 140B, and the dielectric structure 140B is wider and larger than the dielectric structure 140C. In some embodiments, as shown in FIG. Fig.1O As shown, each of the dielectric structures 140A, 140B, and 140C is substantially as thick as the protection layer 132 .

[0083] In some embodiments, dielectric structures 140A, 140B, and 140C are used as capacitor dielectric structures of a decoupling capacitor. In some embodiments, dielectric structure 140A provides a higher capacitance than dielectric structure 140B, and dielectric structure 140B provides a higher capacitance than dielectric structure 140C.

[0084] Figures 2A to 2L are plan views each showing a portion of a capacitor element of a package structure according to some embodiments. Figures 2A to 2L 1 shows a plan view of a plurality of dielectric structures 140. Each of the dielectric structures 140A-140C may be formed to have Figures 2A to 2L By fine-tuning the size, profile and / or shape of the dielectric structure, the capacitance of the capacitor can be adjusted accordingly.

[0085] like Figure 1P As shown, according to some embodiments, conductive components 142A, 142B, and 142C are formed above dielectric structures 140A, 140B, and 140C, respectively. Conductive component 142A, dielectric structure 140A, and conductive component 106 below dielectric structure 140A may together form a first capacitor element. The material and formation method of conductive components 142A-142C may be the same or similar to the material and formation method of conductive components 104 and 106.

[0086] Conductive component 142A can be used as the top electrode of the first capacitor element, and the conductive component 106 below the dielectric structure 140A can be used as the bottom electrode of the first capacitor element. Conductive component 142B, dielectric structure 140B, and conductive component 106 below dielectric structure 140B can form a second capacitor element together. Conductive component 142B can be used as the top electrode of the second capacitor element, and conductive component 106 below dielectric structure 140B can be used as the bottom electrode of the second capacitor element. Conductive component 142C, dielectric structure 140C, and conductive component 106 below dielectric structure 140C can form a third capacitor element together. Conductive component 142C can be used as the top electrode of the third capacitor element, and conductive component 106 below dielectric structure 140C can be used as the bottom electrode of the third capacitor element.

[0087] Then, according to some embodiments, Figure 1PAs shown, an insulating layer 144a is formed over the semiconductor chip 120, the protection layer 132, the conductive structure 116 and the conductive components 142A-142C. The material and formation method of the insulating layer 144a may be the same or similar to the material and formation method of the insulating layers 102a and 102b.

[0088] like Figure 1Q As shown, according to some embodiments, the insulating layer 144a is patterned to form a plurality of openings. The openings may expose the conductive structure 116, the conductive pads 130 of the semiconductor chip 120, and the conductive components 142A-142C. The insulating layer 144a may be patterned using one or more photolithography processes and one or more etching processes. In some embodiments, the insulating layer 144a is made of a photosensitive polymer material. The openings may be formed using a photolithography process.

[0089] Then, according to some embodiments, Figure 1Q As shown, a conductive component 146 is formed over the conductive structure 116, the conductive pad 130 of the semiconductor chip 120, and the conductive components 142A-142C. The conductive component 146 extends over the top surface of the insulating layer 144a and extends into the opening. The material and formation method of the conductive component 146 can be the same or similar to the material and formation method of the conductive component 104.

[0090] like Figure 1R As shown, according to some embodiments, an insulating layer 144b and a plurality of conductive components 148 are formed. The conductive components 148 may fill the openings formed in the insulating layer 144a. The material and the forming method of the insulating layer 144b may be the same as or similar to the insulating layer 144a. The material and the forming method of the conductive component 148 may be the same as or similar to the material and the forming method of the conductive component 146.

[0091] like Figure 1S As shown, according to some embodiments, an insulating layer 144c is formed over the insulating layer 144b and the conductive component 148. The material and formation method of the insulating layer 144c may be the same or similar to that of the insulating layer 144a. The insulating layers 144a-144c and the conductive components 142A-142C, 146 and 148 may together form a redistribution structure for routing.

[0092] like Figure 1TAs shown, according to some embodiments, the insulating layer 144c is partially removed, and then an under bump metallization (UBM) structure 150 is formed. The UBM structure 150 can be used to hold or receive a conductive bump to be formed later. The UBM structure 150 can be a single layer or a stack of multiple sublayers. For example, the UBM structure 150 can be made of Ti, TiW, TiCu, Ni, Cu, other suitable materials or combinations thereof, or include Ti, TiW, TiCu, Ni, Cu, other suitable materials or combinations thereof. In some embodiments, the UBM structure 150 includes sublayers, and the sublayers include, for example, a glue layer (or a diffusion barrier layer) and a seed layer.

[0093] In some embodiments, the glue layer is made of or includes titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), one or more other suitable materials or combinations thereof. In some embodiments, the seed layer is a copper-containing seed layer formed on the glue layer. The copper-containing seed layer may be made of or includes pure copper or one of a variety of copper alloys including silver, chromium, nickel, tin, gold, one or more other suitable elements or combinations thereof.

[0094] In some embodiments, the UBM layer is deposited by using a physical vapor deposition (PVD) process (including, for example, a sputtering process or an evaporation process), a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an electroless plating process, other suitable processes or combinations thereof, and then the UBM layer is patterned to form the UBM structure 150 .

[0095] like Figure 1U As shown, according to some embodiments, a plurality of conductive bumps including conductive bumps 152A, 152B, and 152C are formed over the UBM structure 150. The conductive bump 152A can be electrically connected to the conductive pad 130 of the semiconductor chip 120. The conductive bump 152B can be electrically connected to the conductive component 142A used as the top electrode of the first capacitor element. Other conductive bumps ( Figure 1UConductive bump 152C is electrically connected to conductive structure 116, which is further electrically connected to conductive member 104 serving as a ground plane.

[0096] The conductive bumps 152A, 152B, and 152C may be made of, or include, tin-containing solder material. The tin-containing solder material may also include copper, silver, gold, aluminum, lead, other suitable materials, or combinations thereof. In some other embodiments, the conductive bumps 152A-152C are lead-free.

[0097] like Figure 1V As shown, according to some embodiments, the carrier substrate 100 is removed. A light irradiation operation can be used to remove the carrier substrate 100 and the LTHC film. In some embodiments, a sawing operation is used to form a plurality of package structures. One of the package structures is as shown in FIG. Figure 1V In some embodiments, the edges of the protection layer 132 and the insulating layers 102a-102b and 144a-144c are vertically aligned with each other.

[0098] In some embodiments, dielectric structures 140A-140C are made of the same material and therefore have the same dielectric constant. Since dielectric structure 140A occupies a larger area, dielectric structure 140A can provide a higher capacitance than dielectric structure 140B or 140C. However, the embodiments of the utility model are not limited thereto. Many changes and / or modifications may be made to the embodiments of the utility model. In some other embodiments, the dielectric structures are made of different materials. In some embodiments, the dielectric structures have different dielectric constants.

[0099] Figure 3 is a cross-sectional view of a portion of a package structure according to some embodiments. In some embodiments, forming a similar Figure 1V The package structure of the package structure shown in FIG. In some embodiments, the package structure includes dielectric structures 240A, 240B, and 240C. In some embodiments, the dielectric structures 240A to 240C are made of different materials and have different dielectric constants. In some embodiments, the dielectric constant of the dielectric structure 240A is higher than the dielectric constant of the dielectric structure 240B, and the dielectric constant of the dielectric structure 240B is higher than the dielectric constant of the dielectric structure 240C. Figure 3 As shown, dielectric structures 240A, 240B, and 240C have widths W1', W2', and W3', respectively. In some embodiments, widths W1', W2', and W3' are substantially the same.

[0100] FIG. 4A to FIG. 4G is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. In some embodiments, Figure 4A to Figure 4G show Figure 3 The formation of dielectric structures 240A-240C is shown.

[0101] like Figure 4A As shown, according to some embodiments, similar to Figure 1L to Figure 1M In the illustrated embodiment, the protection layer 132 is patterned to form openings 136A', 136B', and 136C'. In some embodiments, the openings 136A'-136C' have substantially the same width.

[0102] like Figure 4B As shown, patterned mask element 402 is formed to cover openings 136B' and 136C' according to some embodiments. Opening 136A' is not covered by patterned mask element 402. Patterned mask element 402 may be a patterned photoresist layer.

[0103] like Figure 4C As shown, according to some embodiments, dielectric structure 240A is formed in opening 136A'. The material and formation method of dielectric structure 240A can be the same or similar to the material and formation method of dielectric structure 140A. During the formation process of dielectric structure 240A, openings 136B' and 136C' are filled with the remaining portion of patterned mask element 402. As a result, the material used to form dielectric structure 240A is prevented from entering openings 136B' and 136C'. According to some embodiments, as Figure 4C As shown, after the dielectric structure 240A is formed, the patterned mask element 402 is removed.

[0104] like Figure 4D As shown, patterned mask element 404 is formed to cover opening 136C' according to some embodiments. Opening 136B' is not covered by patterned mask element 404. Patterned mask element 404 may be a patterned photoresist layer.

[0105] like Figure 4E As shown, according to some embodiments, a dielectric structure 240B is formed in the opening 136B'. The material and formation method of the dielectric structure 240B may be the same or similar to the material and formation method of the dielectric structure 140A. In some embodiments, the dielectric structure 240B and 240A are made of different materials. In some embodiments, the dielectric structure 240B has a lower dielectric constant than the dielectric structure 240A.

[0106] During the formation of dielectric structure 240B, opening 136C' is filled with the remaining portion of patterned mask element 404, and opening 136A' is occupied by dielectric structure 240A. As a result, material used to form dielectric structure 240B is prevented from entering openings 136A' and 136C'. Figure 4E As shown, after the dielectric structure 204B is formed, the patterned mask element 404 is removed.

[0107] like Figure 4F As shown, according to some embodiments, a dielectric structure 240C is formed in the opening 136C'. The material and the formation method of the dielectric structure 240C can be the same or similar to the material and the formation method of the dielectric structure 140A. In some embodiments, the dielectric structure 240C and 240B and / or 240A are made of different materials. In some embodiments, the dielectric structure 240B has a lower dielectric constant than the dielectric structure 240C.

[0108] During the formation process of dielectric structure 240C, openings 136A' and 136B' are occupied by dielectric structures 240A and 240B, respectively. As a result, the material used to form dielectric structure 240C is prevented from entering openings 136A' and 136B'.

[0109] like Figure 4G As shown, according to some embodiments, Figure 1P Similar to the embodiment shown, conductive features 142A, 142B, and 142C are formed over dielectric structures 240A, 240B, and 240C, respectively. As a result, multiple capacitor elements are formed. In some embodiments, the capacitor element with dielectric structure 240A has a higher capacitance than the capacitor element with dielectric structure 240B or 240C.

[0110] In some embodiments, each of the dielectric structures 240A, 240B, and 240C has a vertical sidewall. In these cases, the angle θ formed between the sidewall and the bottom of the dielectric structures 240A-240C is substantially equal to 90 degrees. However, the embodiments of the present invention are not limited thereto. In some other embodiments, one or more of the dielectric structures 240A-240C are formed to have an inclined sidewall to fine-tune the capacitance as needed. The angle θ may be in the range of about 60 degrees to about 90 degrees.

[0111] Many variations and / or modifications may be made to the embodiments of the present invention. FIG. 5A to FIG. 5G is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. In some embodiments, FIG. 5A to FIG. 5G show Figure 3The formation of dielectric structures 240A-240C is shown.

[0112] like Figure 5A As shown, according to some embodiments, the protective layer 132 is patterned to form an opening 136A'. Then, according to some embodiments, as shown in FIG. Figure 5B As shown, dielectric structure 240A is formed in opening 136A'.

[0113] like Figure 5C As shown, according to some embodiments, the protective layer 132 is patterned to form an opening 136B'. Then, according to some embodiments, as shown in FIG. Figure 5D As shown, dielectric structure 240B is formed in opening 136B'. In some embodiments, dielectric structure 240B and dielectric structure 240A are made of different materials. In some embodiments, dielectric structure 240B has a lower dielectric constant than dielectric structure 240A.

[0114] like Figure 5E As shown, according to some embodiments, the protective layer 132 is patterned to form an opening 136C'. Then, according to some embodiments, as shown in FIG. Fig. 5F As shown, dielectric structure 240C is formed in opening 136C'. In some embodiments, dielectric structures 240C and 240B are made of different materials. In some embodiments, dielectric structure 240C has a lower dielectric constant than dielectric structure 240B.

[0115] like Figure 5G As shown, according to some embodiments, Figure 1P Similar to the embodiment shown, conductive features 142A, 142B, and 142C are formed over dielectric structures 240A, 240B, and 240C, respectively. As a result, multiple capacitor elements are formed. In some embodiments, the capacitor element with dielectric structure 240A has a higher capacitance than the capacitor element with dielectric structure 240B or 240C.

[0116] In some embodiments, each of the dielectric structures 240A, 240B, and 240C has a vertical sidewall. In these cases, the angle θ formed between the sidewall and the bottom of the dielectric structures 240A-240C is substantially equal to 90 degrees. However, the embodiments of the present invention are not limited thereto. In some other embodiments, one or more of the dielectric structures 240A-240C are formed to have an inclined sidewall to fine-tune the capacitance as needed. The angle θ may be in the range of about 60 degrees to about 90 degrees.

[0117] Many variations and / or modifications may be made to the embodiments of the present invention.In some embodiments, the dielectric structure includes two or more insulating layers. 6A to 6Fare cross-sectional views of various stages of a process for forming a portion of a package structure in accordance with some embodiments.

[0118] like Fig. 6A As shown, according to some embodiments, similar to Figure 1L to Figure 1M In the illustrated embodiment, the protection layer 132 is patterned to form openings 136A, 136B, and 136C. In some embodiments, the opening 136A is wider than the opening 136B, and the opening 136B is wider than the opening 136C.

[0119] like Figure 6B As shown, according to some embodiments, the insulating layer 602a is formed on Fig. 6A In some embodiments, the insulating layer 602a overfills the opening 136C having a width W3. In some embodiments, the insulating layer 602a partially fills the openings 136A and 136B. The insulating layer 602a extends along the sidewalls and bottom of the openings 136A and 136B. The material and formation method of the insulating layer 602a may be the same as Figure 1N The material and forming method of the insulating layer 138 shown are the same or similar.

[0120] like Figure 6C As shown, according to some embodiments, insulating layer 602b is formed over insulating layer 602a. In some embodiments, insulating layer 602b overfills opening 136B. In some embodiments, insulating layer 602b partially fills opening 136A. Due to the occupation of insulating layer 602a, insulating layer 602b is prevented from entering opening 136C.

[0121] The material and formation method of the insulating layer 602b can be Figure 1N The materials and formation methods of the insulating layer 138 shown are the same or similar. In some embodiments, the insulating layers 602a and 602b are made of different materials. In some embodiments, the insulating layers 602a and 602b have different dielectric constants. In some embodiments, the insulating layer 602b has a higher dielectric constant than the insulating layer 602a.

[0122] like Fig.6D As shown, according to some embodiments, insulating layer 602c is formed over insulating layer 602b. In some embodiments, insulating layer 602c overfills opening 136A. Due to the occupation of insulating layer 602a, insulating layer 602c is prevented from entering opening 136C. Due to the occupation of insulating layers 602a and 602b, insulating layer 602c is prevented from entering opening 136B.

[0123] The material and formation method of the insulating layer 602c can be Figure 1NThe materials and formation methods of the insulating layers 138 shown are the same or similar. In some embodiments, two or more of the insulating layers 602a-602c are made of different materials. In some embodiments, two or more of the insulating layers 602a-602c have different dielectric constants. In some embodiments, the insulating layer 602c has a higher dielectric constant than the insulating layer 602b.

[0124] like Fig. 6E As shown, according to some embodiments, similar to Figure 1N to Figure 1O In the embodiment shown, the insulating layers 602a-602c are planarized. The first remaining portion of the insulating layer 602a, the first remaining portion of the second insulating layer 602b, and the remaining portion of the insulating layer 602c together form the dielectric structure 140A. The second remaining portion of the insulating layer 602a and the second remaining portion of the insulating layer 602b together form the dielectric structure 140B. The third remaining portion of the insulating layer 602a forms the dielectric structure 140C.

[0125] like Fig. 6F As shown, according to some embodiments, similar to Figure 1P In the embodiment shown, conductive features 142A, 142B, and 142C are formed over dielectric structures 140A, 140B, and 140C, respectively. As a result, multiple capacitor elements are formed. In some embodiments, the capacitor element having dielectric structure 140A has a higher capacitance than the capacitor element having dielectric structure 140B or 140C.

[0126] In some embodiments, each of the dielectric structures 140A, 140B, and 140C has a vertical sidewall. In these cases, the sidewall angles θ1, θ2, and θ3 of the dielectric structures 140A-140C are substantially equal to 90 degrees. However, the embodiments of the present invention are not limited thereto. In some other embodiments, one or more dielectric structures 140A-140C are formed to have inclined sidewalls to fine-tune the capacitance as needed. Each of the sidewall angles θ1, θ2, and θ3 can be in the range of from about 60 degrees to about 90 degrees. In some embodiments, two or more of the sidewall angles θ1, θ2, and θ3 are the same. In some embodiments, two or more of the sidewall angles θ1, θ2, and θ3 are different.

[0127] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 7 1 is a plan view of a portion of a package structure according to some embodiments. In some embodiments, the plurality of semiconductor chips 120A, 120B, and 120C are laterally surrounded by a protective layer 132. In some embodiments, the plurality of dielectric structures 740A, 740B, 740C, and 740D of the plurality of capacitor elements are also laterally surrounded by a protective layer 132.

[0128] like Figures 2A to 2L As mentioned in the illustrated embodiment, each of the dielectric structures 740A-740D can have different sizes, profiles and / or distributions. In some embodiments, the dielectric structures 740A-740C are located on the right side of the semiconductor chip 120B. In some embodiments, the dielectric structure 740D extends between the semiconductor chips 120A-120C.

[0129] The utility model embodiment forms a packaging structure, the packaging structure has a protective layer (such as a mold layer) of a dielectric structure of one or more semiconductor chips and one or more embedded capacitor elements. The shape, profile, size and material of the dielectric structure can be changed to provide a capacitance change of the embedded capacitor element. The capacitance (capacitance) and area of ​​the capacitor element are adjustable, which greatly improves the routing flexibility. The capacitor element embedded in the protective layer can provide a capacitance ranging from about 100 femto-Farad (fF) to about 500 nano-Farad (nF). The interconnection length between the embedded capacitor element and the semiconductor chip is short, which allows a shorter time delay. The performance and reliability of the packaging structure are significantly improved, and it is suitable for future advanced portable products such as a new generation of smart phones, tablets, the Internet of Things (internet of things), cloud computing devices and the like.

[0130] According to some embodiments, a method for forming a package structure is provided. The method includes surrounding a semiconductor chip with a protective layer. The protective layer has a first dielectric constant. The method also includes partially removing the protective layer to form an opening. The method also includes forming a dielectric structure, and the dielectric structure partially or completely fills the opening. The dielectric structure has a second dielectric constant, and the second dielectric constant is higher than the first dielectric constant. The method also includes forming a redistribution structure above the semiconductor chip, the protective layer and the dielectric structure.

[0131] In some embodiments, the method further comprises partially removing the protective layer to form a second opening. An insulating layer is formed, and the insulating layer overfills the opening and the second opening. The insulating layer is planarized so that a first remaining portion of the insulating layer in the opening forms the dielectric structure, and a second remaining portion of the insulating layer in the second opening forms a second dielectric structure. In some embodiments, the opening is wider than the second opening. In some embodiments, the method further comprises partially removing the protective layer to form the second opening. Before forming the dielectric structure, the second opening is covered with a mask element. The mask element is removed. A second dielectric structure is formed, and the second dielectric structure at least partially fills the second opening. In some embodiments, the second dielectric structure has a third dielectric constant, the third dielectric constant is higher than the first dielectric constant, and the third dielectric constant is lower than the second dielectric constant. In some embodiments, the method further comprises partially removing the protective layer after forming the dielectric structure to form the second opening. A second dielectric structure is formed, and the second dielectric structure at least partially fills the second opening. In some embodiments, the method further comprises partially removing the protective layer to form the second opening. The opening is wider than the second opening. A first insulating layer is formed to overfill the second opening. The first insulating layer extends along the sidewall of the opening. A second insulating layer is formed above the first insulating layer to overfill the opening. The first insulating layer and the second insulating layer are planarized so that the first remaining portion of the first insulating layer and the remaining portion of the second insulating layer in the opening form the dielectric structure, and the second remaining portion of the first insulating layer in the second opening forms the second dielectric structure. In some embodiments, the first insulating layer and the second insulating layer have different dielectric constants. In some embodiments, the method further includes forming a second redistribution structure above a carrier substrate. The second redistribution structure has a first conductive component. A semiconductor chip is disposed on the redistribution structure. A protective layer is formed above the redistribution structure so that the protective layer surrounds the semiconductor chip. A second conductive component is formed on the dielectric structure. The dielectric structure is located between the second conductive component and the first conductive component. In some embodiments, the method further includes forming a conductive pillar above the redistribution structure before forming the protective layer. The conductive pillar is electrically connected to the first conductive structure. A first conductive bump and a second conductive bump are formed above the redistribution structure, wherein the first conductive bump is electrically connected to the conductive pillar, and the second conductive bump is electrically connected to the second conductive component.

[0132] According to some embodiments, a packaging structure is provided. The packaging structure includes a semiconductor chip and a dielectric structure laterally apart from the semiconductor chip. The dielectric structure has a first dielectric constant. The packaging structure also includes a protective layer surrounding the semiconductor chip and the dielectric structure. The protective layer has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. The packaging structure also includes a redistribution structure above the semiconductor chip, the dielectric structure, and the protective layer.

[0133] In some embodiments, the dielectric structure is substantially as thick as the protective layer. In some embodiments, the package structure also includes a second dielectric structure laterally spaced apart from the dielectric structure. A portion of the protective layer is between the dielectric structure and the second dielectric structure, the second dielectric structure having a third dielectric constant, and the third dielectric constant is higher than the second dielectric constant of the protective layer. In some embodiments, the first dielectric constant is substantially equal to the third dielectric constant, and the dielectric structure is wider than the second dielectric structure. In some embodiments, the dielectric structure and the second dielectric structure are made of different materials. In some embodiments, the package structure also includes a grounding layer below the dielectric structure and the second dielectric structure. The redistribution structure has a first conductive component formed on the dielectric structure and a second conductive component formed on the second dielectric structure. The package structure also includes a conductive column surrounded by the protective layer. The conductive column is electrically connected to the ground layer.

[0134] According to some embodiments, a packaging structure is provided. The packaging structure includes a semiconductor chip and a capacitor element laterally spaced apart from the semiconductor chip. The capacitor element has a first conductive component, a dielectric structure, and a second conductive component. The dielectric structure is between the first conductive component and the second conductive component. The packaging structure also includes a protective layer of the dielectric structure surrounding the semiconductor chip and the capacitor element. The packaging structure also includes a redistribution structure above the semiconductor chip, the capacitor element, and the protective layer.

[0135] In some embodiments, the package structure further includes a second capacitor element laterally spaced apart from the capacitor element. The second capacitor element has a third conductive component, a second dielectric structure, and a fourth conductive component. The second dielectric structure is between the third conductive component and the fourth conductive component. In some embodiments, the package structure further includes a ground bump formed on the redistribution structure. The ground bump is electrically connected to the second conductive component of the capacitor element and the fourth conductive component of the second capacitor element. In some embodiments, the dielectric structure has the same dielectric constant as the second dielectric structure, and the dielectric structure is larger than the second dielectric structure.

[0136] The foregoing disclosure summarizes the components of multiple embodiments so that those skilled in the art can better understand the methods of the present invention. Those skilled in the art will understand that they can easily design or modify other processes and structures based on the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions or replacements may be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: a semiconductor chip; a dielectric structure laterally spaced apart from the semiconductor chip, wherein the dielectric structure has a first dielectric constant; a protection layer surrounding the semiconductor chip and the dielectric structure, wherein the protection layer has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant; and A redistribution structure is above the semiconductor chip, the dielectric structure and the protection layer.

2. The packaging structure according to claim 1, characterized in that: The dielectric structure is as thick as the protective layer.

3. The packaging structure according to claim 1, characterized in that: Also includes: A second dielectric structure is laterally spaced apart from the dielectric structure, wherein a portion of the protection layer is interposed between the dielectric structure and the second dielectric structure, the second dielectric structure has a third dielectric constant, and the third dielectric constant is higher than the second dielectric constant of the protection layer.

4. The packaging structure according to claim 3, characterized in that: The first dielectric constant is equal to the third dielectric constant, and The dielectric structure is wider than the second dielectric structure.

5. The packaging structure according to claim 1, characterized in that: An angle between a side wall and a bottom of the dielectric structure is in a range of 60 degrees to 90 degrees.

6. The packaging structure according to claim 3, characterized in that: Also includes: a ground layer below the dielectric structure and the second dielectric structure, wherein the redistribution structure has a first conductive component formed on the dielectric structure and a second conductive component formed on the second dielectric structure; as well as A conductive column is provided, and the protective layer surrounds the conductive column, wherein the conductive column is electrically connected to the ground layer.

7. A packaging structure, characterized in that: include: a semiconductor chip; a capacitor element laterally spaced apart from the semiconductor chip, wherein the capacitor element has a first conductive component, a dielectric structure and a second conductive component, and the dielectric structure is interposed between the first conductive component and the second conductive component; a protective layer surrounding the semiconductor chip and the dielectric structure of the capacitor element; and A redistribution structure is above the semiconductor chip, the capacitor element and the protection layer.

8. The packaging structure according to claim 7, characterized in that: Also includes: A second capacitor element is laterally spaced apart from the capacitor element, wherein the second capacitor element has a third conductive component, a second dielectric structure, and a fourth conductive component, and the second dielectric structure is between the third conductive component and the fourth conductive component.

9. The packaging structure according to claim 8, characterized in that: Also includes: A ground bump is formed on the redistribution structure, wherein the ground bump is electrically connected to the second conductive component of the capacitor element and the fourth conductive component of the second capacitor element.

10. The packaging structure according to claim 8, characterized in that: The dielectric structure and the second dielectric structure have the same dielectric constant, and the dielectric structure is larger than the second dielectric structure.

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