Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer and a passivation layer, and the first metal layer is arranged on the substrate; the first insulating layer is arranged on the substrate and covers the first metal layer; the semiconductor layer is arranged on the first insulating layer; the second metal layer comprises a source electrode and a drain electrode, at least part of the source electrode is arranged on the upper surface of the semiconductor layer, part of the drain electrode is arranged on the upper surface of the semiconductor layer, and the other part of the drain electrode covers at least part of the peripheral surface of the semiconductor layer; the passivation layer is arranged on the first insulating layer and covers the semiconductor layer and the second metal layer; the semiconductor layer overlaps the first metal layer in a direction perpendicular to a plane where the substrate is located. The utility model aims to reduce the influence of ambient light on the TFT device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In a conventional bottom-gate thin film transistor (TFT) device, when the semiconductor layer is made of amorphous silicon (a-Si), the edge of the semiconductor layer is greatly affected by light because there is no metal shielding. When ambient light shines on the edge of the semiconductor layer, it will cause leakage current in the TFT device, thereby damaging the TFT device.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0004] The purpose of the present application is to provide an array substrate and a display panel, aiming to reduce the influence of ambient light on TFT devices.

[0005] To solve the above problems, the technical solution of this application is as follows:

[0006] In a first aspect, the present application proposes an array substrate, comprising:

[0007] substrate;

[0008] A first metal layer, disposed on the substrate;

[0009] a first insulating layer, disposed on the substrate and covering the first metal layer;

[0010] A semiconductor layer, disposed on the first insulating layer;

[0011] a second metal layer, comprising a source electrode and a drain electrode, wherein at least a portion of the source electrode is disposed on an upper surface of the semiconductor layer, a portion of the drain electrode is disposed on an upper surface of the semiconductor layer, and another portion of the drain electrode covers at least a portion of an outer peripheral surface of the semiconductor layer; and

[0012] a passivation layer, disposed on the first insulating layer and covering the semiconductor layer and the second metal layer;

[0013] Wherein, in a direction perpendicular to the plane where the substrate is located, the semiconductor layer overlaps with the first metal layer.

[0014] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer includes a first side surface;

[0015] The drain electrode includes a first drain electrode portion, a portion of which covers at least a portion of the first side surface, and another portion of the first drain electrode portion is disposed on the upper surface of the semiconductor layer and is spaced apart from the source electrode.

[0016] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer includes a second side surface, and the second side surface is arranged opposite to the first side surface;

[0017] The drain electrode includes a second drain electrode portion, the second drain electrode portion is arranged opposite to the first drain electrode portion, a portion of the second drain electrode portion covers at least a portion of the second side surface, and another portion of the second drain electrode portion is arranged on the upper surface of the semiconductor layer;

[0018] Wherein, at least a portion of the source is located between the first drain portion and the second drain portion.

[0019] In one embodiment of the present application, the drain electrode further includes a third drain electrode portion, the third drain electrode portion connects the first drain electrode portion and the second drain electrode portion, and forms a notch pattern on the upper surface of the semiconductor layer;

[0020] At least a portion of the source electrode extends between the first drain electrode portion and the second drain electrode portion, and the source electrode is spaced apart from the third drain electrode portion.

[0021] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer includes a third side surface, and the third side surface connects the first side surface and the second side surface;

[0022] A portion of the third drain portion covers at least a portion of the third side surface of the semiconductor layer, and connects a portion of the first drain portion covering the first side surface and a portion of the second drain portion covering the second side surface;

[0023] Another portion of the third drain portion is disposed on the upper surface of the semiconductor layer and connects the portion of the first drain portion disposed on the upper surface of the semiconductor layer and the portion of the second drain portion disposed on the upper surface of the semiconductor layer.

[0024] In one embodiment of the present application, the semiconductor layer includes:

[0025] A first deposition layer is disposed on the first insulating layer; and

[0026] a second deposition layer, covering the first deposition layer;

[0027] The first drain portion, the second drain portion, and the third drain portion overlap the outer surface of the second deposition layer, and the carrier mobility of the second deposition layer is greater than the carrier mobility of the first deposition layer.

[0028] In an embodiment of the present application, the semiconductor layer further includes a doping layer, and the doping layer is located between the second metal layer and the second deposition layer.

[0029] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer includes a fourth side surface, the fourth side surface connects the first side surface and the second side surface, and the fourth side surface is arranged back to back with the third side surface;

[0030] A portion of the source electrode is disposed on the upper surface of the semiconductor layer and extends into the notch pattern, and is spaced apart from a portion of the first drain electrode portion disposed on the upper surface of the semiconductor layer, a portion of the second drain electrode portion disposed on the upper surface of the semiconductor layer, and a portion of the third drain electrode portion disposed on the upper surface of the semiconductor layer;

[0031] Another portion of the source electrode is disposed on the fourth side surface and is spaced apart from a portion of the first drain electrode portion disposed on the first side surface and a portion of the second drain electrode portion disposed on the second side surface.

[0032] In one embodiment of the present application, the second metal layer further includes:

[0033] a first wiring connected to a portion of the third drain portion disposed on the third side surface; and

[0034] A second wiring is connected to a portion of the source electrode disposed on the fourth side surface.

[0035] In the second aspect, the present application proposes a display panel, which includes an array substrate, and the array substrate includes: a substrate; a first metal layer, arranged on the substrate; a first insulating layer, arranged on the substrate and covering the first metal layer; a semiconductor layer, arranged on the first insulating layer; a second metal layer, including a source and a drain, at least a portion of the source is arranged on the upper surface of the semiconductor layer, a portion of the drain is arranged on the upper surface of the semiconductor layer, and another portion of the drain covers the outer side surface of the semiconductor layer; a passivation layer, arranged on the first insulating layer and covering the semiconductor layer and the second metal layer; wherein the semiconductor layer overlaps with the first metal layer in a direction perpendicular to the plane where the substrate is located.

[0036] In the present application, the drain electrode covers at least a portion of the outer peripheral surface of the semiconductor layer, so that the ambient light originally shining on the edge of the semiconductor layer is blocked by the drain electrode covering the outer peripheral surface of the semiconductor layer, thereby reducing the leakage current of the TFT device and extending the service life of the TFT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a top view of the array substrate of the present application;

[0038] Figure 2 yes Figure 1 AA' cross-sectional view of the array substrate;

[0039] Figure 3 yes Figure 1 BB' cross-sectional view of the array substrate;

[0040] Figure 4 is a top view of a conventional array substrate;

[0041] Figure 5 yes Figure 4 CC' cross-sectional view of a conventional array substrate. DETAILED DESCRIPTION

[0042] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0043] The present application proposes a display panel, which may be a Mini LED display panel, a Micro LED display panel, or an OLED display panel. The display panel includes an array substrate 100 .

[0044] See also Figures 1 to 3 , the present application proposes an array substrate 100, comprising:

[0045] Substrate 10;

[0046] A first metal layer 20, disposed on the substrate 10;

[0047] A first insulating layer 30 is disposed on the substrate 10 and covers the first metal layer 20;

[0048] A semiconductor layer 40, disposed on the first insulating layer 30;

[0049] a second metal layer 50, comprising a source electrode 51 and a drain electrode 52, wherein at least a portion of the source electrode 51 is disposed on the upper surface of the semiconductor layer 40, a portion of the drain electrode 52 is disposed on the upper surface of the semiconductor layer 40, and another portion of the drain electrode 52 covers at least a portion of the outer peripheral surface of the semiconductor layer 40; and

[0050] a passivation layer 60, disposed on the first insulating layer 30 and covering the semiconductor layer 40 and the second metal layer 50;

[0051] In the direction perpendicular to the plane where the substrate 10 is located, the semiconductor layer 40 overlaps with the first metal layer 20 .

[0052] In the present application, the drain electrode 52 covers at least a portion of the outer peripheral surface of the semiconductor layer 40, so that the ambient light originally shining on the edge of the semiconductor layer 40 is blocked by the drain electrode 52 covering the outer peripheral surface of the semiconductor layer 40, thereby reducing the leakage current of the TFT device and extending the service life of the TFT device.

[0053] See also Figures 1 to 3 The outer surface of the semiconductor layer of the present application includes an upper surface, a lower surface, and an outer peripheral surface connecting the upper surface and the lower surface. Figure 1 When the shape of the semiconductor layer in a direction perpendicular to the substrate is a rectangle, the outer peripheral surface of the semiconductor layer includes a first side surface, a third side surface, a second side surface and a fourth side surface connected in sequence, wherein the first side surface is back to back with the second side surface, and the third side surface is back to back with the fourth side surface.

[0054] See also Figures 1 to 3 , the drain electrode covers a portion of the outer peripheral surface of the semiconductor layer; or, the drain electrode completely covers the outer peripheral surface of the semiconductor layer.

[0055] See also Figure 4 and Figure 5 In the conventional array substrate 100, the source electrode 51 and the drain electrode 52 in the second metal layer 50 are both arranged on the upper surface of the semiconductor layer 40, and the edges of the first side surface 421, the second side surface 422, the third side surface 423, the fourth side surface 424 and the like of the semiconductor layer 40 are not covered by the second metal layer 50. When ambient light shines from the edge of the semiconductor layer 40 to the semiconductor layer 40, since the material of the semiconductor layer 40 is amorphous silicon, when the semiconductor layer 40 is used as the active layer of the TFT device, the semiconductor layer 40 will generate leakage current when irradiated by ambient light. When the illumination time is too long, the TFT device will be damaged, thereby shortening the service life of the TFT device.

[0056] See also Figure 1 , Figure 2 and Figure 3 In the present application, part of the drain electrode 52 covers the first side 421, the second side 422 and the third side 423 of the semiconductor layer 40, and part of the source electrode 51 covers the fourth side 424 of the semiconductor layer 40, thereby reducing the area of ​​the outer side of the semiconductor layer 40 exposed to light, thereby reducing the leakage current of the semiconductor layer 40 and extending the service life of the semiconductor layer 40.

[0057] The thickness of the first insulating layer 30 is about 3000 angstroms. To 5000 Angstroms within the range.

[0058] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer 40 includes a first side surface 421;

[0059] The drain electrode 52 includes a first drain electrode portion 521 , a portion of which covers at least a portion of the first side surface 421 , and another portion of the first drain electrode portion 521 is disposed on the upper surface of the semiconductor layer 40 and spaced apart from the source electrode 51 .

[0060] See also Figure 2 In this embodiment, the outer side surface of the semiconductor layer 40 includes four side surfaces, namely, the first side surface 421, the second side surface 422, the third side surface 423 and the fourth side surface 424. The first drain electrode portion 521 covers the first side surface 421 of the semiconductor layer 40, reduces the light-receiving area of ​​the first side surface 421 of the semiconductor layer 40, increases the light-shielding area of ​​the TFT device, reduces the leakage current of the TFT device, and prolongs the service life of the TFT device.

[0061] See also Figure 1 and Figure 2 , a portion of the first drain electrode portion 521 covers a portion of the first side surface 421 ; or, a portion of the first drain electrode portion 521 completely covers the first side surface 421 .

[0062] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer 40 includes a second side surface 422 , and the second side surface 422 is disposed opposite to the first side surface 421 ;

[0063] The drain electrode 52 includes a second drain electrode portion 522, the second drain electrode portion 522 is arranged opposite to the first drain electrode portion 521, a portion of the second drain electrode portion 522 covers at least a portion of the second side surface 422, and another portion of the second drain electrode portion 522 is arranged on the upper surface of the semiconductor layer 40;

[0064] At least a portion of the source electrode 51 is located between the first drain electrode portion 521 and the second drain electrode portion 522 .

[0065] See also Figure 2 In this embodiment, the second drain electrode portion 522 covers the second side surface 422 of the semiconductor layer 40, which reduces the light-receiving area of ​​the second side surface 422 of the semiconductor layer 40, increases the light-shielding area of ​​the TFT device, reduces the leakage current of the TFT device, and prolongs the service life of the TFT device.

[0066] See also Figure 1 and Figure 2 , a portion of the second drain electrode portion 522 covers a portion of the second side surface 422 ; or, a portion of the second drain electrode portion 522 completely covers the second side surface 422 .

[0067] In one embodiment of the present application, the drain electrode 52 further includes a third drain electrode portion 523 , the third drain electrode portion 523 connects the first drain electrode portion 521 and the second drain electrode portion 522 , and forms a notch pattern 70 on the upper surface of the semiconductor layer 40 ;

[0068] At least a portion of the source electrode 51 extends between the first drain electrode portion 521 and the second drain electrode portion 522 , and the source electrode 51 is spaced apart from the third drain electrode portion 523 .

[0069] See also Figure 1 In the top view of the array substrate 100, the first drain electrode portion 521, the third drain electrode portion 523 and the second drain electrode portion 522 are connected to each other and formed in one piece. The third drain electrode portion 523 increases the contact area between the drain electrode 52 and the semiconductor layer 40, reduces the internal resistance of the TFT device, and increases the on-state current of the TFT device.

[0070] Compared to Figure 4 and Figure 5 The conventional array substrate 100 shown in FIG. Figure 2 and Figure 3 In the array substrate 100 shown, since the first side 421, the second side 422, and the third side 423 of the semiconductor layer 40 are all covered by the second metal layer 50, the contact area between the second metal layer 50 and the semiconductor layer 40 is increased, the internal resistance of the TFT device is reduced, and the on-state current of the TFT device is increased.

[0071] Please refer to Figure 1 The first drain electrode portion 521, the third drain electrode portion 523 and the second drain electrode portion 522 form a notch pattern 70. In a direction perpendicular to the plane where the substrate 10 is located, the notch pattern 70 is arranged in the direction where the fourth side surface 424 is located. A portion of the source electrode 51 extends between the first drain electrode portion 521 and the second drain electrode portion 522, and is spaced apart from the third drain electrode portion 523. Another portion of the source electrode 51 covers the fourth side surface 424. At this time, since the outer side surface of the source electrode 51 is arranged corresponding to the inner side wall of the notch pattern 70, the width-to-length ratio (W / L) of the TFT device is improved, thereby improving the carrier mobility of the TFT device.

[0072] The outer side surface of the source electrode 51 is disposed corresponding to the inner side wall of the notch pattern 70 .

[0073] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer includes a third side surface, and the third side surface connects the first side surface and the second side surface;

[0074] A portion of the third drain portion 523 covers at least a portion of the third side surface 423 of the semiconductor layer 40 and connects a portion of the first drain portion 521 covering the first side surface 421 and a portion of the second drain portion 522 covering the second side surface 422;

[0075] Another portion of the third drain electrode portion 523 is disposed on the upper surface of the semiconductor layer 40 and connects a portion of the first drain electrode portion 521 disposed on the upper surface of the semiconductor layer 40 and a portion of the second drain electrode portion 522 disposed on the upper surface of the semiconductor layer 40 .

[0076] See also Figure 3 In this embodiment, the third drain electrode portion 523 covers the third side surface 423 of the semiconductor layer 40, which reduces the light-receiving area of ​​the third side surface 423 of the semiconductor layer 40, increases the light-shielding area of ​​the TFT device, reduces the leakage current of the TFT device, and prolongs the service life of the TFT device.

[0077] See also Figure 1 and Figure 3 , a portion of the third drain electrode portion 523 covers a portion of the third side surface 423 ; or, a portion of the third drain electrode portion 523 completely covers the third side surface 423 .

[0078] In one embodiment of the present application, the semiconductor layer 40 includes:

[0079] A first deposition layer 41, disposed on the first insulating layer 30; and

[0080] A second deposition layer 42, covering the first deposition layer 41;

[0081] The first drain portion 521 , the second drain portion 522 , and the third drain portion 523 are overlapped on the outer surface of the second deposition layer 42 , and the carrier mobility of the second deposition layer 42 is greater than the carrier mobility of the first deposition layer 41 .

[0082] In this embodiment, the materials of the first deposition layer 41 and the second deposition layer 42 are amorphous silicon (a-Si), the first deposition layer 41 is an amorphous silicon deposition layer formed on the first insulating layer 30 at a relatively low molding speed, and the second deposition layer 42 is an amorphous silicon deposition layer formed on the outer surface of the first deposition layer 41 at a relatively high molding speed. Compared with the first deposition layer 41 and the second deposition layer 42, the film quality of the first deposition layer 41 is better, so the carrier mobility of the first deposition layer 41 is higher, and the resistance of the first deposition layer 41 is lower; the film quality of the second deposition layer 42 is poor, so the carrier mobility of the second deposition layer 42 is lower, and the resistance of the second deposition layer 42 is higher.

[0083] Since the first metal layer 20 is located below the second metal layer 50 in this embodiment, the TFT device in the embodiment is a bottom gate structure, the first deposition layer 41 serves as the front channel of the semiconductor layer 40, and the second deposition layer 42 serves as the back channel of the semiconductor layer 40. When a threshold voltage is applied to the first metal layer 20, a conductive channel is formed in the first deposition layer 41, so that the source 51 and the drain 52 are turned on.

[0084] The first drain portion 521, the second drain portion 522 and the third drain portion 523 are overlapped on the outer surface of the second deposition layer 42, reducing the illuminated area of ​​the outer surface of the second deposition layer 42, increasing the shading area of ​​the TFT device, reducing the leakage current of the TFT device, and extending the service life of the TFT device.

[0085] The thickness of the first deposition layer 41 is 400 angstroms. To 600 Angstroms The thickness of the second deposition layer 42 is within the range of 500 angstroms. To 1500 Angstroms within the range.

[0086] In an embodiment of the present application, the semiconductor layer 40 further includes a doping layer 43 , and the doping layer 43 is located between the second metal layer 50 and the second deposition layer 42 .

[0087] Please refer to Figure 5 In the conventional array substrate 100 shown, the second metal layer 50 is directly overlapped with the semiconductor layer 40 to form a Schottky contact. At this time, the internal resistance of the TFT device is relatively large, resulting in a decrease in the on-state current of the TFT device.

[0088] Phosphorus (P) is doped into the surface of the second deposition layer 42 made of amorphous silicon to make part of the second deposition layer 42 doped with phosphorus conductive, forming an N+ doped layer 43. The drain 52 and the source 51 of the second metal layer 50 are overlapped with the doped layer 43. At this time, the second metal layer 50 forms an ohmic contact with the semiconductor layer 40, which reduces the internal resistance of the TFT device and increases the on-state current of the TFT device.

[0089] The thickness of the doping layer 43 is 50 angstroms. To 300 Angstroms within the range.

[0090] In one embodiment of the present application, the outer peripheral surface of the semiconductor layer 40 includes a fourth side surface 424, the fourth side surface 424 connects the first side surface 421 and the second side surface 422, and the fourth side surface 424 is arranged opposite to the third side surface 423;

[0091] A portion of the source electrode 51 is disposed on the upper surface of the semiconductor layer 40 and extends into the notch pattern 70, and is spaced apart from a portion of the first drain electrode portion 521 disposed on the upper surface of the semiconductor layer 40, a portion of the second drain electrode portion 522 disposed on the upper surface of the semiconductor layer 40, and a portion of the third drain electrode portion 523 disposed on the upper surface of the semiconductor layer 40;

[0092] Another portion of the source electrode 51 is disposed on the fourth side surface 424 and is spaced apart from a portion of the first drain electrode portion 521 disposed on the first side surface 421 and a portion of the second drain electrode portion 522 disposed on the second side surface 422 .

[0093] See also Figure 3 The source electrode 51 covers the fourth side surface 424 of the semiconductor layer 40, which reduces the light-receiving area of ​​the fourth side surface 424 of the semiconductor layer 40, increases the light-shielding area of ​​the TFT device, reduces the leakage current of the TFT device, and prolongs the service life of the TFT device.

[0094] The manufacturing method of the array substrate 100 of the present application includes the following steps:

[0095] Step 101 : forming a first metal layer 20 on a substrate 10 .

[0096] Step 102: patterning the first metal layer 20 to form a gate of a TFT device.

[0097] Step 103 : forming a first insulating layer 30 on the substrate 10 , wherein the first insulating layer 30 covers the patterned first metal layer 20 .

[0098] Step 104 : forming a first deposition layer 41 on the first insulating layer 30 .

[0099] Step 105 : forming a second deposition layer 42 on the first deposition layer 41 , wherein the second deposition layer 42 covers the outer surface of the first deposition layer 41 , and a deposition speed of the second deposition layer 42 is faster than a deposition speed of the first deposition layer 41 .

[0100] Step 106 : forming a doping layer 43 on the second deposition layer 42 , wherein the first deposition layer 41 , the second deposition layer 42 and the doping layer 43 form a semiconductor layer 40 .

[0101] Step 107 : forming a second metal layer 50 on the first insulating layer 30 , wherein the second metal layer 50 covers the semiconductor layer 40 .

[0102] Step 108: Pattern the second metal layer 50 to form a source electrode 51 and a drain electrode 52, wherein a portion of the source electrode 51 is disposed on the upper surface of the semiconductor layer 40, and another portion of the source electrode 51 covers the outer side surface of the semiconductor layer 40; a portion of the drain electrode 52 is disposed on the upper surface of the semiconductor layer 40, and another portion of the drain electrode 52 covers the outer side surface of the semiconductor layer 40.

[0103] Step 109 : forming a passivation layer 60 on the first insulating layer 30 , wherein the passivation layer 60 covers the semiconductor layer 40 and the patterned second metal layer 50 .

[0104] In one embodiment of the present application, the second metal layer 50 further includes:

[0105] A first wiring 81, the first wiring 81 is connected to a portion of the third drain portion 523 disposed on the third side surface 423; and

[0106] The second wiring 82 is connected to a portion of the source 51 disposed on the fourth side surface 424 .

[0107] The first wiring 81 is electrically connected to the drain 52 , and the first wiring 81 is used to connect the drain 52 and a device corresponding thereto.

[0108] The second wiring 82 is electrically connected to the source 51. The second wiring 82 is used to connect the source 51 and the corresponding device.

[0109] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first metal layer, disposed on the substrate; a first insulating layer, disposed on the substrate and covering the first metal layer; A semiconductor layer, disposed on the first insulating layer; a second metal layer, comprising a source electrode and a drain electrode, wherein at least a portion of the source electrode is disposed on an upper surface of the semiconductor layer, a portion of the drain electrode is disposed on an upper surface of the semiconductor layer, and another portion of the drain electrode covers at least a portion of an outer peripheral surface of the semiconductor layer; and a passivation layer, disposed on the first insulating layer and covering the semiconductor layer and the second metal layer; Wherein, in a direction perpendicular to the plane where the substrate is located, the semiconductor layer overlaps with the first metal layer.

2. The array substrate according to claim 1, characterized in that: The outer peripheral surface of the semiconductor layer includes a first side surface; The drain electrode includes a first drain electrode portion, a portion of which covers at least a portion of the first side surface, and another portion of the first drain electrode portion is disposed on the upper surface of the semiconductor layer and is spaced apart from the source electrode.

3. The array substrate according to claim 2, characterized in that: The outer peripheral surface of the semiconductor layer includes a second side surface, and the second side surface is arranged opposite to the first side surface; The drain electrode includes a second drain electrode portion, the second drain electrode portion is arranged opposite to the first drain electrode portion, a portion of the second drain electrode portion covers at least a portion of the second side surface, and another portion of the second drain electrode portion is arranged on the upper surface of the semiconductor layer; Wherein, at least a portion of the source is located between the first drain portion and the second drain portion.

4. The array substrate according to claim 3, characterized in that: The drain electrode further includes a third drain electrode portion, the third drain electrode portion connects the first drain electrode portion and the second drain electrode portion and forms a notch pattern on the upper surface of the semiconductor layer; Wherein, at least a portion of the source electrode extends between the first drain electrode portion and the second drain electrode portion, and the source electrode is spaced apart from the third drain electrode portion.

5. The array substrate according to claim 4, characterized in that: The outer peripheral surface of the semiconductor layer includes a third side surface, and the third side surface connects the first side surface and the second side surface; A portion of the third drain portion covers at least a portion of the third side surface of the semiconductor layer, and connects a portion of the first drain portion covering the first side surface and a portion of the second drain portion covering the second side surface; Another portion of the third drain portion is disposed on the upper surface of the semiconductor layer and connects the portion of the first drain portion disposed on the upper surface of the semiconductor layer and the portion of the second drain portion disposed on the upper surface of the semiconductor layer.

6. The array substrate according to claim 5, characterized in that: The semiconductor layer comprises: A first deposition layer is disposed on the first insulating layer; and a second deposition layer, covering the first deposition layer; The first drain portion, the second drain portion, and the third drain portion overlap the outer surface of the second deposition layer, and the carrier mobility of the second deposition layer is greater than the carrier mobility of the first deposition layer.

7. The array substrate according to claim 6, characterized in that: The semiconductor layer further includes a doping layer, and the doping layer is located between the second metal layer and the second deposition layer.

8. The array substrate according to claim 5, characterized in that: The outer peripheral surface of the semiconductor layer includes a fourth side surface, the fourth side surface connects the first side surface and the second side surface, and the fourth side surface is arranged opposite to the third side surface; A portion of the source electrode is disposed on the upper surface of the semiconductor layer and extends into the notch pattern, and is spaced apart from a portion of the first drain electrode portion disposed on the upper surface of the semiconductor layer, a portion of the second drain electrode portion disposed on the upper surface of the semiconductor layer, and a portion of the third drain electrode portion disposed on the upper surface of the semiconductor layer; Another portion of the source electrode is disposed on the fourth side surface and is spaced apart from a portion of the first drain electrode portion disposed on the first side surface and a portion of the second drain electrode portion disposed on the second side surface.

9. The array substrate according to claim 8, characterized in that: The second metal layer further includes: a first wiring connected to a portion of the third drain portion disposed on the third side surface; and A second wiring is connected to a portion of the source electrode disposed on the fourth side surface.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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