Integrated circuit
By adopting the quasi-super junction structure and conductive plate design in the integrated circuit, the problem of medium and high power dissipation value reduction in the scale of the integrated circuit is solved, the collapse voltage and stability are improved, and the manufacturing and processing complexity is reduced.
Patent Information
- Application Number
- CN202420193126.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-25
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2034-01-25
AI Technical Summary
Integrated circuits face high power dissipation values during scale reduction, resulting in increased manufacturing and processing complexity, making it difficult to effectively reduce costs and improve efficiency.
A quasi-super junction structure including p-type substrate region, n-type region, p-type epitaxy region and doped region is adopted, and the vertical overlap between the conductive plate and the gate and doped region is reduced to the high electric field region and increase the collapse voltage. .
The collapse voltage of the integrated circuit is improved, the stability of the semiconductor device is increased, the high electric field at the edge of the junction between the p-type doped region and the n-well region is reduced, and the overall performance of the device is improved.
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Figure CN222261075U_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to an integrated circuit. Background Art
[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generation after generation of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and in order to achieve these advances, similar developments in IC processing and manufacturing are needed. In the process of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometric size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) decreases. This process of scale reduction generally provides benefits by improving production efficiency and reducing associated costs. This scale reduction also produces relatively high power dissipation values. Utility Model Content
[0003] In some embodiments of the present disclosure, an integrated circuit includes a substrate. The substrate includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region; and a p-type doped region within the second n-type region. An isolation structure is above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region is vertically below the isolation structure. A drain electrode is electrically coupled to the first n-type region. A gate electrode is electrically coupled to the p-type doped region. A source electrode is electrically coupled to the second n-type region.
[0004] In some embodiments of the present disclosure, an integrated circuit includes an input terminal and an output terminal. The transformer includes a main winding and a secondary winding, the main winding is electrically coupled to the input terminal, and the secondary winding is electrically coupled to the output terminal. The synchronous rectifier is electrically coupled between the secondary winding of the transformer and the output terminal. The synchronous rectifier controller is electrically coupled to the synchronous rectifier. The synchronous rectifier controller includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region; a p-type doped region within the second n-type region; an isolation structure above the p-type substrate region; a drain electrode electrically coupled to the first n-type region; a gate electrode electrically coupled to the p-type doped region; a source electrode electrically coupled to the second n-type region; and a conductive plate above the isolation structure, wherein the conductive plate is laterally located between the drain electrode and the gate electrode.
[0005] In some embodiments of the present disclosure, an integrated circuit includes a substrate. The substrate includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region, wherein in a top view, the first p-type epitaxial region has a ring-shaped top profile; and a p-type doped region within the second n-type region. An isolation structure is above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region is vertically below the isolation structure, and the first p-type epitaxial region extends from a top surface of the p-type substrate region to a bottom surface of the isolation structure. A drain electrode is electrically coupled to the first n-type region. A gate electrode is electrically coupled to the p-type doped region. A source electrode is electrically coupled to the second n-type region. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] The aspects of this disclosure are in accordance with the attached Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
[0007] Figure 1 is a circuit diagram of an integrated circuit according to some embodiments of the present disclosure;
[0008] Figure 2A is a top view of a semiconductor device according to some embodiments of the present disclosure;
[0009] Figure 2B is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
[0010] Figure 3 is a top view of a semiconductor device according to some embodiments of the present disclosure;
[0011] 4A to 4F is a top view of a semiconductor device according to some embodiments of the present disclosure;
[0012] Figures 5 to 10 illustrates semiconductor devices at different manufacturing stages according to some embodiments of the present disclosure;
[0013] Fig.11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.
[0014]
Explanation of symbols
[0015] 100: Converter
[0016] 110: Half-bridge switching circuit
[0017] 120: Clamping circuit
[0018] 130: Flyback controller
[0019] 140: Transformer
[0020] 150: Synchronous rectifier
[0021] 160:Synchronous rectifier controller
[0022] 170: Load
[0023] 200:Semiconductor devices
[0024] 202:Substrate
[0025] 204: p-type substrate region
[0026] 210: p-type epitaxial region
[0027] 210A: Part 1
[0028] 210B: Part 2
[0029] 211: p-type epitaxial layer
[0030] 212: p-type epitaxial region
[0031] 212A: Part 1
[0032] 212B: Part 2
[0033] 214: p-type epitaxial region
[0034] 220:n Well Area
[0035] 222:n Well Area
[0036] 222A: Part 1
[0037] 222B: Part 2
[0038] 224:n Well Area
[0039] 224A: Part 1
[0040] 224B: Part 2
[0041] 226:p Well Area
[0042] 226A: Part 1
[0043] 226B: Part 2
[0044] 230: p-type doped region
[0045] 230A: Part I
[0046] 230B: Part 2
[0047] 232: Deep P Well Area
[0048] 232A: Part 1
[0049] 232B: Part 2
[0050] 240: n-type heavily doped region
[0051] 242: p-type heavily doped region
[0052] 242A: Part 1
[0053] 242B: Part 2
[0054] 244: n-type heavily doped region
[0055] 244A: Part 1
[0056] 244B: Part 2
[0057] 246: p-type heavily doped region
[0058] 246A: Part 1
[0059] 246B: Part 2
[0060] 250: Silicide layer
[0061] 260: Drain electrode
[0062] 262: Gate electrode
[0063] 262A: Part 1
[0064] 262B: Part 2
[0065] 264: Source electrode
[0066] 264A: Part 1
[0067] 264B: Part 2
[0068] 266: Pickup Electrode
[0069] 266A: Part 1
[0070] 266B: Part 2
[0071] 270: Dielectric layer
[0072] 270A: Part 1
[0073] 270B: Part 2
[0074] 272: Conductive plate
[0075] 272A: Part 1
[0076] 272B: Part 2
[0077] 274: Contact
[0078] 274A: Part 1
[0079] 274B: Part 2
[0080] 300A~300F: Isolation structure
[0081] Ld: Length
[0082] Lk1~Lk3: Length
[0083] Ln: Width
[0084] L od :length
[0085] Lp: Width
[0086] Ls: Length
[0087] Ls1~Ls2: length
[0088] L poly :length
[0089] MA1~MA3: Patterned mask
[0090] Np: Main winding
[0091] Ns: Secondary winding DETAILED DESCRIPTION
[0092] The following disclosure provides many different embodiments, or examples, for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.
[0093] In addition, for ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature illustrated in the figures to another (multiple) element or feature. Spatially relative terms are intended to cover different orientations of the device when in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly. As used herein, "approximately", "about", "roughly", or "substantially" may generally refer to within 20%, within 10%, or within 5% of a given value or range. The quantities given herein are approximate, meaning that the terms "approximately", "about", "roughly", or "substantially" may be inferred without explicit statement. However, those skilled in the art will recognize that the values or ranges mentioned throughout the specification are merely examples and may be reduced or changed as the scale of the integrated circuit is reduced.
[0094] Figure 1 1 is a circuit diagram of an integrated circuit according to some embodiments of the present disclosure. The figure shows a circuit diagram of an integrated circuit 100. In some embodiments, the integrated circuit 100 is a converter, which can also be referred to as a converter 100. The converter 100 includes a half-bridge switching circuit 110, which includes a high-side switch M1 and a low-side switch M2 connected in series. In some embodiments, the drain of the high-side switch M1 is electrically coupled to the input terminal AC Vin via a clamp circuit 120. The clamp circuit 120 includes a clamp capacitor C1 and a resistor R1 connected in parallel.
[0095] The gates of the high-side switch M1 and the low-side switch M2 are connected to and driven by a flyback controller 130. In some embodiments, the flyback controller 130 is used to drive the high-side switch M1 and the low-side switch M2. The source of the high-side switch M1 is electrically coupled to the drain of the low-side switch M2. The source of the low-side switch M2 is grounded.
[0096] The converter 100 further includes a transformer 140. The transformer 140 provides electrical isolation between the primary side and the secondary side of the converter 100. According to some embodiments, the transformer 140 may be formed by two transformer windings. For example, the transformer 140 may include a primary winding N p And the secondary winding N s .exist Figure 1 In the example, the main winding N p It can be regarded as the input winding of the converter 100, and the secondary winding N s It can be regarded as the output winding of the converter 100. The main winding Np Furthermore, the clamp circuit 120 is coupled to the primary winding N of the transformer 140 via the high-side switch M1. p superior.
[0097] The converter 100 further includes a synchronous rectifier 150 at the secondary side of the converter 100 and electrically coupled to the transformer 140 to convert an AC polarity waveform received from the output of the transformer 140 into a unipolar waveform. In some embodiments, the synchronous rectifier 150 may include a switch M3. The gate of the switch M3 is electrically coupled to a synchronous rectifier controller 160. In some embodiments, the synchronous rectifier controller 160 may include a high-voltage junction field effect transistor (HV JFET), which will be discussed below.
[0098] The converter 100 further includes an output capacitor C2 and a load 170 electrically coupled to the synchronous rectifier 150. An output terminal is provided for the load 170 and may provide an output voltage DC Vout. In some embodiments, the load 170 may include a resistor R2 and a resistor R3 connected in series.
[0099] The embodiments of the present disclosure also provide a method for forming the converter 100. For example, a method includes forming a half-bridge switch circuit 110, a clamp circuit 120, a flyback controller 130, a transformer 140, a synchronous rectifier 150, a synchronous rectifier controller 160, an output capacitor C2, and a load 170. The method further includes forming suitable windings to electrically couple the above components, thereby serving as the converter 100.
[0100] Figure 2A FIG. 4 is a top view of a semiconductor device according to some embodiments of the present disclosure. Figure 2B is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. In more detail, Figure 2B For along Figure 2A It should be noted that for simplicity, Figure 2B Some components in the cross-sectional view are not shown. Figure 2A is shown in a top view.
[0101] Figure 2A and Figure 2BThe semiconductor device 200 is shown. In some embodiments, the semiconductor device 200 is a junction field effect transistor (JFET). More specifically, the semiconductor device 200 is a high-voltage junction field effect transistor (HV JFET), and the semiconductor device 200 can be used for Figure 1 . Here, the term "high voltage (HV) device" may refer to a device having a high breakdown voltage. For example, the breakdown voltage of the semiconductor device 200 is greater than about 100V. In some embodiments, the breakdown voltage of the semiconductor device 200 is in the range of about 100V to about 200V.
[0102] The semiconductor device 200 includes a substrate 202. The substrate 202 may include a crystalline silicon structure. Alternatively, the substrate 202 may be formed of other semiconductor materials such as silicon germanium.
[0103] In some embodiments, the substrate 202 may include a p-type substrate region 204 at the bottom of the substrate 202. The p-type substrate region 204 is doped with p-type impurities. In some embodiments, the p-type impurity concentration of the p-type substrate region 204 may be about 1×10 14 cm -3 About 1×10 15 cm -3 In some embodiments, the p-type substrate region 204 has a vertical thickness in a range of about 500 μm to about 1000 μm. The p-type substrate region 204 has a resistivity in a range of about 10 ohm-cm to about 100 ohm-cm.
[0104] The semiconductor device 200 further includes isolation structures 300A, 300B, 300C, 300D, 300E, and 300F disposed in the substrate 202. In some embodiments, the top surfaces of the isolation structures 300A, 300B, 300C, 300D, 300F, and 300F may be substantially flush with the top surface of the substrate 202. In some embodiments, the isolation structures 300A, 300B, 300C, 300D, 300F, and 300F may be shallow trench isolation (STI) structures and may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like.
[0105] The semiconductor device 200 further includes p-type epitaxial regions 210 and 212 in the substrate 202. In some embodiments, the p-type epitaxial regions 210 and 212 are p-type doped regions in the substrate 202 and may include the same impurities as the p-type substrate region 204. In some embodiments, the p-type impurity concentrations of the p-type epitaxial regions 210 and 212 are the same. For example, the p-type impurity concentrations of the p-type epitaxial regions 210 and 212 may be about 1×10 14 cm -3 About 1×10 15 cm -3 within the range.
[0106] The semiconductor device 200 further includes n-well regions 220, 222, and 224 doped with n-type impurities in the substrate 202. Exemplary n-type dopants may include phosphorus (P), arsenic (As), or antimony (Sb), or the like. In some embodiments, the n-type impurity concentration of the n-well regions 220, 222, and 224 may be about 1×10 12 cm -3 About 1×10 13 cm -3 In some embodiments, the n-well regions 220, 222, and 224 may also be referred to as high-voltage n-well (HVNW) regions.
[0107] The semiconductor device 200 further includes a p-well region 226 doped with p-type impurities in the substrate 202. For example, the p-type impurity concentration of the p-well region 226 may be about 1×10 12 cm -3 About 1×10 13 cm -3 In some embodiments, the p-well region 226 may also be referred to as a high-voltage p-well (HVPW) region.
[0108] like Figure 2A As shown in the top view of FIG. 1 , each of the p-type epitaxial regions 210 and 212 may include a rectangular ring-shaped top profile. Figure 2A Although not shown in the figure, each of the n-well regions 222 and 224, and the p-well region 226 may include a rectangular ring top profile. The p-type epitaxial region 210 surrounds the n-well region 220. The n-well region 222 surrounds the p-type epitaxial region 210. The p-type epitaxial region 212 surrounds the n-well region 222. The n-well region 224 surrounds the p-type epitaxial region 212. The p-well region 226 surrounds the n-well region 224. In some embodiments, Figure 2A In the top view of FIG. 8 , the length and width of the p-type epitaxial region 212 are greater than the length and width of the p-type epitaxial region 210 .
[0109] like Figure 2BAs shown in the cross-sectional view of , each of the p-type epitaxial regions 210 and 212 may include two separate portions. For example, the p-type epitaxial region 210 may include a first portion 210A and a second portion 210B. Similarly, the p-type epitaxial region 212 may include a first portion 212A and a second portion 212B. In some embodiments, the distance between the first portion 210A and the second portion 210B of the p-type epitaxial region 210 is less than the distance between the first portion 212A and the second portion 212B of the p-type epitaxial region 212.
[0110] Still reference Figure 2B , the p-type epitaxial regions 210 and 212 may extend from the top surface of the p-type substrate region 204 to the bottom surface of the respective isolation structures. For example, the first portion 210A of the p-type epitaxial region 210 and the first portion 212A of the p-type epitaxial region 212 extend from the top surface of the p-type substrate region 204 to the bottom surface of the isolation structure 300D. Similarly, the second portion 210B of the p-type epitaxial region 210 and the second portion 212B of the p-type epitaxial region 212 extend from the top surface of the p-type substrate region 204 to the bottom surface of the isolation structure 300C. In some embodiments, the vertical thickness of the p-type epitaxial regions 210 and 212 is in the range of about 5 μm to about 10 μm. The resistivity of the p-type epitaxial regions 210 and 212 is in the range of about 10 ohm-cm to about 100 ohm-cm.
[0111] exist Figure 2B In the cross-sectional view of , the n-well region 222 may also include two separate portions. For example, the n-well region 222 may include a first portion 222A and a second portion 222B. Figure 2B , the first portion 222A of the n-well region 222 is laterally located between the first portion 210A of the p-type epitaxial region 210 and the first portion 212A of the p-type epitaxial region 212. Similarly, the second portion 222B of the n-well region 222 is laterally located between the second portion 210B of the p-type epitaxial region 210 and the second portion 212B of the p-type epitaxial region 212. The n-well region 222 may also extend from the top surface of the p-type substrate region 204 to the bottom surface of the respective isolation structures (e.g., isolation structures 300C and 300D).
[0112] From another aspect, the p-type epitaxial regions 210 and 212 are inserted into the n-well regions 220, 222, and 224. As a result, the n-well region 220, the p-type epitaxial region 210, the n-well region 222, the p-type epitaxial region 212, and the n-well region 224 together form a quasi-super junction structure. Here, the term "quasi-super junction structure" is a structure constructed by alternately configuring n-type impurity regions and p-type impurity regions. The quasi-super junction structure helps to increase the breakdown voltage of the device for n / p-type charge balance. Therefore, the quasi-super junction structure is conducive to maintaining a high breakdown voltage, and thus will increase the breakdown voltage of the semiconductor device 200.
[0113] In the depicted embodiment, the number of p-type epitaxial regions is two (e.g., p-type epitaxial regions 210 and 212), but the present disclosure is not limited thereto. In other embodiments, more or fewer p-type epitaxial regions may also be used. For example, in some other embodiments, a single p-type epitaxial region is sandwiched between two n-well regions. In still other embodiments, multiple p-type epitaxial regions and n-well regions may be alternately disposed above the p-type substrate region 204.
[0114] Each of the first portion 210A and the second portion 210B of the p-type epitaxial region 210 may include a lateral width Lp. Similarly, each of the first portion 212A and the second portion 212B of the p-type epitaxial region 212 may include a lateral width Lp. That is, the first portion 210A and the second portion 210B of the p-type epitaxial region 210 may include substantially the same width as the first portion 212A and the second portion 212B of the p-type epitaxial region 212, respectively. On the other hand, each of the first portion 222A and the second portion 222B of the n-well region 222 may include a lateral width Ln. In some embodiments, the lateral width Lp is substantially equal to the lateral width Ln.
[0115] In some embodiments, the width Lp is in a range of about 0.5 μm to about 2 μm. In some embodiments, the width Lp is in a range of about 0.5 μm to about 2 μm. If the widths Lp and Ln are too small (e.g., much smaller than 0.5 μm), the p-type epitaxial regions 210 and 212 and the n-well region 222 may not be able to improve the device breakdown voltage. If the widths Lp and Ln are too large (e.g., much larger than 2 μm), the device performance may not be significantly improved.
[0116] The semiconductor device 200 further includes a p-type doped region 230 and a deep p-well region 232 in the substrate 202. In more detail, the p-type doped region 230 is in the n-well region 224, and the deep p-well region 232 is in the p-type substrate region 204. The p-type impurity concentration of the p-type doped region 230 may be about 1×10 13 cm -3 About 1×10 14 cm -3 The p-type impurity concentration of the deep p-well region 232 may be about 1×10 12 cm -3 About 1×10 13 cm -3 within the range.
[0117] Similarly, the p-type doped region 230 and the deep p-well region 232 may also include a rectangular ring-shaped top profile. Figure 2BIn the cross-sectional view of , each of the p-type doped region 230 and the deep p-well region 232 may include two separate portions. For example, the p-type doped region 230 includes a first portion 230A and a second portion 230B. The deep p-well region 232 includes a first portion 232A and a second portion 232B.
[0118] In some embodiments, the p-type doped region 230 may vertically overlap the deep p-well region 232. The p-type doped region 230 and the deep p-well region 232 may include substantially the same width. For example, the first portion 230A of the p-type doped region 230 vertically overlaps the first portion 232A of the deep p-well region 232. Similarly, the second portion 230B of the p-type doped region 230 vertically overlaps the second portion 232B of the deep p-well region 232. In some embodiments, the opposite sidewalls of the first portion 230A of the p-type doped region 230 may be vertically aligned with the opposite sidewalls of the first portion 232A of the deep p-well region 232. Similarly, the opposite sidewalls of the second portion 230B of the p-type doped region 230 are vertically aligned with the opposite sidewalls of the second portion 232B of the deep p-well region 232.
[0119] The p-type doping region 230 may contact the isolation structures 300B, 300C, 300D, and 300E. For example, the first portion 230A of the p-type doping region 230 contacts the sidewalls and bottom surfaces of the isolation structures 300D and 300E. The second portion 230B of the p-type doping region 230 contacts the sidewalls and bottom surfaces of the isolation structures 300B and 300C.
[0120] The deep p-well region 232 is in the p-type substrate region 204 , so the bottom surface of the deep p-well region 232 is lower than the top surface of the p-type substrate region 204 . In some embodiments, the bottom surface of the deep p-well region 232 is lower than the bottom surfaces of the p-type epitaxial regions 210 and 212 .
[0121] The semiconductor device 200 further includes an n-type heavily doped region 240, a p-type heavily doped region 242, an n-type heavily doped region 244, and a p-type heavily doped region 246 in the substrate 202. The n-type impurity concentration of the n-type heavily doped regions 240 and 244 may be about 1×10 14 cm -3 About 1×10 15 cm -3 The p-type impurity concentration of the p-type heavily doped regions 242 and 246 may be about 1×10 14 cm -3 About 1×10 15 cm -3 In some embodiments, the n-type heavily doped region 240 may also be referred to as a drain region. The p-type heavily doped region 242 may also be referred to as a gate region. The n-type heavily doped region 244 may also be referred to as a source region. The p-type heavily doped region 246 may also be referred to as a pickup region.
[0122] Similarly, the n-type heavily doped region 244 and the p-type heavily doped regions 242 and 246 may also include a rectangular ring-shaped top profile. Figure 2B In the cross-sectional view of , each of the n-type heavily doped region 244 and the p-type heavily doped regions 242 and 246 may include two separate portions. For example, the p-type heavily doped region 242 includes a first portion 242A and a second portion 242B. The n-type heavily doped region 244 includes a first portion 244A and a second portion 244B. The p-type heavily doped region 246 includes a first portion 246A and a second portion 246B.
[0123] In more detail, the n-type heavily doped region 240 is in the n-well region 220. The first portion 242A and the second portion 242B of the p-type heavily doped region 242 are respectively in the first portion 230A and the second portion 230B of the p-type doped region 230. The first portion 244A and the second portion 244B of the n-type heavily doped region 244 are respectively in the first portion 224A and the second portion 224B of the n-well region 224. The first portion 246A and the second portion 246B of the p-type heavily doped region 246 are respectively in the first portion 226A and the second portion 226B of the p-well region 226.
[0124] The semiconductor device 200 further includes a silicide layer 250 over the substrate 202. In more detail, the silicide layer 250 contacts the n-type heavily doped region 240, the p-type heavily doped region 242, the n-type heavily doped region 244, and the p-type heavily doped region 246. In some embodiments, the silicide layer 250 may include a metal silicide, such as cobalt silicide, titanium silicide, or the like.
[0125] Semiconductor device 200 further includes drain electrode 260, gate electrode 262, source electrode 264, and pickup electrode 266. In some embodiments, drain electrode 260, gate electrode 262, source electrode 264, and pickup electrode 266 may include metals such as aluminum, copper, tungsten, nickel, or the like.
[0126] The drain electrode 260 is electrically coupled to the n-type heavily doped region 240 and the n-well region 220. The gate electrode 262 is electrically coupled to the p-type heavily doped region 242, the p-type doped region 230, and the n-well region 224. The source electrode 264 is electrically coupled to the n-type heavily doped region 244 and the n-well region 224. The pickup electrode 266 is electrically coupled to the p-type heavily doped region 246 and the p-well region 226.
[0127] exist Figure 2A In the top view of FIG. 1 , each of the gate electrode 262, the source electrode 264, and the pickup electrode 266 may include a rectangular ring-shaped top profile. Figure 2BIn the cross-sectional view of , each of the gate electrode 262, the source electrode 264, and the pickup electrode 266 may include two separate portions. For example, the gate electrode 262 includes a first portion 262A and a second portion 262B. The source electrode 264 includes a first portion 264A and a second portion 264B. The pickup electrode 266 includes a first portion 266A and a second portion 266B.
[0128] In more detail, the drain electrode 260 is over the n-type heavily doped region 240 and electrically coupled to the n-type heavily doped region 240 via the silicide layer 250. The first portion 262A and the second portion 262B of the gate electrode 262 are over the first portion 242A and the second portion 242B of the p-type heavily doped region 242, respectively, and electrically coupled to the first portion 242A and the second portion 242B of the p-type heavily doped region 242 via the silicide layer 250. The first portion 264A and the second portion 264B of the source electrode 264 are over the first portion 244A and the second portion 244B of the n-type heavily doped region 244, respectively, and electrically coupled to the first portion 244A and the second portion 244B of the n-type heavily doped region 244 via the silicide layer 250. The first and second portions 266A and 266B of the pickup electrode 266 are respectively above and electrically coupled to the first and second portions 246A, 246B of the p-type heavily doped region 246 through the silicide layer 250 .
[0129] The semiconductor device 200 further includes a dielectric layer 270, a conductive plate 272 above the dielectric layer 270, and a contact 274 above the conductive plate 272. In some embodiments, the dielectric layer 270 may include a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like. In some embodiments, the conductive plate 272 includes a semiconductor material such as polysilicon. The use of polysilicon may include the advantage of compatibility with other devices (e.g., logic devices) without additional process steps. In other embodiments, the conductive plate 272 may include a metal, a metal alloy, or other suitable conductive material. The conductive plate 272 is used to reduce the high electric field at the junction edge between the n-well region 224 and the p-type doped region 230, thereby increasing the device breakdown voltage. In some embodiments, the contact 274 may include a metal such as aluminum, copper, tungsten, nickel, or the like.
[0130] exist Figure 2A In the top view of FIG. 1 , each of the conductive plate 272 and the contact 274 may include a rectangular ring-shaped top profile. Similarly, the dielectric layer 270 may also include a rectangular ring-shaped top profile. Figure 2BIn the cross-sectional view of , each of the dielectric layer 270, the conductive plate 272, and the contact 274 may include two separate parts. For example, the dielectric layer 270 includes a first part 270A and a second part 270B. The conductive plate 272 includes a first part 272A and a second part 272B. The contact 274 includes a first part 274A and a second part 274B.
[0131] In some embodiments, first portion 270A of dielectric layer 270 contacts the top surface of isolation structure 300D, first portion 272A of conductive plate 272 contacts the first portion 270A of dielectric layer 270, and first portion 274A of contact 274 contacts the first portion 272A of conductive plate 272. Similarly, second portion 270B of dielectric layer 270 contacts the top surface of isolation structure 300C, second portion 272B of conductive plate 272 contacts the second portion 270B of dielectric layer 270, and second portion 274B of contact 274 contacts the second portion 272B of conductive plate 272.
[0132] In some embodiments, the contact 274 is electrically coupled to a ground terminal. That is, the conductive plate 272 is grounded. The conductive plate 272 may vertically overlap a portion of the p-type doped region 230. For example, a first portion 272A of the conductive plate 272 vertically overlaps a first portion 230A of the p-type doped region 230, and a second portion 272B of the conductive plate 272 vertically overlaps a second portion 230B of the p-type doped region 230. The conductive plate 272 is at the edge of the p-type doped region 230 near the gate terminal (e.g., the gate electrode 262), which helps to reduce the high electric field at the junction edge between the p-type doped region 230 and the n-well region 224, and will further increase the device breakdown voltage. In some embodiments, the conductive plate 272 may vertically overlap a vertical boundary between the p-type doped region 230 and the n-well region 224. In addition, the conductive plate 272 may also vertically overlap a portion of the deep p-well region 232.
[0133] The conductive plate 272 is laterally offset from the p-type epitaxial region 212 by a length Ls. In some embodiments, the length Ls is in a range of about 0.5 μm to about 1 μm. The thickness of the conductive plate 272 is in a range of about 0.1 μm to about 0.3 μm. The thickness of the dielectric layer 270 is in a range of about to about The conductive plate 272 has a length L poly In some embodiments, the length L poly In the range of about 1 μm to about 5 μm.
[0134] The distance between the gate electrode 262 and the drain electrode 260 may be referred to as a drift length Ld, wherein the drift length Ld may also be the length of the isolation structure 300C (or the isolation structure 300D). In some embodiments, the drift length Ld is in a range of about 5 μm to about 15 μm. The distance between the gate electrode 262 and the source electrode 264 may be referred to as a length Ls1, wherein the length Ls1 may also be the length of the isolation structure 300B (or the isolation structure 300E). In some embodiments, the length Ls1 is in a range of about 2 μm to about 5 μm. The distance between the source electrode 264 and the pickup electrode 266 may be referred to as a length Ls2, wherein the length Ls2 may also be the length of the isolation structure 300A (or the isolation structure 300F). In some embodiments, the length Ls2 is in a range of about 2 μm to about 5 μm. In some embodiments, the drift length Ld is greater than the length Ls1 and the length Ls2.
[0135] The portion of the p-type doped region 230 (and the deep p-well region 232) vertically below the isolation structures 300C and 300D has a length Lk1. In some embodiments, the length Lk1 is in the range of about 0.5 μm to about 1 μm. The portion of the p-type doped region 230 (and the deep p-well region 232) vertically below the isolation structures 300B and 300F has a length Lk2. In some embodiments, the length Lk2 is in the range of about 0.5 μm to about 1 μm. The portion of the n-well region 224 vertically below the isolation structures 300A and 300F has a length Lk3. In some embodiments, the length Lk3 is in the range of about 0.5 μm to about 1 μm.
[0136] Each of the n-type heavily doped region 240 , the p-type heavily doped region 242 , the n-type heavily doped region 244 , and the p-type heavily doped region 246 includes a length L od In some embodiments, the length L od In the range of about 0.5 μm to about 2 μm.
[0137] Figure 3 FIG. 4 is a top view of a semiconductor device according to some embodiments of the present disclosure. Figure 3 Similar to Figure 2A , Figure 3 and Figure 2A The difference is Figure 3 The element has a circular ring-shaped top profile.
[0138] For example, Figure 3 As shown in FIG. 4 , the p-type epitaxial regions 210 and 212 , the conductive plate 272 , the contact 274 , the source electrode 264 , and the pickup electrode 266 include circular ring-shaped top profiles. Figure 2A Other elements including a rectangular ring top profile as described in the above may also include Figure 3 The donut-shaped top profile described in .
[0139] 4A to 4F FIG. 1 is a top view of a semiconductor device according to some embodiments of the present disclosure. 4A to 4F Some elements of the present invention are labeled identically, and for the sake of simplicity, the relevant details will not be repeated.
[0140] exist Figure 4A In the embodiment of the present invention, the semiconductor device 200 includes a first group of circumferentially arranged p-type epitaxial regions 210 and a second group of circumferentially arranged p-type epitaxial regions 212. The first group of p-type epitaxial regions 210 and the second group of p-type epitaxial regions 212 are arranged concentrically. Figure 4A The cross-sectional view can be similar to Figure 2B 210A and 210B (see Figure 2B ) is a separate p-type epitaxial region 210, and portions 212A and 212B (see Figure 2B ) is a separate p-type epitaxial region 212. Each of the p-type epitaxial regions 210 and 212 may be a dot-shaped structure, such as Figure 4A In some embodiments, each of the p-type epitaxial regions 210 and 212 may include a circular shape, a rectangular shape, or other suitable top profiles, but the present disclosure is not limited thereto.
[0141] exist Figure 4B , the semiconductor device 200 includes a first group of p-type epitaxial regions 210 arranged in a row (see the rectangular ring dashed line). In such an embodiment, the p-type epitaxial region 212 is omitted. In the first row, each side of the rectangular ring includes a single p-type epitaxial region 210. Each of the p-type epitaxial regions 210 can be a dot-like structure, such as Figure 4B shown in top view.
[0142] exist Figure 4C , the semiconductor device 200 includes a first group of p-type epitaxial regions 210 arranged in a first row (see the dotted line of the rectangular ring), and a second group of p-type epitaxial regions 212 arranged in a second row (see the dotted line of the rectangular ring), wherein the second row surrounds the first row. In the first row, each side of the rectangular ring includes a single p-type epitaxial region 210. Similarly, in the second row, each side of the rectangular ring includes a single p-type epitaxial region 212. Each of the p-type epitaxial regions 210 and 212 may be a dot-shaped structure, such as Figure 4C shown in top view.
[0143] exist Figure 4D, the semiconductor device 200 includes a first group of p-type epitaxial regions 210 arranged in a first column (see the rectangular ring dashed line), and a second group of p-type epitaxial regions 212 arranged in a second column (see the rectangular ring dashed line), wherein the second column surrounds the first column. In the first column, each side in the rectangular ring includes a plurality of p-type epitaxial regions 210. Similarly, in the second column, each side in the rectangular ring includes a plurality of p-type epitaxial regions 212. In some embodiments, the number of p-type epitaxial regions 210 on each side in the rectangular ring of the first column is the same as the number of p-type epitaxial regions 212 on each side in the rectangular ring of the second column. In some embodiments, the total number of p-type epitaxial regions 210 in the first column is the same as the total number of p-type epitaxial regions 212 in the second row. Each of the p-type epitaxial regions 210 and 212 may be a dot-like structure, such as Figure 4D shown in top view.
[0144] exist Figure 4E , the semiconductor device 200 includes a first group of p-type epitaxial regions 210 arranged in a first column (see the rectangular ring dashed line), and a second group of p-type epitaxial regions 212 arranged in a second column (see the rectangular ring dashed line), wherein the second column surrounds the first column. In the first column, each side in the rectangular ring includes a plurality of p-type epitaxial regions 210. Similarly, in the second column, each side in the rectangular ring includes a plurality of p-type epitaxial regions 212. In some embodiments, the number of p-type epitaxial regions 210 on each side of the rectangular ring of the first column (e.g., 2 in this case) is less than the number of p-type epitaxial regions 212 on each side of the rectangular ring of the second column (e.g., 4 in this case). In some embodiments, the total number of p-type epitaxial regions 210 in the first column (e.g., 8 in this case) is less than the total number of p-type epitaxial regions 212 in the second column (e.g., 12 in this case). Each of the p-type epitaxial regions 210 and 212 may be a dot-like structure, such as Figure 4E shown in top view.
[0145] exist Figure 4F, the semiconductor device 200 includes a first group of p-type epitaxial regions 210 arranged in a first row (see the rectangular ring dashed line), a second group of p-type epitaxial regions 212 arranged in a second row (see the rectangular ring dashed line), and a third group of p-type epitaxial regions 214 arranged in a third row (see the rectangular ring dashed line), wherein the third row surrounds the second row, and the second row surrounds the first row. The structure of the p-type epitaxial region 214 can be similar to the p-type epitaxial regions 210 and 212, so the relevant details will not be repeated. In the first row, each side of the rectangular ring includes a plurality of p-type epitaxial regions 210. In the second row, each side of the rectangular ring includes a plurality of p-type epitaxial regions 212. In the third row, each side of the rectangular ring includes a plurality of p-type epitaxial regions 214. In some embodiments, the number of p-type epitaxial regions 210 on each side of the rectangular rings of the first column (e.g., 2 in this case) is smaller than the number of p-type epitaxial regions 212 on each side of the rectangular rings of the second column (e.g., 4 in this case), and the number of p-type epitaxial regions 212 on each side of the rectangular rings of the second column (e.g., 4 in this case) is smaller than the number of p-type epitaxial regions 214 on each side of the rectangular rings of the third column (e.g., 5 in this case). In some embodiments, the total number of p-type epitaxial regions 210 in the first column (e.g., 8 in this case) is smaller than the total number of p-type epitaxial regions 212 in the second column (e.g., 12 in this case), and the total number of p-type epitaxial regions 212 in the second column (e.g., 12 in this case) is smaller than the total number of p-type epitaxial regions 214 in the third column (e.g., 16 in this case). Each of the p-type epitaxial regions 210, 212, and 214 may be a dot-shaped structure, such as Figure 4F shown in top view.
[0146] Figures 5 to 10 The semiconductor device according to some embodiments of the present disclosure is shown in different manufacturing stages. Figures 5 to 10 Diagram used to form Figure 2B Therefore, similar elements are labeled the same and the relevant details will not be repeated for the sake of simplicity.
[0147] refer to Figure 5 The figure shows a substrate 202. The substrate 202 includes a p-type substrate region 204 and a p-type epitaxial layer 211 formed on the p-type substrate region 204. In some embodiments, the p-type substrate region 204 and the p-type epitaxial layer 211 may be doped using a suitable implantation process.
[0148] Isolation structures 300A, 300B, 300C, 300D, 300E, and 300F are formed in substrate 202. Isolation structures 300A, 300B, 300C, 300D, 300E, and 300F may be formed by, for example, etching substrate 202 to form trenches in substrate 202, filling the trenches in substrate 202 with dielectric material, and then performing a planarization process such as CMP to remove excess dielectric material outside the trenches. As a result, the top surfaces of isolation structures 300A, 300B, 300C, 300D, 300E, and 300F may be substantially flush with the top surface of substrate 202.
[0149] refer to Figure 6 . A patterned mask MA1 is formed over the substrate 202. In some embodiments, the patterned mask MA1 may be a photoresist. The patterned mask MA1 has an opening that exposes a portion of the substrate 202. Next, an implantation process is performed through the opening of the patterned mask MA1 to form n-well regions 220, 222, and 224 in the substrate 202. As a result, the portion of the p-type epitaxial layer 211 between the n-well regions 220 and 222 is referred to as the p-type epitaxial region 210. The portion of the p-type epitaxial layer 211 between the n-well regions 222 and 224 is referred to as the p-type epitaxial region 212. In some embodiments, the implantation process may include using a dose of 1×10 12 cm -3 About 1×10 13 cm -3 Phosphorus (P) is within a range, and the implantation energy is within a range of about 50 keV to about 3000 keV.
[0150] refer to Figure 7 After forming the n-well regions 220, 222, and 224, the patterned mask MA1 is removed (see Figure 6 ). Then, a patterned mask MA2 is formed over the substrate 202. In some embodiments, the patterned mask MA2 may be a photoresist. The patterned mask MA2 has an opening that exposes a portion of the substrate 202. Then, an implantation process is performed through the opening of the patterned mask MA2 to form a p-well region 226 in the substrate 202. In some embodiments, the implantation process may include using a dose of 1×10 12 cm -3 About 1×10 13 cm -3 The implant energy is in the range of about 50 keV to about 3000 keV.
[0151] refer to Figure 8 After forming the p-well region 226, the patterned mask MA2 is removed (see Figure 7). Then, a patterned mask MA3 is formed over the substrate 202. In some embodiments, the patterned mask MA3 may be a photoresist. The patterned mask MA3 has an opening that exposes a portion of the substrate 202. Then, an implantation process is performed through the opening of the patterned mask MA3 to form a p-type doped region 230 and a deep p-well region 232 in the substrate 202. In more detail, a first implantation process is performed to form the p-type doped region 230, and a second implantation process is performed to form the deep p-well region 232. The first implantation process may be formed before or after the second implantation process. The first implantation process is performed at a lower energy, and the second implantation process is performed at a higher energy, so that the p-type doped region 230 is formed in a higher level in the substrate 202, and the deep p-well region 232 is formed in a lower level in the substrate 202. For example, the p-type doped region 230 is formed in the top portion of the n-well region 224, and the deep p-well region 232 is formed in the p-type substrate region 204. In some embodiments, the first implantation process may include using a dose of 1×10 13 cm -3 About 1×10 14 cm -3 The second implantation process may include using a dose of 1×10 12 cm -3 About 1×10 13 cm -3 The implant energy is in the range of about 200 keV to about 500 keV.
[0152] refer to Fig. 9 A dielectric layer 270 and a conductive plate 272 are formed over the substrate 202. In some embodiments, the dielectric layer 270 and the conductive plate 272 may be formed by, for example, depositing a blanket layer of dielectric material and polysilicon layer over the substrate 202, and patterning the dielectric material and polysilicon layer according to a predetermined pattern.
[0153] refer to Fig.10 An n-type heavily doped region 240, a p-type heavily doped region 242, an n-type heavily doped region 244, and a p-type heavily doped region 246 are formed in the substrate 202. In some embodiments, the n-type heavily doped regions 240 and 244 may be formed together in a first implantation process, and the p-type heavily doped regions 242 and 246 may be formed together in a second implantation process.
[0154] Afterwards, a silicide layer 250 is formed over the portions of the substrate 202 exposed by the isolation structures 300A, 300B, 300C, 300D, 300E, and 300F. In more detail, the silicide layer 250 is formed over the n-type heavily doped regions 240 and 244 and the p-type heavily doped regions 242 and 246 in the substrate 202.
[0155] Drain electrode 260, contact 274, gate electrode 262, source electrode 264, and pickup electrode 266 are then formed over substrate 202. Drain electrode 260, contact 274, gate electrode 262, source electrode 264, and pickup electrode 266 may be formed, for example, by depositing a blanket metal layer over substrate 202 and then patterning the metal layer.
[0156] Fig.11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Fig.11 Similar to Figure 2A , Fig.11 and Figure 2A The difference is Fig.11 Omitted Figure 2A The deep p-well region 232 can be skipped. Figure 8 The implantation process described in the for forming the deep p well region 232 is used, and the resulting structure is as shown in FIG. Fig.11 as shown in .
[0157] Based on the above embodiments, it can be seen that the present disclosure provides advantages in the manufacture of integrated circuits. However, it should be understood that other embodiments may provide additional advantages, not all advantages must be disclosed herein, and no specific advantages need to be used in all embodiments. The embodiments of the present disclosure provide a quasi-super junction structure in the drift region of the JFET device. The quasi-super junction structure is conducive to maintaining a high breakdown voltage, thereby increasing the breakdown voltage of the device. The embodiments of the present disclosure also provide a conductive plate overlapping the p-type doped region near the gate terminal of the device, which helps to reduce the high electric field at the junction edge between the p-type doped region and the n-well region, and will further increase the breakdown voltage of the device.
[0158] In some embodiments of the present disclosure, an integrated circuit includes a substrate. The substrate includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first and second n-type regions, wherein in a top view, the first p-type epitaxial region has a ring-shaped top profile; and a p-type doped region within the second n-type region. An isolation structure is above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region extends from a top surface of the p-type substrate region to a bottom surface of the isolation structure. A drain electrode is electrically coupled to the first n-type region. A gate electrode is electrically coupled to the p-type doped region. A source electrode is electrically coupled to the second n-type region.
[0159] In some embodiments, the integrated circuit further includes a second p-type epitaxial region above the p-type substrate region and between the first and second n-type regions, the second p-type epitaxial region being laterally spaced apart from the first p-type epitaxial region.
[0160] In some embodiments, in a cross-sectional view, the first and second p-type epitaxial regions have substantially the same width.
[0161] In some embodiments, the integrated circuit further includes a third n-type region above the p-type substrate region and laterally between the first and second p-type epitaxial regions.
[0162] In some embodiments, in a top view, the second p-type epitaxial region also includes a ring-shaped top profile, and wherein the second p-type epitaxial region surrounds the first p-type epitaxial region.
[0163] In some embodiments, the integrated circuit further includes a polysilicon plate over the isolation structure, wherein the polysilicon plate is laterally located between the drain electrode and the gate electrode.
[0164] In some embodiments, in a cross-sectional view, the polysilicon plate overlaps a portion of the p-type doped region.
[0165] In some embodiments, the integrated circuit further includes a dielectric layer between the polysilicon plate and the isolation structure.
[0166] In some embodiments of the present disclosure, an integrated circuit includes an input terminal and an output terminal. The transformer includes a main winding and a secondary winding, the main winding is electrically coupled to the input terminal, and the secondary winding is electrically coupled to the output terminal. The synchronous rectifier is electrically coupled between the secondary winding of the transformer and the output terminal. The synchronous rectifier controller is electrically coupled to the synchronous rectifier. The synchronous rectifier controller includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first and second n-type regions; a p-type doped region within the second n-type region; an isolation structure above the p-type substrate region; a drain electrode electrically coupled to the first n-type region; a gate electrode electrically coupled to the p-type doped region; a source electrode electrically coupled to the second n-type region; and a polysilicon plate above the isolation structure, wherein the polysilicon plate is laterally located between the drain electrode and the gate electrode.
[0167] In some embodiments, the polysilicon plate is spaced apart from the gate electrode.
[0168] In some embodiments, the polysilicon plate is grounded.
[0169] In some embodiments, the polysilicon plate overlaps a boundary between the p-type doped region and the second n-type region.
[0170] In some embodiments, the integrated circuit further includes a dielectric layer between the polysilicon plate and the isolation structure.
[0171] In some embodiments, the integrated circuit further includes first and second p-type epitaxial regions above the first p-type substrate region, between the first and second n-type regions, and below the isolation structure, the first p-type epitaxial region being spaced apart from the second p-type epitaxial region.
[0172] In some embodiments, the first and second p-type epitaxial regions extend from the p-type substrate region to the isolation structure.
[0173] In some embodiments of the present disclosure, a method includes forming a substrate having a p-type substrate region and a p-type epitaxial layer above the p-type substrate region; forming an isolation structure in the substrate; performing a first implantation process to form first, second, and third n-type regions in the p-type epitaxial layer, the third n-type region being between the first and second n-type regions, wherein the p-type epitaxial layer has a first remaining portion between the first and third n-type regions, and a second remaining portion between the second and third n-type regions; performing a second implantation process to form a p-type doped region in the third n-type region; and forming a drain electrode, a gate electrode, and a source electrode above the substrate, wherein the drain electrode is electrically coupled to the first n-type region, the gate electrode is electrically coupled to the p-type doped region, and the source electrode is electrically coupled to the second n-type region.
[0174] In some embodiments, the first and second p-type epitaxial regions extend from the p-type substrate region to the isolation structure.
[0175] In some embodiments, the first and second p-type epitaxial regions have ring-shaped top profiles.
[0176] In some embodiments, the method further includes forming a dielectric layer over the isolation structure; and forming a polysilicon plate over the dielectric layer, wherein the polysilicon plate is spaced apart from the gate electrode.
[0177] In some embodiments, the second implantation process is performed such that the p-type doping region has a portion extending to a position below the isolation structure, and wherein the polysilicon plate overlaps a portion of the p-type doping region.
[0178] In some embodiments of the present disclosure, an integrated circuit includes a substrate. The substrate includes a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first and second n-type regions, wherein in a top view, the first p-type epitaxial region has a ring-shaped top profile; and a p-type doped region within the second n-type region. An isolation structure is above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region is vertically below the isolation structure, and the first p-type epitaxial region extends from a top surface of the p-type substrate region to a bottom surface of the isolation structure. A drain electrode is electrically coupled to the first n-type region. A gate electrode is electrically coupled to the p-type doped region. A source electrode is electrically coupled to the second n-type region.
[0179] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.
Claims
1. An integrated circuit, characterized in that: Include: A substrate comprising: a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region; a p-type doped region within the second n-type region; an isolation structure above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region is vertically below the isolation structure; a drain electrode electrically coupled to the first n-type region; a gate electrode electrically coupled to the p-type doped region; and A source electrode is electrically coupled to the second n-type region.
2. The integrated circuit according to claim 1, wherein: Further included is a second p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region, the second p-type epitaxial region being laterally spaced apart from the first p-type epitaxial region.
3. The integrated circuit according to claim 2, characterized in that In the cross-sectional view, the first p-type epitaxial region and the second p-type epitaxial region have substantially the same width.
4. The integrated circuit according to claim 2, wherein: The invention further includes a third n-type region above the p-type substrate region and laterally located between the first p-type epitaxial region and the second p-type epitaxial region.
5. The integrated circuit according to claim 2, wherein: In a top view, the first p-type epitaxial region and the second p-type epitaxial region include a ring-shaped top profile, and the second p-type epitaxial region surrounds the first p-type epitaxial region.
6. The integrated circuit according to claim 1, wherein: The invention further comprises a polysilicon plate above the isolation structure, wherein the polysilicon plate is laterally located between the drain electrode and the gate electrode.
7. An integrated circuit, characterized in that: Include: an input terminal and an output terminal; A transformer comprising a main winding and a secondary winding, the main winding being electrically coupled to the input terminal, the secondary winding being electrically coupled to the output terminal; a synchronous rectifier electrically coupled between the secondary winding of the transformer and the output terminal; and A synchronous rectifier controller, electrically coupled to the synchronous rectifier, comprising: a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region; a p-type doped region within the second n-type region; an isolation structure above the p-type substrate region; a drain electrode electrically coupled to the first n-type region; a gate electrode electrically coupled to the p-type doped region; a source electrode electrically coupled to the second n-type region; and A conductive plate is above the isolation structure, wherein the conductive plate is laterally located between the drain electrode and the gate electrode.
8. The integrated circuit according to claim 7, characterized in that The conductive plate overlaps a boundary between the p-type doped region and the second n-type region.
9. The integrated circuit according to claim 7, characterized in that Further including: The first p-type epitaxial region and a second p-type epitaxial region are located above the p-type substrate region, between the first n-type region and the second n-type region, and below the isolation structure. The first p-type epitaxial region is spaced apart from the second p-type epitaxial region.
10. An integrated circuit, characterized in that: Include: A substrate comprising: a p-type substrate region; a first n-type region above the p-type substrate region; a second n-type region above the p-type substrate region; a first p-type epitaxial region above the p-type substrate region and between the first n-type region and the second n-type region, wherein the first p-type epitaxial region has a ring-shaped top profile in a top view; a p-type doped region within the second n-type region; an isolation structure above the p-type substrate region, wherein in a cross-sectional view, the first p-type epitaxial region is vertically below the isolation structure and extends from an upper surface of the p-type substrate region to a lower surface of the isolation structure; a drain electrode electrically coupled to the first n-type region; a gate electrode electrically coupled to the p-type doped region; and A source electrode is electrically coupled to the second n-type region.