5G small station front card transmission device

Abstract

The utility model relates to the technical field of communication, and discloses a 5G small station front card transmission device which is connected with a base server through PCIE (Peripheral Component Interface Express). Comprising an integrated circuit which is responsible for high-PHY acceleration processing, an editable logic circuit which is responsible for data format conversion, a time service positioning circuit which is responsible for receiving GPS and Beidou signals, a golden finger and four optical ports which are arranged at the front section and are responsible for being connected with an active antenna unit. The clock circuit is electrically connected with the editable logic circuit and is used for realizing time synchronization with the EU through four optical ports of forward transmission; the integrated circuit interacts with an MAC (Media Access Control) on a base server through PCIE (Peripheral Component Interface Express) x4, and the integrated circuit, the time service positioning circuit and the four optical ports are electrically connected with the editable logic circuit. According to the utility model, a plug-and-play universal forward-transmission board card is adopted, a standard option7-2 networking mode is realized, a protocol stack can use a universal server, and the protocol stack is convenient to use. And the board card also realizes a clock scheme, so that the cost is saved, and the system complexity is reduced.

Description

Technical Field

[0001] The utility model relates to the field of communication technology, in particular to the field of 5G High-PHY processing and distribution of fronthaul data, and specifically is a 5G small station fronthaul card device. Background Art

[0002] Open NR small base stations mostly adopt a distributed layout, and the DU (distributed unit) and AAU (active antenna unit) communicate through the fronthaul network.

[0003] In the 5G communication system, the physical layer (PHY layer) plays a vital role. According to the different processing contents and stages, the PHY layer can be further divided into High-PHY and Low-PHY. The main functions of High-PHY are encoding and decoding, rate matching, scrambling, modulation decoding, and layer mapping.

[0004] The fronthaul interface is defined as the communication interface between the RRU and the HUB, and the communication interface between the BBU and the HUB. In the 5G system, the distribution of fronthaul data is a complex process involving multiple components and interfaces. Through reasonable PHY layer division and fronthaul interface design, efficient data transmission and coverage expansion can be achieved.

[0005] In the prior art, the following defects still exist in 5G communication:

[0006] After High-PHY processing, the data needs to be transmitted back to the base server, and then distributed through the CPU, which wastes the CPU;

[0007] For general servers, a separate clock card needs to be inserted, which is costly;

[0008] The board supports small specifications and high costs.

[0009] Therefore, we need to propose a 5G small cell fronthaul card device that is cost-effective, supports four 100MHz 2TR NR cells High-PHY, and has a clock. Utility Model Content

[0010] The purpose of the utility model is to provide a 5G small station fronthaul card device, which adopts a plug-and-play universal fronthaul board card and realizes the standard option7-2 networking mode, so that the protocol stack can use a universal server. The board card also implements a clock scheme, which saves costs and reduces system complexity to solve the problems raised in the above background technology.

[0011] To achieve the above purpose, the utility model provides the following technical solutions: a 5G small station front transmission card device, connected to the base server through PCIE, including an integrated circuit responsible for the acceleration processing of High-PHY, an editable logic circuit responsible for data format conversion, a timing and positioning circuit responsible for receiving GPS and Beidou signals, a gold finger, and four optical ports in the front section responsible for connecting to the active antenna unit;

[0012] It also includes a clock circuit electrically connected to the editable logic circuit and used to achieve time synchronization with the EU through the four optical ports of the fronthaul;

[0013] The integrated circuit interacts with the MAC on the base server through PCIE x4, the integrated circuit, the timing and positioning circuit, and the four optical ports are all electrically connected to the editable logic circuit, and the integrated circuit and the editable logic circuit are all electrically connected to the gold finger.

[0014] Preferably, the integrated circuit includes an integrated chip U67A, the W20 pin of the integrated chip U67A is connected to a resistor R906, the V20 pin of the integrated chip U67A is connected to a resistor R905, the V19 pin of the integrated chip U67A is connected to a resistor R904, the AE3 pin of the integrated chip U67A is connected to a resistor R903, the AD4 pin of the integrated chip U67A is connected to a resistor R902, the AE4 pin of the integrated chip U67A is connected to a resistor R901, the R21 pin of the integrated chip U67A is connected to a resistor R899, and one end of the resistor R899, the resistor R901, the resistor R902, the resistor R903, the resistor R904, the resistor R905, and the resistor R906 are all connected to a 1.8V voltage.

[0015] Preferably, the clock circuit includes a clock driving chip U73, and pins 1 to 12 of the clock driving chip U73 are connected to resistors with a resistance of 0, pin 20 of the clock driving chip U73 is connected to capacitor C1411, pin 21 of the clock driving chip U73 is connected to capacitor C1412, resistor R1213 is connected between capacitor C1411 and capacitor C1412, pin 40 of the clock driving chip U73 is connected to capacitor C1413, pin 41 of the clock driving chip U73 is connected to capacitor C1414, and resistor R1228 is connected between capacitor C1413 and capacitor C1414.

[0016] Preferably, the clock circuit also includes a reset chip U35, a capacitor C394 is connected between pin 1 and pin 9 of the reset chip U35, a resistor R313 is connected between pin 1 and pin 8 of the reset chip U35, a resistor R315 is connected between pin 1 and pin 7 of the reset chip U35, and a resistor R314, a switch S1, and a capacitor C395 are connected between pin 3 and pin 2 of the reset chip U35.

[0017] Preferably, the timing and positioning circuit includes a timing and positioning chip U38, wherein resistors R338 and R339 are connected between pin 1 and pin 2 of the timing and positioning chip U38, resistor R340 is connected to pin 3 of the timing and positioning chip U38, resistor R336 is connected to pin 4 of the timing and positioning chip U38, and resistor R335 is connected between pin 5 and pin 6 of the timing and positioning chip U38;

[0018] A resistor R333 and a capacitor C467 arranged in parallel are connected to pin 10 of the timing and positioning chip U38, a resistor R332 and a magnetic bead FB83 are connected between pins 11 and 12 of the timing and positioning chip U38, and capacitors C465 and C466 arranged in parallel are connected to the connection terminals of the resistor R332 and the magnetic bead FB83.

[0019] Preferably, the editable logic circuit includes an editable logic chip BANK65, and a capacitor C234 and a resistor R145 are connected between the connection terminals of the P22 pin, U23 pin, and V18 pin of the editable logic chip BANK65 and the V18 pin, and a resistor with a resistance of 0 is connected to the U26 pin, P24 pin, N24 pin, U25 pin, AA25 pin, AA24 pin, Y26 pin, Y25 pin, and Y23 pin of the editable logic chip BANK65.

[0020] Preferably, it also includes a terminal block J9 for connecting a gold finger, wherein the A2 pin of the terminal block J9 is connected to a resistor R490, the A3 pin of the terminal block J9 is connected to a resistor R489, the A6 pin of the terminal block J9 is connected to a resistor R488, the A8 pin of the terminal block J9 is connected to a resistor R487, and one end of the resistor R487, the resistor R488, the resistor R489, and the resistor R490 are all connected to a 3.3V power supply voltage;

[0021] The A9 pin of the terminal block J9 is respectively connected to a resistor R465 connected to a 3.3V power supply voltage and a resistor R466 connected to ground. The A5 pin of the terminal block J9 is respectively connected to a resistor R578, a resistor R575, and a resistor R468. The A4 pin of the terminal block J9 is respectively connected to a resistor R577, a resistor R576, and a resistor R467.

[0022] Preferably, the connection terminals of the B1, B2 and B3 pins of the gold finger are connected to a 12V power supply voltage and are connected to capacitors C1093, C1090 and C1091 arranged in parallel, the B5 pin of the gold finger is connected to resistor R616, the B6 pin of the gold finger is connected to resistor R617, resistors R619 and R618 are connected between the resistors R616 and R617, and the B9 pin of the gold finger is connected to capacitor C1177 and resistor R621 arranged in parallel.

[0023] Compared with the prior art, the beneficial effects of the utility model are:

[0024] The utility model adopts a plug-and-play universal fronthaul board card, realizes a standard option 7-2 networking mode, enables a protocol stack to use a universal server, and the board card also realizes a clock solution, thus saving costs and reducing system complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a system block diagram of the utility model;

[0026] Figure 2 This is a schematic diagram of the accelerated processing of High-PHY of the utility model;

[0027] Figure 3 A circuit diagram of the integrated circuit of the utility model;

[0028] Figure 4 A circuit diagram of a clock circuit of the utility model;

[0029] Figure 5 This is a circuit diagram of the reset chip of the utility model;

[0030] Figure 6 The circuit diagram of the timing and positioning circuit of the utility model;

[0031] Figure 7 A circuit diagram of an editable logic circuit of the utility model;

[0032] Figure 8 This is the circuit diagram of the wiring socket J9 of the utility model;

[0033] Fig. 9 The utility model is a circuit diagram of the gold finger. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0035] See also Figure 1-9 ,The utility model provides a technical solution: a 5G small station front transmission card device, connected to the base server through PCIE, including an integrated circuit responsible for the acceleration processing of High-PHY, an editable logic circuit responsible for data format conversion, a timing and positioning circuit responsible for receiving GPS and Beidou signals, a gold finger, and four optical ports in the front section responsible for connecting with the active antenna unit;

[0036] Also included is a clock circuit electrically connected to the editable logic circuit and used to achieve time synchronization with the EU through the four optical ports of the fronthaul;

[0037] The integrated circuit interacts with the MAC on the base server through PCIE x4, the integrated circuit, the timing and positioning circuit, and the four optical ports are all electrically connected to the editable logic circuit, and the integrated circuit and the editable logic circuit are all electrically connected to the gold finger.

[0038] The main components of this front-end card include two NXP LA1201 chips, Xilinx's KU3PFPGA, a Taidouwei GPS module, and four optical ports on the front end. The overall block diagram is as follows Figure 1 shown.

[0039] LA1201 is responsible for the acceleration processing of highphy, mainly including precoding, debugging demodulation, channel estimation, encoding, decoding, etc. Figure 2 shown.

[0040] 3GPP defines High-PHY and Low-PHY according to option 7-2. The functions are clearly divided, where Low-PHY functions (such as precoding, FFT / IFFT) and resource element (RE) mapping / demapping functions are either implemented in the remote radio unit (RRU) or in the fronthaul gateway network node between the RU and the DU. High-PHY functions (mainly including encoding / decoding, scrambling and modulation / demodulation) are executed in the DU. In this article 1201, the acceleration processing of highphy is completed by the dsp module.

[0041] LA1201 interacts with the mac on the base through PCIEx4 and performs fapi interaction. At this time, LA1201 acts as the EP device of the base PCIE. After LA1201 processes the data, it interacts with ku3p through PCIEx4. At this time, LA1201 acts as the RC of PCIE.

[0042] FAPI is a specification in 3GPP, which defines the interface specification between PHY and MAC when they are located in the same physical entity. In this article, FAPI is transmitted through PCIE.

[0043] KU3P is mainly responsible for converting the data of LA1201 into eCPRI format and then forwarding it to EU. If the data of EU needs to be merged in baseband before transmission, it is also completed by KU3P. The communication method between KU3P and LA1201 is PCIEx4. KU3P acts as the EP end of PCIE. Another function of KU3P is to receive 1pps and tod from Taidou micromodule, or receive 1pps and tod from OTII pin of PCIE to complete its own time synchronization; at the same time, KU3P needs to implement the function of 1588master to achieve time synchronization with EU through the front-haul optical port.

[0044] 1PPS (Pulse Per Second) is a pulse per second signal generated by a GPS receiver. TOD (Time Of Day) is the time information generated by a GPS receiver.

[0045] Taidouwei's GPS module is mainly responsible for receiving GPS and Beidou signals, completing time synchronization, and generating 1pps and tod for KU3P.

[0046] 1588 is a master-slave synchronization system. During the synchronization process of the system, the master clock periodically releases time synchronization and time information, and the slave clock port receives the timestamp information sent by the master clock port. The system calculates the master-slave line time delay and the master-slave time difference based on this information, and uses this time difference to adjust the local time, so that the device time maintains the same frequency and phase as the master device time. Here, 1588master refers to the master clock of 1588.

[0047] The integrated circuit includes an integrated chip U67A, the W20 pin of the integrated chip U67A is connected to a resistor R906, the V20 pin of the integrated chip U67A is connected to a resistor R905, the V19 pin of the integrated chip U67A is connected to a resistor R904, the AE3 pin of the integrated chip U67A is connected to a resistor R903, the AD4 pin of the integrated chip U67A is connected to a resistor R902, the AE4 pin of the integrated chip U67A is connected to a resistor R901, and the R21 pin of the integrated chip U67A is connected to a resistor R899, and one end of the resistor R899, the resistor R901, the resistor R902, the resistor R903, the resistor R904, the resistor R905, and the resistor R906 are all connected to a 1.8V voltage.

[0048] The clock circuit includes a clock driving chip U73, and pins 1 to 12 of the clock driving chip U73 are all connected to resistors with a resistance of 0, pin 20 of the clock driving chip U73 is connected to capacitor C1411, pin 21 of the clock driving chip U73 is connected to capacitor C1412, resistor R1213 is connected between capacitor C1411 and capacitor C1412, pin 40 of the clock driving chip U73 is connected to capacitor C1413, pin 41 of the clock driving chip U73 is connected to capacitor C1414, and resistor R1228 is connected between capacitor C1413 and capacitor C1414.

[0049] The clock circuit also includes a reset chip U35, a capacitor C394 is connected between pin 1 and pin 9 of the reset chip U35, a resistor R313 is connected between pin 1 and pin 8 of the reset chip U35, a resistor R315 is connected between pin 1 and pin 7 of the reset chip U35, and a resistor R314, a switch S1, and a capacitor C395 are connected between pin 3 and pin 2 of the reset chip U35.

[0050] The timing and positioning circuit includes a timing and positioning chip U38, wherein resistors R338 and R339 are connected between pin 1 and pin 2 of the timing and positioning chip U38, resistor R340 is connected to pin 3 of the timing and positioning chip U38, resistor R336 is connected to pin 4 of the timing and positioning chip U38, and resistor R335 is connected between pin 5 and pin 6 of the timing and positioning chip U38;

[0051] A resistor R333 and a capacitor C467 arranged in parallel are connected to pin 10 of the timing and positioning chip U38, a resistor R332 and a magnetic bead FB83 are connected between pins 11 and 12 of the timing and positioning chip U38, and capacitors C465 and C466 arranged in parallel are connected to the connection terminals of the resistor R332 and the magnetic bead FB83.

[0052] The editable logic circuit includes an editable logic chip BANK65, and a capacitor C234 and a resistor R145 are connected between the connection terminals of the P22 pin, U23 pin, and V18 pin of the editable logic chip BANK65 and the V18 pin, and a resistor with a resistance of 0 is connected to the U26 pin, P24 pin, N24 pin, U25 pin, AA25 pin, AA24 pin, Y26 pin, Y25 pin, and Y23 pin of the editable logic chip BANK65.

[0053] It also includes a terminal block J9 for connecting a gold finger, wherein the A2 pin of the terminal block J9 is connected to a resistor R490, the A3 pin of the terminal block J9 is connected to a resistor R489, the A6 pin of the terminal block J9 is connected to a resistor R488, and the A8 pin of the terminal block J9 is connected to a resistor R487, and one end of the resistor R487, the resistor R488, the resistor R489, and the resistor R490 are all connected to a 3.3V power supply voltage;

[0054] The A9 pin of the terminal block J9 is respectively connected to a resistor R465 connected to a 3.3V power supply voltage and a resistor R466 connected to ground. The A5 pin of the terminal block J9 is respectively connected to a resistor R578, a resistor R575, and a resistor R468. The A4 pin of the terminal block J9 is respectively connected to a resistor R577, a resistor R576, and a resistor R467.

[0055] The connection terminals of the B1, B2 and B3 pins of the gold finger are connected to a 12V power supply voltage and are connected to capacitors C1093, C1090 and C1091 arranged in parallel, the B5 pin of the gold finger is connected to a resistor R616, the B6 pin of the gold finger is connected to a resistor R617, resistors R619 and R618 are connected between the resistors R616 and R617, and the B9 pin of the gold finger is connected to a capacitor C1177 and a resistor R621 arranged in parallel.

[0056] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A 5G small station front transmission card device, connected to a base server via PCIE, characterized in that: include: The integrated circuit responsible for the acceleration processing of High-PHY, the editable logic circuit responsible for data format conversion, the timing and positioning circuit responsible for receiving GPS and Beidou signals, the gold finger, and the four optical ports in the front section responsible for connecting to the active antenna unit; It also includes a clock circuit electrically connected to the editable logic circuit and used to achieve time synchronization with the EU through the four optical ports of the fronthaul; The integrated circuit interacts with the MAC on the base server through PCIE x4, the integrated circuit, the timing and positioning circuit, and the four optical ports are all electrically connected to the editable logic circuit, and the integrated circuit and the editable logic circuit are all electrically connected to the gold finger.

2. A 5G small station front transmission card device according to claim 1, characterized in that: The integrated circuit includes an integrated chip U67A, the W20 pin of the integrated chip U67A is connected to a resistor R906, the V20 pin of the integrated chip U67A is connected to a resistor R905, the V19 pin of the integrated chip U67A is connected to a resistor R904, the AE3 pin of the integrated chip U67A is connected to a resistor R903, the AD4 pin of the integrated chip U67A is connected to a resistor R902, the AE4 pin of the integrated chip U67A is connected to a resistor R901, and the R21 pin of the integrated chip U67A is connected to a resistor R899, and one end of the resistor R899, the resistor R901, the resistor R902, the resistor R903, the resistor R904, the resistor R905, and the resistor R906 are all connected to a 1.8V voltage.

3. A 5G small station front transmission card device according to claim 1, characterized in that: The clock circuit includes a clock driving chip U73, and pins 1 to 12 of the clock driving chip U73 are all connected to resistors with a resistance of 0, pin 20 of the clock driving chip U73 is connected to capacitor C1411, pin 21 of the clock driving chip U73 is connected to capacitor C1412, resistor R1213 is connected between capacitor C1411 and capacitor C1412, pin 40 of the clock driving chip U73 is connected to capacitor C1413, pin 41 of the clock driving chip U73 is connected to capacitor C1414, and resistor R1228 is connected between capacitor C1413 and capacitor C1414.

4. A 5G small station front transmission card device according to claim 3, characterized in that: The clock circuit also includes a reset chip U35, a capacitor C394 is connected between pin 1 and pin 9 of the reset chip U35, a resistor R313 is connected between pin 1 and pin 8 of the reset chip U35, a resistor R315 is connected between pin 1 and pin 7 of the reset chip U35, and a resistor R314, a switch S1, and a capacitor C395 are connected between pin 3 and pin 2 of the reset chip U35.

5. A 5G small station front transmission card device according to claim 1, characterized in that: The timing and positioning circuit includes a timing and positioning chip U38, wherein resistors R338 and R339 are connected between pin 1 and pin 2 of the timing and positioning chip U38, resistor R340 is connected to pin 3 of the timing and positioning chip U38, resistor R336 is connected to pin 4 of the timing and positioning chip U38, and resistor R335 is connected between pin 5 and pin 6 of the timing and positioning chip U38; A resistor R333 and a capacitor C467 arranged in parallel are connected to pin 10 of the timing and positioning chip U38, a resistor R332 and a magnetic bead FB83 are connected between pins 11 and 12 of the timing and positioning chip U38, and capacitors C465 and C466 arranged in parallel are connected to the connection terminals of the resistor R332 and the magnetic bead FB83.

6. A 5G small station front transmission card device according to claim 1, characterized in that: The editable logic circuit includes an editable logic chip BANK65, and a capacitor C234 and a resistor R145 are connected between the connection terminals of the P22 pin, U23 pin, and V18 pin of the editable logic chip BANK65 and the V18 pin, and a resistor with a resistance of 0 is connected to the U26 pin, P24 pin, N24 pin, U25 pin, AA25 pin, AA24 pin, Y26 pin, Y25 pin, and Y23 pin of the editable logic chip BANK65.

7. A 5G small station front transmission card device according to claim 1, characterized in that: It also includes a terminal block J9 for connecting a gold finger, wherein the A2 pin of the terminal block J9 is connected to a resistor R490, the A3 pin of the terminal block J9 is connected to a resistor R489, the A6 pin of the terminal block J9 is connected to a resistor R488, and the A8 pin of the terminal block J9 is connected to a resistor R487, and one end of the resistor R487, the resistor R488, the resistor R489, and the resistor R490 are all connected to a 3.3V power supply voltage; The A9 pin of the terminal block J9 is respectively connected to a resistor R465 connected to a 3.3V power supply voltage and a resistor R466 connected to ground. The A5 pin of the terminal block J9 is respectively connected to a resistor R578, a resistor R575, and a resistor R468. The A4 pin of the terminal block J9 is respectively connected to a resistor R577, a resistor R576, and a resistor R467.

8. A 5G small station front transmission card device according to claim 1, characterized in that: The connection terminals of the B1, B2 and B3 pins of the gold finger are connected to a 12V power supply voltage and are connected to capacitors C1093, C1090 and C1091 arranged in parallel, the B5 pin of the gold finger is connected to a resistor R616, the B6 pin of the gold finger is connected to a resistor R617, resistors R619 and R618 are connected between the resistors R616 and R617, and the B9 pin of the gold finger is connected to a capacitor C1177 and a resistor R621 arranged in parallel.

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