Semiconductor package

Abstract

The utility model provides a semiconductor packaging body. The semiconductor package includes an interposer module, a thermal interface material (TIM) layer, a TIM layer protection structure, and a package cover. The intermediary module is located on the package substrate. The TIM layer is located on the intermediary module. The TIM layer protection structure is located on the side surface of the TIM layer and the side surface of the intermediary module. The packaging cover is located on the intermediary module, the TIM layer and the TIM layer protection structure.

Description

Technical Field

[0001] The utility model relates to semiconductor technology, and in particular to a semiconductor package. Background Art

[0002] A semiconductor package may include one or more semiconductor dies that may be stacked or mounted on an interposer. During operation, the semiconductor dies may generate a large amount of heat energy. To improve performance, the generated heat energy may be dissipated.

[0003] A semiconductor package may include a thermal interface material (TIM) layer to help dissipate heat. In particular, the TIM layer may help transfer heat energy from an interposer (e.g., from a semiconductor wafer on the interposer) to a package lid of the semiconductor package. The TIM layer may be particularly beneficial in large semiconductor packages and advanced semiconductor packages. Utility Model Content

[0004] In some embodiments, a semiconductor package is provided. The semiconductor package includes an intermediate module, a thermal interface material (TIM) layer, a thermal interface material layer protection structure, and a package lid. The intermediate module is located on a package substrate. The thermal interface material layer is located on the intermediate module. The thermal interface material layer protection structure is located on a side of the thermal interface material layer and a side of the intermediate module. The package lid is located on the intermediate module, the thermal interface material layer, and the thermal interface material layer protection structure.

[0005] In some embodiments, a ratio of a thickness of the thermal interface material layer protection structure to a thickness of the intermediate module is between 1.0 and 3.0.

[0006] In some embodiments, the packaging cover has a packaging cover length in a first horizontal direction, the thermal interface material layer protection structure has a thermal interface material layer protection structure length in the first horizontal direction, and the ratio of the thermal interface material layer protection structure length to the packaging cover length is between 0.3 and 1.0.

[0007] In some embodiments, the packaging cover has a packaging cover width in a second horizontal direction perpendicular to the first horizontal direction, the thermal interface material layer protection structure has a thermal interface material layer protection structure width in the second horizontal direction, and the ratio of the thermal interface material layer protection structure width to the packaging cover width is between 0.3 and 1.0.

[0008] In some embodiments, the package body further includes: a reinforcement ring adhered to the package substrate and located around the intermediate module, wherein the thermal interface material layer protection structure is formed in a space defined by the reinforcement ring and the intermediate module.

[0009] In some embodiments, the thermal interface material layer protection structure is bonded to the reinforcement ring and continuously extends from the reinforcement ring to the intermediate module.

[0010] In some embodiments, the thermal interface material layer protection structure is bonded to the packaging cover and the packaging substrate, and continuously extends from the packaging cover to the packaging substrate.

[0011] In some embodiments, the packaging cover includes a filling plug and a degassing plug, the filling plug is above the thermal interface material layer protection structure, and the degassing plug is above the thermal interface material layer protection structure.

[0012] In some embodiments, the package cover includes a plate portion and a foot portion, the foot portion extends from the plate portion and contacts the package substrate around the periphery of the intermediate module, and the thermal interface material layer protection structure is formed in the space between the foot portion and the intermediate module. In some embodiments, a semiconductor package is provided. The semiconductor package includes an intermediate module, a thermal interface material layer, a thermal interface material layer protection structure, a reinforcement ring and a package cover. The intermediate module is located on the package substrate. The thermal interface material layer is located on the intermediate module. The thermal interface material layer protection structure is located on the package substrate and surrounds the intermediate layer and the thermal interface material layer, wherein the thermal expansion coefficient of the thermal interface material layer protection structure is between 3ppm / ℃ and 20ppm / ℃, and the thermal conductivity of the thermal interface material layer protection structure is greater than 1W / m·K. The reinforcement ring is attached to the package substrate and is located around the intermediate module, wherein the thermal interface material layer protection structure is formed in the space defined by the reinforcement ring and the intermediate module. The packaging cover is located on the reinforcement ring, the intermediate module, the thermal interface material layer and the thermal interface material layer protection structure, wherein the packaging cover contacts the upper surface of the thermal interface material layer and the upper surface of the thermal interface material layer protection structure. The packaging cover includes a filling hole, a filling plug, a degassing hole and a degassing plug. The filling hole is located above the thermal interface material layer protection structure, and the diameter of the filling hole is between 3mm and 10mm. The filling plug is used to plug the filling hole. The degassing hole is located above the thermal interface material layer protection structure, and the diameter of the degassing hole is between 3mm and 10mm. The degassing plug is used to plug the degassing hole. Among them, the filling hole is located on the side of the intermediate module opposite to the degassing hole.

[0013] At least one embodiment of the present invention has the following advantages or technical effects: a TIM layer formed on an intermediate module can dissipate heat energy generated during operation of a semiconductor package; a TIM layer protection structure can help protect the TIM layer, and in particular can help inhibit (e.g., prevent) the TIM layer from being delaminated from the intermediate module; or the TIM layer protection structure can provide enhanced reliability and better heat dissipation performance for the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0015] Figure 1A FIG. 1 is a vertical cross-sectional view of a semiconductor package according to one or more embodiments.

[0016] Figure 1B FIG. 1 is an enlarged vertical cross-sectional view illustrating a filling hole in a package cover according to one or more embodiments.

[0017] Figure 1C FIG. 1 is an enlarged vertical cross-sectional view showing a degassing hole in a package cover according to one or more embodiments.

[0018] Figure 1D According to one or more embodiments, Figure 1A A plan view of the package lid is shown.

[0019] Figure 2A A vertical cross-sectional view of an intermediate structure including an upper bonding pad of a package substrate and a lower bonding pad of a package substrate is shown according to one or more embodiments.

[0020] Figure 2B A vertical cross-sectional view of an intermediate structure including an upper surface layer of a package substrate and a lower surface layer of a package substrate is shown according to one or more embodiments.

[0021] Figure 2C A vertical cross-sectional view of an intermediate structure including an opening in an upper surface layer of a package substrate and an opening in a lower surface layer of the package substrate according to one or more embodiments.

[0022] Figure 2D A vertical cross-sectional view of an intermediate structure is shown in which an interposer module may be mounted on a package substrate (eg, via a flip chip bonding (FCB) process) according to one or more embodiments.

[0023] Figure 2E A vertical cross-sectional view of an intermediate structure is shown in which a package underfill layer may be formed on a package substrate according to one or more embodiments.

[0024] Figure 2F FIG. 5 is a vertical cross-sectional view of an intermediate structure in which a TIM layer may be attached to a top surface of an interposer module according to one or more embodiments.

[0025] Figure 2G FIG. 5 is a vertical cross-sectional view of an intermediate structure in which an adhesive may be applied to a package substrate according to one or more embodiments.

[0026] Figure 2H 2 is a vertical cross-sectional view of an intermediate structure in which a stiffener ring may be attached (eg, mounted) to a package substrate in accordance with one or more embodiments.

[0027] Fig.2I FIG. 1 is a vertical cross-sectional view of an intermediate structure in which a packaging cover may be attached to a reinforcement ring according to one or more embodiments.

[0028] Figure 2J A vertical cross-sectional view of an intermediate structure is shown in which a TIM layer protection structure may be added to a semiconductor package according to one or more embodiments.

[0029] Figure 2K FIG. 1 is a plan view showing an intermediate structure including a TIM layer protection structure on a package substrate according to one or more embodiments.

[0030] Figure 2L FIG. 1 is a vertical cross-sectional view of an intermediate structure including a filling plug and a degassing plug according to one or more embodiments.

[0031] Figure 2M FIG. 5 is a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls may be formed on a package substrate according to one or more embodiments.

[0032] Figure 3 The present invention is a flow chart showing a method of forming a semiconductor package according to one or more embodiments.

[0033] Figure 4A FIG. 1 is a plan view illustrating a first alternative design of a package cover according to one or more embodiments.

[0034] Figure 4B FIG. 1 is a plan view illustrating a second alternative design of a package cover according to one or more embodiments.

[0035] Figure 4CFIG. 1 is a plan view illustrating a third alternative design of a package cover according to one or more embodiments.

[0036] Figure 5 FIG. 4 is a vertical cross-sectional view illustrating a fourth alternative design of a package cover according to one or more embodiments.

[0037] Figure 6 FIG. 5 is a vertical cross-sectional view illustrating a fifth alternative design of a package cover according to one or more embodiments.

[0038] The accompanying drawings are described as follows:

[0039] 100:Semiconductor package

[0040] 110:Packaging substrate

[0041] 110a: upper surface layer of packaging substrate

[0042] 110b: lower surface layer of packaging substrate

[0043] 110c: Solder ball

[0044] 112: Core

[0045] 112a: Guide hole

[0046] 114: Dielectric layer on packaging substrate

[0047] 114a: Bonding pad on package substrate

[0048] 114b: Metal interconnect structure

[0049] 116: Dielectric layer under the package substrate

[0050] 116a: Bonding pad under package substrate

[0051] 116b: Metal interconnect structure

[0052] 120:Intermediary module

[0053] 121: Controlled collapse of wafer connection bumps

[0054] 122: Intermediate dielectric layer

[0055] 122a: Metal interconnect

[0056] 123: first semiconductor grain

[0057] 124: second semiconductor grain

[0058] 126:Intermediary bottom filling layer

[0059] 127: Molding material layer

[0060] 128: Micro bump

[0061] 129: Package bottom fill layer

[0062] 130: Packaging cover

[0063] 130a: bottom surface

[0064] 130b: Upper surface

[0065] 130c,130d:foot

[0066] 130p: Board

[0067] 131:Filling hole

[0068] 132: Filling plug

[0069] 133: Degassing hole

[0070] 134: Degassing plug

[0071] 140: Thermal interface material layer

[0072] 150: Reinforcement ring

[0073] 160,161: Adhesive

[0074] 170: Thermal interface material layer protection structure

[0075] 170i: Thermal interface material layer protects the structural interface

[0076] 310,320,330,340: Steps

[0077] D131, D133: Diameter

[0078] L130, L131i, L131o, L133o, L170: Length

[0079] O110a, O110b: Open

[0080] T120, T130, T170: Thickness

[0081] W130,W170: Width DETAILED DESCRIPTION

[0082] The following disclosure provides many different embodiments or examples for implementing different components of the subject matter provided. Specific examples of each component and its configuration are described below to simplify the description of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first component and the second component are in direct contact, and it may also include an embodiment in which an additional component is formed between the first component and the second component so that they are not in direct contact. In addition, the present disclosure may repeat component symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and is not used to represent the relationship between the different embodiments and / or configurations discussed.

[0083] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, may be used herein to facilitate description of the relationship between one element or component and another element or component in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative descriptions used therein will also be interpreted according to the orientation after the turn. Unless otherwise required, it is assumed that each element with the same element number has the same material composition and has a thickness within the same thickness range.

[0084] Thermal variation (e.g., heating, cooling) may cause typical semiconductor package warpage (e.g., warpage caused by thermal stress). Such package warpage may cause delamination of the thermal interface material (TIM) layer from the interposer module, which may cause failure of the semiconductor package. In the case of such package warpage, the TIM layer may delaminate from the upper surface of the interposer module at the corners of the interposer module.

[0085] One or more embodiments of the present disclosure may include a TIM layer protection structure. The TIM layer protection structure may help protect the TIM layer to inhibit (e.g., prevent) the TIM layer from delaminating from the interposer module. The TIM layer protection structure may thus provide enhanced reliability and better heat dissipation performance for the entire semiconductor package. The TIM layer protection structure may be positioned in an air gap surrounding an interposer module (e.g., a semiconductor die / wafer, an integrated fan-out chiplet, an integrated multiple logic chiplet, etc.) and between a package cover and a package substrate (e.g., an integrated circuit (IC) substrate).

[0086] In one or more embodiments, a TIM layer protection structure may be added to the semiconductor package after attaching the package cover to the package substrate on the interposer module. In one or more embodiments, the package cover may include a filling hole and a degassing hole. The TIM layer protection structure material (e.g., a liquid material) may be injected into the filling hole, and a gas (e.g., air, nitrogen, etc.) may leave the semiconductor package through the degassing hole.

[0087] For example, the TIM layer protection structure material may include a bottom fill material or similar material. The coefficient of thermal expansion (CTE) of the TIM layer protection structure may be between 3ppm / °C and 20ppm / °C. The thermal conductivity of the TIM layer protection structure may be greater than 1W / m·K.

[0088] The TIM layer protection structure material may be cured to form a solid TIM layer protection structure. The TIM layer protection structure may form a strong bond between the package cover, the package substrate, and the intermediate module (e.g., which may include a semiconductor die / wafer). The TIM layer protection structure may be formed below the package cover, above the package substrate, and around the intermediate module.

[0089] The ratio of the thickness of the TIM layer protection structure to the thickness of the intermediate module (e.g., the wafer thickness) may be greater than 1.0 and less than 3.0. In addition, the package cover may have a package cover length in the first direction, and the TIM layer protection structure may have a TIM layer protection structure length in the first horizontal direction. The ratio of the TIM layer protection structure length to the package cover length may be between 0.3 and 1.0. The package cover may also have a package cover width in a second horizontal direction perpendicular to the first horizontal direction, and the TIM layer protection structure may have a TIM layer protection structure width in the second horizontal direction. The ratio of the TIM layer protection structure width to the package cover width may be between 0.3 and 1.0.

[0090] Figures 1A to 1D Different views of a semiconductor package 100 (eg, an organic / silicon interposer package) are provided in accordance with one or more embodiments. Figure 1A FIG. 1 is a vertical cross-sectional view of a semiconductor package 100 according to one or more embodiments. Figure 1B FIG. 1 is an enlarged vertical cross-sectional view illustrating a filling hole 131 in a package cover 130 according to one or more embodiments. Figure 1C FIG. 1 is an enlarged vertical cross-sectional view illustrating a degassing hole 133 in a package cover 130 according to one or more embodiments. Figure 1D FIG. 1 is a plan view of a package cover 130 according to one or more embodiments.

[0091] The semiconductor package 100 may include a package substrate 110, an interposer 120 mounted on the package substrate 110, and a package cover 130 on the interposer 120 and attached to the package substrate 110. The semiconductor package 100 may further include a TIM layer 140 on the interposer 120. The semiconductor package 100 may further include a TIM layer protection structure 170 that may protect the TIM layer 140. In particular, the TIM layer protection structure 170 may suppress or mitigate delamination of the TIM layer 140 from the surface of the interposer 120.

[0092] For example, the package substrate 110 may include a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., on a first side or chip-side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., on a second side or board-side of the package substrate 110). In particular, the package substrate 110 may include a build-up film substrate such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0093] The core 112 may provide rigidity to the package substrate 110. For example, the core 112 may include an epoxy resin such as bismaleimide triazine epoxy (BT epoxy) and / or a woven glass laminate. The core 112 may alternatively or additionally include an organic material such as a polymer material. In particular, the core 112 may include a dielectric polymer material such as polyimide (PI), benzocyclo-butene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are contemplated to be within the scope of the disclosure.

[0094] The core 112 may include one or more vias 112a. The one or more vias 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The one or more vias 112a may allow electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. For example, the one or more vias 112a may include one or more film layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are included in the intended disclosure.

[0095] The lower dielectric layer 116 of the package substrate may include a plurality of film layers, and in particular may include a build-up film (e.g., ABF). The lower dielectric layer 116 of the package substrate may include an organic material such as a polymer material. In particular, the lower dielectric layer 116 of the package substrate may include one or more layers of a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are included within the intended disclosure.

[0096] The lower dielectric layer 116 of the package substrate may include one or more lower bonding pads 116a of the package substrate on the board side surface of the lower dielectric layer 116 of the package substrate. In particular, the lower bonding pads 116a of the package substrate may be exposed from the board side surface of the lower dielectric layer 116 of the package substrate. The lower dielectric layer 116 of the package substrate may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may be connected to the lower bonding pads 116a of the package substrate and the guide holes 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., copper traces) and a metal guide hole connecting the metal layer. For example, the lower bonding pads 116a of the package substrate and the metal interconnect structure 116b may include one or more film layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for the metal interconnect structure 116b are included in the expected disclosure range.

[0097] The package substrate lower surface layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The package substrate lower surface layer 110b may partially cover the package substrate lower bonding pad 116a. The package substrate lower surface layer 110b may include one or more passivation layers and protective layers. For example, the package substrate lower surface layer 110b may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). The package substrate lower surface layer 110b may alternatively or additionally include silicon oxide, silicon nitride, low dielectric constant (low-k) dielectric materials such as carbon-doped oxides, very low-k dielectric materials such as porous carbon doped silicon dioxide, or combinations thereof. Other suitable dielectric materials are included within the intended disclosure.

[0098] A ball-grid array (BGA) including a plurality of solder balls 110c may be formed on the board side surface of the lower dielectric layer 116 of the package substrate. The solder balls 110c may allow the semiconductor package 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may contact the lower bonding pads 116a of the package substrate, respectively.

[0099] A dielectric layer 114 on the package substrate may be formed on the upper surface of the core 112. The dielectric layer 114 on the package substrate may also include a plurality of film layers, and may specifically include a build-up film (e.g., ABF). The dielectric layer 114 on the package substrate may also include an organic material such as a polymer material. In particular, the dielectric layer 114 on the package substrate may include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Other suitable dielectric materials are included within the intended disclosure.

[0100] The package substrate upper dielectric layer 114 may include one or more package substrate upper bonding pads 114a on the wafer-side surface of the package substrate upper dielectric layer 114. In particular, the package substrate upper bonding pads 114a may be exposed from the wafer-side surface of the package substrate upper dielectric layer 114. In at least one embodiment, a bonding pad surface layer (not shown) (e.g., one or more layers of metal (e.g., tin, nickel, palladium, gold, etc.) and / or other materials) may be formed on the package substrate upper bonding pads 114a to improve solder joint reliability.

[0101] The dielectric layer 114 on the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may include a metal layer (e.g., a copper wire) and a metal via connecting the metal layer. The bonding pad 114a on the package substrate may be electrically connected to the solder ball 110c of the BGA through the metal interconnect structure 114b, the via 112a, the metal interconnect structure 116b, and the bonding pad 116a under the package substrate. For example, the bonding pad 114a on the package substrate and the metal interconnect structure 114b may include one or more film layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are included in the expected disclosure.

[0102] The package substrate upper surface layer 110a may be formed on the wafer side surface of the package substrate upper dielectric layer 114. The package substrate upper surface layer 110a may include a plating layer, a laminate, etc. The package substrate upper surface layer 110a may be formed to at least partially cover the package substrate upper bonding pad 114a.

[0103] In at least one embodiment, the upper surface layer 110a of the package substrate may include a solder resist layer (e.g., a solder mask layer). The solder resist layer may include a thin layer of a polymer material (e.g., an epoxy polymer). The thickness of the solder resist layer may be between about 5 μm and 50 μm. In at least one embodiment, the thickness of the solder resist layer may be between about 10 μm and 30 μm. Solder resist layers with greater or lesser thicknesses may be used. The solder resist layer may be formed to cover the bonding pads 114a on the package substrate and other metal components (e.g., wires, copper wires) on the wafer side surface of the package substrate 110. The solder resist layer may protect the bonding pads 114a and other metal components on the package substrate from oxidation. The solder resist layer may also inhibit (e.g., prevent) the formation of solder bridges (e.g., unintentional electrical connections) between closely spaced metal components. The solder resist layer may include a plurality of solder resist openings (SROs) respectively located above the bonding pads 114a on the package substrate. The upper surface of the bonding pad 114a on the package substrate may be exposed by a plurality of SROs. The SRO may have a tapered sidewall so that the diameter of the SRO (in the XY plane) may decrease in a direction toward the bonding pad 114a on the package substrate.

[0104] The upper surface layer 110a of the package substrate may alternatively or additionally include a film layer different from the solder mask layer, such as a passivation layer or a protective layer. In particular, the upper surface layer 110a of the package substrate may alternatively or additionally include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. For example, the upper surface layer 110a of the package substrate may alternatively or additionally be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination, or other suitable deposition techniques.

[0105] The interposer 120 may be mounted via a controlled collapse chip connection (C4) bump 121 on a bonding pad 114a on a package substrate in the package substrate 110. The interposer 120 may include an interposer dielectric layer 122, which may include a metal interconnect 122a electrically connected to the C4 bump 121. The interposer 120 may also include a first semiconductor die 123 and a second semiconductor die 124, which may be mounted on the interposer dielectric layer 122, respectively. It should be noted that any number of semiconductor dies may be mounted on the interposer dielectric layer 122.

[0106] The first semiconductor die 123 and the second semiconductor die 124 may be mounted on the interposer dielectric layer 122 via micro bumps 128 that may be electrically connected to the metal interconnects 122a. A package underfill layer 129 may be formed under and around the interposer module 120 and the C4 bumps 121 to fix the interposer module 120 to the package substrate 110. The package underfill layer 129 may be formed of a polymer material such as epoxy resin.

[0107] For example, each of the first semiconductor die 123 and the second semiconductor die 124 may include a semiconductor chip or chiplet for high performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a dynamic random access memory (DRAM) die, a wide I / O die, an M-RAM die, an R-RAM die, a NAND die, a static random access memory (SRAM), etc.), a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field-programmable gate array (FPGA) die, a network chip, a specific integrated circuit (ASIC) chip, an artificial intelligence / deep neural network (AI / DNN) chip, etc. network, AI / DNN) accelerator chips, etc., co-processors, accelerators, on-chip memory buffers, memory cubes (such as HBM, HMC, etc.), high data rate transceiver dies, I / O interface dies, IPD dies (e.g., integrated passives device), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end,AFE) die), monolithic 3D heterogeneous chiplet stacking die, etc.

[0108] For example, each of the first semiconductor die 123 and the second semiconductor die 124 may include an active region (not shown). The active region may include a front end of line (FEOL) region, which includes an electronic circuit including various electronic devices (e.g., transistors, resistors, etc.). In particular, the FEOL region may include one or more logic circuits and / or one or more memory circuits. The logic circuit includes a logic device (e.g., a logic gate), and the memory circuit includes a memory device (e.g., a volatile memory (VM) device and / or a non-volatile memory (non-volatile memory) device. The active region may also include a back end of line (BEOL) region, which may include an interlayer dielectric having multiple dielectric layers. For example, the dielectric layer may include SiO2, a dielectric polymer, or other suitable dielectric materials. The interlayer dielectric may include one or more metal interconnect structures formed therein. The metal interconnect structure may include metal lines and metal vias formed in the dielectric layer and provide electrical connections to the electronic circuits in the FEOL region.

[0109] An intervening bottom filling layer 126 may be formed around the micro-bumps 128, between the first semiconductor die 123 and the intervening dielectric layer 122, and between the second semiconductor die 124 and the intervening dielectric layer 122. Figure 1A As shown, the intermediate bottom filling layer 126 may be continuously formed under both the first semiconductor die 123 and the second semiconductor die 124. Alternatively, the intermediate bottom filling layer 126 may be formed in a separate portion under each of the first semiconductor die 123 and the second semiconductor die 124. The intermediate bottom filling layer 126 may also be formed between the first semiconductor die 123 and the second semiconductor die 124. The intermediate bottom filling layer 126 may also be formed of a polymer material such as epoxy resin.

[0110] A molding material layer 127 may be formed on the first semiconductor die 123, the second semiconductor die 124, the intervening underfill layer 126, and the intervening dielectric layer 122. The molding material layer 127 may be formed of an epoxy molding compound (EMC).

[0111] For example, the TIM layer 140 may include a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. Other types of TIMs are included within the intended scope of the present disclosure. In at least one embodiment, the TIM layer 140 may be between 30 μm and 150 μm. The TIM layer 140 may be formed on the intermediate module 120 to dissipate heat energy generated during operation of the semiconductor package 100 (e.g., operation of the first semiconductor die 123 and the second semiconductor die 124). For example, the TIM layer 140 may be attached to the intermediate module 120 by a thermally conductive adhesive. In particular, the TIM layer 140 may be brought into contact with the upper surface of the first semiconductor die 123, the upper surface of the second semiconductor die 124, the upper surface of the molding material layer 127, and / or the upper surface of the intermediate bottom fill layer 126. The TIM layer 140 may have a low bulk thermal impedance and a high thermal conductivity. The bond-line-thickness (BLT) (eg, the distance between package lid 130 and interposer 120 ) may be less than about 100 μm, although larger or smaller distances may be used.

[0112] The semiconductor package 100 may further include a stiffener ring 150, which may be fixed to the package substrate 110 by an adhesive 160 such as a silicone adhesive or an epoxy adhesive. Other adhesives are included within the intended scope of the present disclosure. The stiffener ring 150 may be formed of a metal such as copper or an aluminum alloy with a nickel coating. The stiffener ring 150 may alternatively be formed of a ceramic material or a hard plastic (polymer) material. The stiffener ring 150 may be formed on the package substrate 110 so that the stiffener ring 150 surrounds (e.g., encircles) the intermediate module 120 in the xy plane. The stiffener ring 150 may be extended from the package substrate 110 in a substantially vertical direction (e.g., in the z direction). The stiffener ring 150 may help provide rigidity to the package substrate 110 and the intermediate module 120.

[0113] The package cover 130 may be connected to the reinforcement ring 150 to cover the intermediate module 120. The package cover 130 may be fixed to the reinforcement ring 150 by an adhesive 161 (e.g., a silicone adhesive or an epoxy adhesive). The package cover 130 may be in contact with at least a portion of the TIM layer 140. In one or more embodiments, the package cover 130 may be in direct contact with the entire upper surface of the TIM layer 140. For example, the package cover 130 may be formed of a metal, a ceramic, or a polymer material. The package cover 130 may be plate-shaped (e.g., a planar shape) and substantially parallel to the upper surface of the package substrate 110. For example, the package cover 130 may be Figure 1AThe package cover 130 may include a central portion that is substantially aligned with a central portion of the interposer module 120 in the z-direction.

[0114] The package cover 130 may include a bottom surface 130a and an upper surface 130b, the upper surface 130b being opposite to the bottom surface 130a in the z direction. The package cover 130 may have a thickness T130. The bottom surface 130a of the package cover 130 may extend across the package cover 130 between the opposite sides of the reinforcement ring 150 and contact the TIM layer 140. The TIM layer 140 may be compressed between the bottom surface 130a of the package cover 130 and the upper surface of the intermediate module 120. The bottom surface 130a of the package cover 130 may be fixed to the reinforcement ring 150 by an adhesive 161. The bottom surface 130a may be a substantially plane. In particular, the height of the bottom surface 130a from the upper surface layer 110a of the package substrate (e.g., in the z direction) may be substantially uniform over the entire bottom surface 130a. Alternatively, the package cap 130 may further include a bottom stepped region (not shown), which may protrude from the bottom surface 130a and contact the TIM layer 140. The bottom stepped region may extend from the bottom surface 130a in a substantially vertical direction. The bottom stepped region may be formed around a central region of the package cap 130.

[0115] The semiconductor package 100 may further include a TIM layer protection structure 170. The TIM layer protection structure 170 may help protect the TIM layer 140, and in particular may help inhibit (e.g., prevent) the TIM layer 140 from delaminating from the interposer 120. Thus, the TIM layer protection structure 170 may provide the semiconductor package 100 with enhanced reliability and better heat dissipation performance.

[0116] The TIM layer protection structure 170 may include a material substantially similar to the package underfill layer 129 and / or the interposer underfill layer 126. In at least one embodiment, the TIM layer protection structure 170 may include a polymer material, and in particular, an epoxy-based polymer material. In at least one embodiment, the TIM layer protection structure 170 may include an added material (e.g., a filler material) for enhancing the properties (e.g., thermal conductivity, CTE, etc.) of the TIM layer protection structure 170. For example, the added material may include metal powder, metal oxide powder, etc. Other materials in the TIM layer protection structure 170 are also included in the intended scope of the present disclosure.

[0117] The TIM layer protection structure 170 may be positioned in a space (e.g., an air gap) surrounding the interposer module 120, between the interposer module 120 and the stiffener ring 150, and between the package cover 130 and the package substrate 110. In at least one embodiment, the TIM layer protection structure 170 may substantially fill the space (e.g., an air gap) surrounding the interposer module 120.

[0118] In at least one embodiment, the coefficient of thermal expansion (CTE) of the TIM layer protection structure 170 may be between 3ppm / °C and 20ppm / °C. In at least one embodiment, the thermal conductivity of the TIM layer protection structure may be greater than 1W / m·K. In at least one embodiment, the CTE of the TIM layer protection structure may be greater than the CTE of the TIM layer. In at least one embodiment, the thermal conductivity of the TIM layer protection structure may be greater than the thermal conductivity of the TIM layer. In at least one embodiment, the TIM layer protection structure 170 may be formed of a curable material that can be cured into a hard solid structure. The ratio of the thickness T170 of the TIM layer protection structure 170 to the thickness T120 of the intermediate module 120 (e.g., the wafer thickness) may be greater than 1.0 and less than 3.0. The TIM layer protection structure 170 may form a strong bond between the package cover 130, the package substrate 110, and the intermediate module 120. In at least one embodiment, the TIM layer protection structure 170 can be bonded to one or more of the bottom surface 130a of the package cover 130, the upper surface of the package substrate 110, the outer surface (sidewall) of the TIM layer 140, the outer surface (sidewall) of the intermediate module 120, the inner surface (sidewall) of the reinforcement ring 150, the package bottom filling layer 129, the adhesive 160 and the adhesive 161.

[0119] In at least one embodiment, a TIM layer protection structure 170 may be added to the semiconductor package 100 through a filling hole 131 in the package cover 130. The package cover 130 may also include a degassing hole 133 to facilitate the addition of the TIM layer protection structure 170. The package cover 130 may also include a filling plug 132 and a degassing plug 134, which are used to plug the filling hole 131 and the degassing hole 133, respectively. The filling plug 132 and the degassing plug 134 may include a polymer material, and in particular, an epoxy resin-based polymer material. Other materials are included within the intended scope of the present disclosure.

[0120] Reference Figure 1B , the diameter D131 (eg, width) of the filling hole 131 may be between 3 mm and 10 mm. The diameter D131 may be substantially uniform over the height (in the z-direction) of the filling hole 131. In at least one embodiment, the diameter D131 may vary over the height (in the z-direction) of the filling hole 131. Figure 1B As shown, the filling hole 131 may extend in the z-direction substantially perpendicular to the package cover 130. Alternatively, the filling hole 131 may be inclined relative to the package cover 130.

[0121] The filling hole 131 may be positioned in the central region of the TIM layer protection structure 170. The filling hole 131 may be separated from the intermediate module 120 by an inner length L131i. The filling hole 131 may be separated from the reinforcement ring 150 by an outer length L131o. In at least one embodiment, the filling hole 131 may be equidistant from the intermediate module 120 and from the reinforcement ring 150 (e.g., inner length L131i=outer length L131o).

[0122] The filling plug 132 may extend from the bottom surface 130a of the packaging cover 130 to the upper surface 130b of the packaging cover 130. The upper surface of the filling plug 132 may be substantially coplanar with the upper surface 130b of the packaging cover 130. The bottom surface of the filling plug 132 may be substantially coplanar with the bottom surface 130a of the packaging cover 130. Therefore, the thickness of the filling plug 132 may be substantially the same as the thickness T130 of the packaging cover 130. The filling plug 132 may fill the entire filling hole 131 and completely seal the filling hole 131. The filling plug 132 may be adhered and bonded to the wall of the filling hole 131 throughout the filling hole 131.

[0123] like Figure 1B As further shown, the TIM layer protection structure 170 may include a TIM layer protection structure interface portion 170i. The TIM layer protection structure interface portion 170i may contact the side surface of the TIM layer 140 and the side surface of the molding material layer 127 (e.g., the intermediate module 120) at the interface between the TIM layer 140 and the molding material layer 127. The TIM layer protection structure interface portion 170i may extend continuously from the side surface of the TIM layer 140 to the side surface of the molding material layer 127, thereby helping to inhibit (e.g., prevent) the TIM layer 140 from being delaminated from the molding material layer 127.

[0124] Reference Figure 1C , the diameter D133 (e.g., width) of the degassing hole 133 may also be between 3 mm and 10 mm. The diameter D133 may also be substantially uniform over the height (in the z-direction) of the degassing hole 133. In at least one embodiment, the diameter D133 may vary over the height (in the z-direction) of the degassing hole 133. In at least one embodiment, the diameter D133 of the degassing hole 133 may be different from (e.g., smaller than) the diameter D131 of the filling hole 131. Figure 1C As shown, the degassing holes 133 may extend in the z-direction substantially perpendicular to the package cover 130. Alternatively, the degassing holes 133 may be inclined relative to the package cover 130.

[0125] The degassing hole 133 may be positioned in the central area of ​​the TIM layer protection structure 170. The degassing hole 133 may be spaced apart from the intermediate module 120 by a diameter D133. The degassing hole 133 may be spaced apart from the reinforcement ring 150 by an outer length L133o. In at least one embodiment, the degassing hole 133 may be equidistant from the intermediate module 120 and from the reinforcement ring 150 (e.g., inner length L131i=outer length L131o). In at least one embodiment, the inner length L131i may be greater than the outer length L133o (e.g., inner length L131i>outer length L131o). That is, the degassing hole 133 may be positioned in the package cover 130 to be closer to the reinforcement ring 150 than the intermediate module 120.

[0126] The degassing plug 134 may also extend from the bottom surface 130a of the packaging cover 130 to the upper surface 130b of the packaging cover 130. The upper surface of the degassing plug 134 may be substantially coplanar with the upper surface 130b of the packaging cover 130. The bottom surface of the degassing plug 134 may be substantially coplanar with the bottom surface 130a of the packaging cover 130. Therefore, the thickness of the degassing plug 134 may be substantially the same as the thickness T130 of the packaging cover 130. The degassing plug 134 may fill the entire degassing hole 133 and completely seal the degassing hole 133. The degassing plug 134 may be bonded and joined to the wall of the degassing hole 133 throughout the degassing hole 133.

[0127] exist Figure 1D , the package cover 130 is shown at the locations indicated by the dashed lines on each of the reinforcement ring 150, the intermediate module 120 (and the TIM layer 140), and the TIM layer protection structure 170. Figure 1D As shown, package cover 130 can have a rectangular shape. Other shapes are within the intended scope of the present disclosure.

[0128] In particular, the package cover 130 may have a length L130 in a first horizontal direction (i.e., the x-direction) and a width W130 in a second horizontal direction (i.e., the y-direction). A TIM layer protection structure 170 may be formed around the entire periphery of the intermediate module 120 and the TIM layer 140. The TIM layer protection structure 170 may have a length L170 in the first horizontal direction (i.e., the x-direction) and a width W170 in the second horizontal direction (i.e., the y-direction). A ratio R1 of the length L170 of the TIM layer protection structure 170 to the length L130 of the package cover 130 may be between 0.3 and 1.0. A ratio R2 of the width W170 of the TIM layer protection structure 170 to the width W130 of the package cover 130 may be between 0.3 and 1.0. The ratio R1 and the ratio R2 may be between 0.3 and 1.0 to ensure that the TIM layer protection structure 170 provides sufficient bonding between the package cover 130 , the package substrate 110 and the interposer module 120 .

[0129] like Figure 1D As shown, the filling hole 131 (and the filling plug 132) and the degassing hole 133 (and the degassing plug 134) may be substantially aligned with the opposing corners of the package cover 130 and / or the opposing corners of the intermediate module 120. Other positions of the filling hole 131 (and the filling plug 132) and the degassing hole 133 (and the degassing plug 134) are included in the expected disclosure range. Each of the filling hole 131 and the degassing hole 133 may have a circular cross-sectional shape. Other shapes (e.g., elliptical, linear, rectangular) are included in the expected disclosure range. In at least one embodiment, the cross-sectional shape of the filling hole 131 (and the filling plug 132) may be different from the cross-sectional shape of the degassing hole 133 (and the degassing plug 134).

[0130] It should be noted that the diameter D131 of the filling hole 131 and the diameter D133 of the degassing hole 133 may depend on the thickness of the package cover 130. In at least one embodiment, the diameter D131 and the diameter D133 may increase as the thickness of the package cover 130 increases. The diameter D131 and the diameter D133 may also depend on the volume of the space to be filled by the TIM layer protection structure 170 (i.e., the volume defined by the inner reinforcement ring 150 and the intermediate module 120, and the volume defined by the top surface of the package substrate 110 and the bottom surface of the package cover 130). In at least one embodiment, the diameter D131 and the diameter D133 may increase as the volume of the space increases.

[0131] FIG. 2A to FIG. 2I A method of forming a semiconductor package 100 is shown according to one or more embodiments. Figure 2A A vertical cross-sectional view of an intermediate structure including a bonding pad 114a on a package substrate and a bonding pad 116a under a package substrate is shown according to one or more embodiments. For example, a bonding pad 114a on a package substrate may be formed on the topmost dielectric layer of a dielectric layer 114 on a package substrate. A bonding pad 114a on a package substrate may be formed and contact a metal interconnect structure 114b. The bonding pad 114a on a package substrate may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the topmost dielectric layer of the dielectric layer 114 on the package substrate. Then, the metal layer may be patterned by etching (e.g., wet etching, dry etching, etc.) to form a bonding pad 114a on a package substrate. Other suitable metal layer materials and etching processes may be included within the intended disclosure.

[0132] For example, a bonding pad 116a under the package substrate may be formed on the lowest dielectric layer of the dielectric layer 116 under the package substrate. The bonding pad 116a under the package substrate may be formed and contact the metal interconnect structure 116b. The bonding pad 116a under the package substrate may be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive materials) on the lowest dielectric layer of the dielectric layer 114 on the package substrate. Then, the metal layer may be patterned by etching (e.g., wet etching, dry etching, etc.) to form the bonding pad 116a under the package substrate. Other suitable metal layer materials and etching processes may be included in the intended disclosure.

[0133] After formation, the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate may be optionally subjected to a surface roughening treatment (e.g., copper surface roughening treatment, also referred to as CZ treatment). In the surface roughening treatment, the surface (e.g., copper surface) of the upper bonding pad 114a of the package substrate and the surface (e.g., copper surface) of the lower bonding pad 116a of the package substrate may be etched by an organic acid microetching solution. The uniquely-roughened copper surface topography of the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate may help achieve high copper-to-resin adhesion.

[0134] Figure 2B 1 is a vertical cross-sectional view of an intermediate structure including an upper surface layer 110a of a package substrate and a lower surface layer 110b of a package substrate according to one or more embodiments. In at least one embodiment, the upper surface layer 110a of the package substrate may include a solder resist layer (e.g., a polymer material), which is also referred to as a solder mask. The upper surface layer 110a of the package substrate may also be referred to as an upper solder resist layer 110a, and the lower surface layer 110b of the package substrate may also be referred to as a lower solder resist layer 110b.

[0135] The upper surface layer 110a of the packaging substrate and the lower surface layer 110b of the packaging substrate may be applied concurrently. For example, the upper surface layer 110a of the packaging substrate and the lower surface layer 110b of the packaging substrate may be applied in the form of a liquid photo-imageable film. For example, the liquid photo-imageable film may be applied by silk-screening or spraying the liquid photo-imageable film onto the surface of the packaging substrate 110. The liquid photo-imageable film may be applied onto the upper bonding pad 114a of the packaging substrate and the lower bonding pad 116a of the packaging substrate. Alternatively, the upper surface layer 110a of the packaging substrate and the lower surface layer 110b of the packaging substrate may be applied in the form of a dry-film photo-imageable film, which may be vacuum-laminated onto the surface of the packaging substrate 110 and onto the upper bonding pad 114a of the packaging substrate and the lower bonding pad 116a of the packaging substrate, respectively.

[0136] The package substrate upper surface layer 110a and the package substrate lower surface layer 110b may be applied to have a thickness slightly greater than the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. Alternatively, the package substrate upper surface layer 110a and the package substrate lower surface layer 110b may be applied to have upper surfaces substantially coplanar with the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively.

[0137] Figure 2C FIG. 1 is a vertical cross-sectional view showing an intermediate structure including an opening O110 a in an upper surface layer 110 a of a package substrate and an opening O110 b in a lower surface layer 110 b of a package substrate according to one or more embodiments.

[0138] An opening O110a may be formed in the upper surface layer 110a of the package substrate to expose the upper surface of the bonding pad 114a on the package substrate. An opening O110b may be formed in the lower surface layer 110b of the package substrate to expose the upper surface of the bonding pad 116a under the package substrate. For example, the opening O110b and the opening O110b may be formed using a photolithography process. In at least one embodiment, the opening O110b and the opening O110b may be formed in different photolithography processes.

[0139] The photolithography process (e.g., multiple processes) for forming the opening O110a may include: forming a patterned photolithography mask (not shown) on the upper surface layer 110a of the packaging substrate, and etching the upper surface of the upper surface layer 110a of the packaging substrate exposed from the opening of the photolithography mask (e.g., wet etching, dry etching, etc.). Subsequently, the photolithography mask may be removed by ashing, dissolving, or consuming the photolithography mask during the etching process.

[0140] The photolithography process (e.g., multiple processes) for forming the opening O110b may include: forming a patterned photolithography mask (not shown) on the packaging substrate lower surface layer 110b, and etching the upper surface of the packaging substrate lower surface layer 110b exposed from the opening of the photolithography mask (e.g., wet etching, dry etching, etc.). Subsequently, the photolithography mask may be removed by ashing, dissolving, or consuming the photolithography mask during the etching process.

[0141] After forming opening O110a in the upper surface layer 110a of the packaging substrate and forming opening O110b in the lower surface layer 110b of the packaging substrate, the upper surface layer 110a (upper solder resist layer) of the packaging substrate and the lower surface layer 110b of the packaging substrate can be cured, such as by thermal curing or ultraviolet (UV) curing.

[0142] Figure 2D FIG. 2 is a vertical cross-sectional view of an intermediate structure in which an interposer module 120 may be mounted on a package substrate 110 (eg, via a flip chip bonding (FCB) process) according to one or more embodiments. Figure 2D As shown, the C4 bumps 121 of the interposer module 120 may be located on the package substrate bonding pads 114 a of the package substrate 110 , and may be heated so that the C4 bumps 121 are bonded to the package substrate bonding pads 114 a .

[0143] Figure 2E FIG. 2 is a vertical cross-sectional view of an intermediate structure according to one or more embodiments, wherein a package bottom filling layer 129 may be formed on a package substrate 110. The package bottom filling layer 129 may be formed of a polymer material such as epoxy resin. Figure 2E As shown, a package underfill layer 129 may be formed (e.g., injected) under and around the interposer 120 and the C4 bumps 121 to fix the interposer 120 to the package substrate 110. Next, the package underfill layer 129 may be cured, for example, in a box oven at a temperature ranging from 120° C. to 180° C. for about 60 minutes to 120 minutes to provide the package underfill layer 129 with sufficient rigidity and mechanical strength.

[0144] Figure 2F 1 is a vertical cross-sectional view of an intermediate structure in which a TIM layer 140 may be attached to the upper surface of the interposer module 120 according to one or more embodiments. For example, the TIM layer 140 may include a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. The TIM layer 140 may be attached to the upper surface 140 of the interposer module 120 by applying a thermally conductive adhesive to the upper surface of the interposer module 120 (or to the bottom surface of the TIM layer 140), and then pressing the TIM layer onto the interposer module 120.

[0145] Figure 2G 1 is a vertical cross-sectional view of an intermediate structure, wherein an adhesive 160 may be applied to a package substrate 110, according to one or more embodiments. For example, the adhesive may include a silicone resin adhesive or an epoxy resin adhesive. The adhesive may be positioned on the package substrate 110 at a location corresponding to the location of the reinforcement ring 150, and applied in a sufficient amount to securely bond the reinforcement ring 150 to the package substrate 110.

[0146] Figure 2H 1 is a vertical cross-sectional view of an intermediate structure in which a reinforcement ring 150 may be attached to (e.g., mounted on) a package substrate 110 according to one or more embodiments. As described above, the reinforcement ring 150 may be formed of metal, ceramic, or plastic. For example, the reinforcement ring 150 may be formed by milling using a computer numerical control (CNC) milling machine, or by molding or stamping.

[0147] exist Figure 2H In the embodiment, the package substrate 110 with the intermediate module 120 may be placed on a surface, and the reinforcement ring 150 may be lowered onto the intermediate module 120 and onto the package substrate 110. Then, the reinforcement ring 150 may be aligned with the adhesive 160 (e.g., a ring of adhesive material) formed on the package substrate 110. Then, the reinforcement ring 150 may be pressed downward by applying pressure downward to the upper surface of the reinforcement ring 150 so that the reinforcement ring 150 may be firmly fixed to the package substrate 110 through the adhesive 160. Alternatively, the reinforcement ring 150 may be placed on a surface (e.g., a flat surface), and the intermediate module 120 on the package substrate 110 may be placed upside down into the reinforcement ring 150. Then, pressure may be applied downward to the package substrate lower surface layer 110b of the package substrate 110 to bond the package substrate 110 to the reinforcement ring 150.

[0148] Fig.2I FIG. 2 is a vertical cross-sectional view of an intermediate structure in which a package cover 130 may be attached to a reinforcement ring 150 according to one or more embodiments. Fig.2I As shown, in the method for forming a semiconductor package, the package cover 130 may include a filling hole 131 and a degassing hole 133. The package cover 130 may not include a filling plug 132 and a degassing plug 134.

[0149] Adhesive 161 may be applied to an upper surface (e.g., the entire upper surface) of the reinforcement ring 150. Alternatively, adhesive 161 may be applied to a position of the bottom surface 130a of the package cover 130 corresponding to the position of the reinforcement ring 150. The package cover 130 may then be aligned with the reinforcement ring 150 and lowered onto the reinforcement ring 150 and the TIM layer 140. The package cover 130 may then be clamped onto the package substrate 110 for a period of time to allow the adhesive 161 and adhesive 160 to cure and form a secure bond between the package substrate 110, the reinforcement ring 150, and the package cover 130. For example, the package cover 130 may be clamped to the package substrate 110 using a heat clamp module. The heat clamp module may apply a uniform force across the upper surface of the package cover 130. Refer to Figure 5 , the reinforcement ring 150 and the packaging cover 130 may be integrally formed in a single structure.

[0150] Figure 2J 1 is a vertical cross-sectional view of an intermediate structure, wherein a TIM layer protection structure 170 may be added to a semiconductor package 100, according to one or more embodiments. In at least one embodiment, a material (e.g., a curable material, a liquid material) for forming the TIM layer protection structure 170 may be added to the semiconductor package through the filling hole 131. In particular, the material may be injected (e.g., manually injected) into the semiconductor package 100 to fill a volume (e.g., an air gap) around the interposer 120, wherein the volume is constrained by the stiffening ring 150 and the package cover 130. While the material is injected, gas (e.g., air, nitrogen, etc.) may leave the semiconductor package 100 through the degassing holes 133 in the package cover 130.

[0151] In at least one embodiment, the material of the TIM layer protection structure 170 may be injected into the filling hole 131 until the material of the TIM layer protection structure 170 reaches the degassing hole 133. That is, when the material of the TIM layer protection structure 170 reaches the degassing hole 133, the injection of the material may be stopped. In at least one embodiment, when the uppermost surface of the TIM layer protection structure 170 is substantially coplanar with the bottom surface 130a, the bottom end of the filling hole 131, and the bottom end of the degassing hole 133, the injection of the material may be stopped. In at least one embodiment, when the TIM layer protection structure 170 fills the entire volume between the intermediate module 120 and the reinforcement ring 150, the injection of the material may be stopped.

[0152] Figure 2K FIG. 1 is a plan view of an intermediate structure including a TIM layer protection structure 170 on a package substrate 110 according to one or more embodiments. Figure 2K The packaging cover 130 is omitted. Figure 2K The positions of the filling holes 131 and the degassing holes 133 are indicated by dotted lines.

[0153] Figure 2K The directional arrows in show the flow direction of the material of the TIM layer protection structure 170 when it is injected into the filling hole 131. As further shown, the material may initially spread locally around the periphery of the filling hole 131. The material may spread toward the intermediate module 120 along the upper surface layer 110a of the packaging substrate. The first portion of the material may be caused by the intermediate module 120 to initially flow around the intermediate module 120 in the x-direction. The second portion of the material may be caused by the intermediate module 120 to initially flow around the intermediate module 120 in the y-direction. The flow rate of the first portion and the flow rate of the second portion may be substantially the same. The first portion and the second portion may arrive at the degassing hole 133 substantially at the same time.

[0154] In at least one embodiment, the material of the TIM layer protection structure 170 can be automatically filled. In particular, various aspects of the filling process can be computer-controlled by a control system (e.g., an electronic control system; a central processing unit (CPU)). In at least one embodiment, the control system can control the execution of: starting material injection, the flow rate of the injected material, and stopping the material injection.

[0155] In at least one embodiment, a vacuum tube may be connected to the degassing hole 133 so that the volume around the intermediate module 120 can be evacuated. An imaging device (e.g., a camera) may be connected to the portion of the vacuum tube that is inserted into the degassing hole 133. The vacuum tube and the imaging device may also be controlled by a control system. The imaging device may detect the level of the material of the TIM layer protection structure 170. The output of the imaging device may be transmitted (e.g., via a wired or wireless signal) to the control system. When the output of the imaging device indicates that the material has reached a certain level within the semiconductor package 100 (e.g., when the material has reached the degassing hole 133), the control system may stop the injection of the material and stop the vacuum of the vacuum tube.

[0156] Alternatively, the control system may be programmed to inject a predetermined volume of material based on various input parameters, such as the volume of the space surrounding the intermediate module 120 , the size of the intermediate module 120 , the size of the package cover 130 , the size of the reinforcement ring 150 , etc.

[0157] In at least one embodiment, the material used to form the TIM layer protection structure 170 (e.g., an epoxy-based polymer material) may include a capillary material (e.g., a capillary bottom fill type material). The material may have a low viscosity. In particular, the viscosity of the material may be less than the viscosity of the material of the package bottom fill layer 129. In at least one embodiment, the viscosity may be less than about 5000 cP at 10 rpm. In at least one embodiment, the material may include a low viscosity suspension of a thermally conductive material (e.g., a metal, a metal oxide) in a prepolymer. Low viscosity may help promote material transport around and through the surrounding space of the intermediate module 120. Low viscosity may also help avoid the formation of voids in the TIM layer protection structure 170. In at least one embodiment, the TIM layer protection structure 170 may be substantially free of voids.

[0158] In the process of adding the material of the TIM layer protection structure 170, the material may contact and flow over the surface of the upper surface layer 110a of the package substrate (e.g., solder mask layer). The surface of the upper surface layer 110a of the package substrate may have a low surface roughness. In particular, the surface roughness of the upper surface layer 110a of the package substrate may be less than the surface roughness of the bottom surface 130a of the package cover 130. In at least one embodiment, the surface roughness (arithmetic mean roughness (arithmetical mean roughness, Ra)) of the upper surface layer 110a of the package substrate may be less than 1.0 nm (Ra<1.0 nm). Low surface roughness may help promote the flow (transmission) of the material in the surrounding space of the intermediate module 120. For example, the roughness value may include the arithmetic mean roughness (Ra), the ten-point mean roughness (Rz), the Rq (root-mean-square (rms) value of the departures of the profile from the mean line) and / or the maximum height or depth (Rmax). However, other measures of roughness, such as the mean spacing of profile irregularities (Sm), the mean spacing of local peaks of the profile (S), and the profile bearing length ratio (tp), may be included within the scope of the present disclosure.

[0159] Figure 2L1 is a vertical cross-sectional view of an intermediate structure including a filling plug 132 and a degassing plug 134 according to one or more embodiments. After adding (e.g., filling the space) the material for forming the TIM layer protection structure 170, the filling plug 132 may be added (e.g., injected, inserted) in the filling hole 131. The degassing plug 134 may also be added (e.g., injected, inserted) in the degassing hole 133 of the package cover 130. The filling plug 132 and the degassing plug 134 may include the same material as the TIM layer protection structure 170. In at least one embodiment, the filling plug 132 may be formed in the filling hole 131 by injecting a plug material (epoxy resin-based polymer material) into the filling hole 131. The degassing plug 134 may be formed in the degassing hole 133 by injecting a plug material (epoxy resin-based polymer material) into the degassing hole 133. In at least one embodiment, the filling plug 132 and the degassing plug 134 may be formed simultaneously when the TIM layer protection structure 170 is formed.

[0160] In an alternative embodiment, the material of the filling plug 132 may be different from the material of the degassing plug 134. For example, the material of one of the filling plug 132 and the degassing plug 134 may include a silicone resin-based material, and the material of the other of the filling plug 132 and the degassing plug 134 may include an epoxy resin-based polymer material. In another alternative embodiment, the material of the filling plug 132 and / or the degassing plug 134 may be different from the material of the TIM layer protection structure 170.

[0161] Figure 2M 1 is a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c may be formed on a package substrate 110 according to one or more embodiments. A plurality of solder balls 110c may be formed on a lower bonding pad 116a of the package substrate through an opening in a lower surface layer 110b of the package substrate. For example, the solder balls 110c may be formed by an electroplating process. For example, the solder balls 110c may be positioned below the reinforcement ring 150 and below the intermediate module 120. The plurality of solder balls 110c may form a ball grid array (BGA), which may allow the semiconductor package 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate. The formation of the solder balls 110c may complete the formation of the semiconductor package 100.

[0162] Figure 3 A flow chart of a method for forming a semiconductor package is shown according to one or more embodiments. Step 310 includes mounting an interposer module on a package substrate. Step 320 includes positioning a thermal interface material (TIM) layer on the interposer module. Step 330 includes positioning a package cover on the interposer module and the TIM layer. Step 340 includes forming a TIM layer protection structure on one side of the TIM layer and the interposer module through a filling hole in the package cover.

[0163] FIG. 4A to FIG. 4C FIG. 1 is a plan view showing an alternative design of the package cover 130 according to one or more embodiments. In particular, Figure 4A FIG. 1 is a plan view showing a first alternative design of the package cover 130 according to one or more embodiments. In the first alternative design, the distance between the degassing hole 133 and the adjacent corner of the stiffening ring 150 may be smaller than the distance between the filling hole 131 and the adjacent corner of the stiffening ring 150. This design may help to allow more material of the TIM layer protection structure 170 to fill the space between the interposer 120 and the stiffening ring 150 before the material reaches the degassing hole 133.

[0164] Figure 4B FIG. 1 is a plan view showing a second alternative design of the package cover 130 according to one or more embodiments. In the second alternative design, the filling hole 131 and the degassing hole 133 may be positioned on opposite sides of the interposer module 120 (and the TIM layer 140) in the x-direction. The x-direction may include the longitudinal direction of the package cover 130. In at least one embodiment, the filling hole 131 and the degassing hole 133 may be substantially aligned with the center region of the interposer module 120 (and the TIM layer 140).

[0165] Figure 4C FIG. 1 is a plan view showing a third alternative design of the package cover 130 according to one or more embodiments. In the third alternative design, the cross-sectional shape of the filling hole 131 and the filling plug 132 may be oval or elliptical. The longitudinal direction of the filling hole 131 and the filling plug 132 may be substantially perpendicular to the diagonal line intersecting the opposite corners of the package cover 130. The degassing hole 133 (and the degassing plug 134) may have a circular cross-sectional shape.

[0166] Figure 5 FIG. 2 is a vertical cross-sectional view showing a fourth alternative design of the package cover 130 according to one or more embodiments. Figure 5 As shown, in Figure 1A The two-piece unit of the package cover 130 and the reinforcement ring 150 in the original design of the fourth alternative design may replace the reinforcement ring 150 with a one-piece package cover 130 having an outer foot 130c. In particular, the package cover 130 of the fourth alternative design (e.g., the one-piece package cover 130) may include a plate portion 130p and an outer foot 130c extending from the plate portion 130p. The outer foot 130c may be integrally formed with the plate portion 130p (e.g., by a CNC process), and the outer foot 130c may protrude vertically from the plate portion 130p around the periphery of the plate portion 130p.

[0167] like Figure 5As shown in FIG. 1 , the filling hole 131 and the degassing hole 133 can be positioned on the inner side (e.g., in the x direction) of the outer foot portion 130c. Therefore, the TIM layer protection structure 170 can be formed in the space bounded by the outer foot portion 130c, the plate portion 130p, the package substrate 110, and the intermediate module 120 (and the TIM layer 140). The fourth alternative design can eliminate the step of bonding the package cover 130 to the reinforcement ring 150, and thus can be compared to the conventional design. Figure 1A The original design of the package cover 130 requires less process time.

[0168] Figure 6 FIG. 2 is a vertical cross-sectional view showing a fifth alternative design of package cover 130 according to one or more embodiments. Figure 6 As shown, the packaging cover 130 in the fifth alternative design may be similar to the fourth alternative design, but may additionally include an inner foot portion 130d. In particular, the packaging cover 130 in the fifth alternative design may include a plate portion 130p and an outer foot portion 130c integrally formed with the plate portion 130p. The outer foot portion 130c may protrude vertically from the plate portion 130p around the periphery of the plate portion 130p.

[0169] The package cover 130 in the fifth alternative design may also include an inner foot portion 130d formed inside the outer foot portion 130c. The inner foot portion 130d may protrude substantially vertically from the plate portion 130p. The inner foot portion 130d may have the same or different length as the outer foot portion 130c in the z direction. The inner foot portion 130d may also be connected to the package substrate 110 by an adhesive 160.

[0170] like Figure 6 As shown, the filling holes 131 and the degassing holes 133 can be positioned inside the inner foot portion 130d (e.g., in the x-direction). Therefore, the TIM layer protection structure 170 can be formed in the volume defined by the inner foot portion 130d, the plate portion 130p, the package substrate 110, and the intermediate module 120 (and the TIM layer 140). Figure 1A Compared to the original design of the encapsulation cover 130 in FIG. 1 , the fifth alternative design may require less material to fill the surrounding volume of the interposer module 120 and may require less time to fill the volume.

[0171] Reference Figures 1A to 6, the semiconductor package 100 may include an intermediate module 120, a thermal interface material (TIM) layer 40, a thermal interface material layer protection structure 170, and a package lid 130. The intermediate module 120 is located on the package substrate 110. The thermal interface material layer 140 is located on the intermediate module 120. The thermal interface material layer protection structure 170 is located on the side of the thermal interface material layer 140 and the side of the intermediate module 120. The package lid 130 is located on the intermediate module 120, the thermal interface material layer 140, and the thermal interface material layer protection structure 170. The ratio of the thickness of the thermal interface material layer protection structure 170 to the thickness of the intermediate module 120 may be between 1.0 and 3.0. The package cover 130 may have a package cover length L130 in the first horizontal direction, the thermal interface material layer protection structure 170 may have a thermal interface material layer protection structure length L170 in the first horizontal direction, and the ratio of the thermal interface material layer protection structure length L170 to the package cover length L130 may be between 0.3 and 1.0. The package cover 130 may have a package cover width W130 in a second horizontal direction perpendicular to the first horizontal direction, the thermal interface material layer protection structure 170 may have a thermal interface material layer protection structure width W170 in the second horizontal direction, and the ratio of the thermal interface material layer protection structure width W170 to the package cover width W130 may be between 0.3 and 1.0. The thermal expansion coefficient of the thermal interface material layer protection structure 170 may be between 3ppm / ℃ and 20ppm / ℃. The thermal conductivity of the thermal interface material layer protection structure 170 may be greater than 1W / m·K. The package cover 130 may contact the upper surface of the thermal interface material layer 140 and the upper surface of the thermal interface material layer protection structure 170. The thermal interface material layer protection structure 170 may surround the periphery of the thermal interface material layer 140. The thermal interface material layer protection structure 170 may extend across the interface between the thermal interface material layer 140 and the molding material layer 127 of the intermediate module 120. The semiconductor package 100 may further include a stiffener ring 150. The stiffener ring 150 is adhered to the package substrate 110 and is located around the intermediate module 120, wherein the thermal interface material layer protection structure 170 may be formed in a space bounded by the stiffener ring 150 and the intermediate module 120. The thermal interface material layer protection structure 170 may be bonded to the stiffener ring 150 and may extend continuously from the stiffener ring 150 to the intermediate module 120. The thermal interface material layer protection structure 170 may be bonded to the package cover 130 and the package substrate 110, and may extend continuously from the package cover 130 to the package substrate 110. The packaging cover 130 may include a filling plug 132 and a degassing plug 134 . The filling plug 132 is on the thermal interface material layer protection structure 170 , and the degassing plug 134 is on the thermal interface material layer protection structure 170 .The packaging cover 130 may include a plate portion 130p, a foot 130c and a foot 130d, the foot 130c and the foot 130d extending from the plate portion 130p and contacting the packaging substrate 110 around the periphery of the intermediate module 120, and a thermal interface material layer protection structure 170 is formed in the space between the foot 130c and the foot 130d and the intermediate module 120.

[0172] Reference Figures 1A to 6 , the method for forming the semiconductor package 100 may include: mounting the intermediate module 120 on the package substrate 110. Positioning the thermal interface material layer on the intermediate module 120. Positioning the package cover 130 on the intermediate module 120 and the thermal interface material layer 140. Forming a thermal interface material layer protection structure 170 on the side of the thermal interface material layer 140 and the side of the intermediate module 120 through the filling hole 131 in the package cover 130. The step of forming the thermal interface material layer protection structure 170 may include degassing the space (volume) between the reinforcement ring 150 and the intermediate module through the degassing hole 133 in the package cover 130. The formation method further includes: plugging the filling hole 131 on the package cover 130. Plug the degassing hole 133 on the package cover 130. The step of forming the thermal interface material layer protection structure 170 may include injecting the thermal interface material layer protection structure material into the filling hole 131 of the package cover 130 until the volume of the thermal interface material layer protection structure material 170 reaches the bottom level of the degassing hole 133. The step of forming the thermal interface material layer protection structure 170 may include injecting the thermal interface material layer protection structure material into the filling hole 131 in the package cover 130 so that the upper surface of the thermal interface material layer protection structure material contacts the bottom surface of the package cover 130 around the periphery of the thermal interface material layer 140.

[0173] Reference Figures 1A to 6, the semiconductor package 100 may include an intermediate module 120, a thermal interface material layer, a thermal interface material layer protection structure 170 and a package cover 130. The intermediate module 120 is located on the package substrate 110. The thermal interface material layer is located on the intermediate module 120. The thermal interface material layer protection structure 170 is located on the package substrate and surrounds the intermediate layer and the thermal interface material layer, wherein the thermal expansion coefficient of the thermal interface material layer protection structure 170 may be between 3ppm / ℃ and 20ppm / ℃, and the thermal conductivity of the thermal interface material layer protection structure 170 may be greater than 1W / m·K. The reinforcement ring 150 may be attached to the package substrate 110 and located around the intermediate module 120, wherein the thermal interface material layer protection structure 170 may be formed in the space defined by the reinforcement ring 150 and the intermediate module 120. The packaging cover 130 is located on the reinforcement ring 150, the intermediate module 120, the thermal interface material layer 140 and the thermal interface material layer protection structure 170, wherein the packaging cover 130 contacts the upper surface of the thermal interface material layer 140 and the upper surface of the thermal interface material layer protection structure 170. The packaging cover 130 may include a filling hole 131, a filling plug 132, a degassing hole 133 and a degassing plug 134. The filling hole 131 is located on the thermal interface material layer protection structure, and the diameter of the filling hole 131 is between 3mm and 10mm. The filling plug 132 is used to plug the filling hole 131. The degassing hole 133 is located on the thermal interface material layer protection structure 170, and the diameter of the degassing hole is between 3mm and 10mm. The degassing plug 134 is used to plug the degassing hole 133. Among them, the filling hole 131 may be located on the side of the intermediate module 120 opposite to the degassing hole 133.

[0174] The above summarizes the components of several embodiments so that those skilled in the art in the technical field to which the utility model belongs can more easily understand the concepts of the embodiments of the utility model. Those skilled in the art in the technical field to which the utility model belongs should understand that they can design or modify other processes and structures based on the embodiments of the utility model to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art in the technical field to which the utility model belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the utility model, and they can make various changes, substitutions and replacements without violating the spirit and scope of the utility model.

Claims

1. A semiconductor package, characterized in that: include: An intermediate module is located on a packaging substrate; a thermal interface material layer, located on the intermediate module; A thermal interface material layer protection structure is located on the side of the thermal interface material layer and the side of the intermediate module; as well as A packaging cover is located on the intermediate module, the thermal interface material layer and the thermal interface material layer protection structure.

2. The semiconductor package according to claim 1, wherein: The ratio of the thickness of the thermal interface material layer protection structure to the thickness of the intermediate module is between 1.0 and 3.

0.

3. The semiconductor package according to claim 1, wherein: The packaging cover has a packaging cover length in a first horizontal direction, the thermal interface material layer protection structure has a thermal interface material layer protection structure length in the first horizontal direction, and the ratio of the thermal interface material layer protection structure length to the packaging cover length is between 0.3 and 1.

0.

4. The semiconductor package according to claim 3, wherein: The packaging cover has a packaging cover width in a second horizontal direction perpendicular to the first horizontal direction, the thermal interface material layer protection structure has a thermal interface material layer protection structure width in the second horizontal direction, and the ratio of the thermal interface material layer protection structure width to the packaging cover width is between 0.3 and 1.

0.

5. The semiconductor package according to claim 1, wherein: Also includes: A reinforcement ring is adhered to the package substrate and is located around the intermediate module, wherein the thermal interface material layer protection structure is formed in the space defined by the reinforcement ring and the intermediate module.

6. The semiconductor package according to claim 5, wherein: The thermal interface material layer protection structure is joined to the reinforcement ring and continuously extends from the reinforcement ring to the intermediate module.

7. The semiconductor package according to claim 5, wherein: The thermal interface material layer protection structure is bonded to the packaging cover and the packaging substrate, and continuously extends from the packaging cover to the packaging substrate.

8. The semiconductor package according to claim 5, wherein: The packaging cover includes a filling plug and a degassing plug. The filling plug is on the thermal interface material layer protection structure, and the degassing plug is on the thermal interface material layer protection structure.

9. The semiconductor package according to any one of claims 1 to 8, wherein: The package cover includes a plate portion and a foot portion, wherein the foot portion extends from the plate portion and contacts the package substrate around the periphery of the intermediate module, and the thermal interface material layer protection structure is formed in the space between the foot portion and the intermediate module.

10. A semiconductor package, characterized in that: include: An intermediate module is located on a packaging substrate; a thermal interface material layer, located on the intermediate module; a thermal interface material layer protection structure, located on the package substrate and surrounding the intermediate module and the thermal interface material layer, wherein the thermal expansion coefficient of the thermal interface material layer protection structure is between 3ppm / °C and 20ppm / °C, and the thermal conductivity of the thermal interface material layer protection structure is greater than 1W / m·K; a reinforcement ring attached to the package substrate and located around the intermediate module, wherein the thermal interface material layer protection structure is formed in a space defined by the reinforcement ring and the intermediate module; as well as A packaging cover is located on the reinforcement ring, the intermediate module, the thermal interface material layer and the thermal interface material layer protection structure, wherein the packaging cover contacts the upper surface of the thermal interface material layer and the upper surface of the thermal interface material layer protection structure, wherein the packaging cover comprises: A filling hole is located on the thermal interface material layer protection structure, and the diameter of the filling hole is between 3 mm and 10 mm; A filling plug, used to plug the filling hole; a degassing hole located on the thermal interface material layer protection structure, and the diameter of the degassing hole is between 3 mm and 10 mm; and a degassing plug, used to plug the degassing hole, The filling hole is located at a side of the intermediate module opposite to the degassing hole.

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