Universal system middle computer testing tool

By designing an automated general-purpose system test tooling, using the cooperation of the signal detection unit and the A/D conversion module with the central processor, the problems of long test time and low accuracy in the existing technology are solved, and efficient and accurate are achieved Record and save the test results.

CN222301826UActive Publication Date: 2025-01-03TIANJIN TONGLIAN ELECTRIC CO LTD
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Patent Information

Application Number
CN202421172039.7
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-05-27
Publication Date
2025-01-03
Estimated Expiration
2034-05-27

AI Technical Summary

Technical Problem

In the prior art, the test of the general system's intermediate computer is in a semi-automated mode, with a long test time and human error, and the intermediate process cannot be recorded, and the test results are not accurate.

Method used

A test tool including upper computer and general system central computer testing module is designed, and the A/D conversion module and the central processor are passed through a signal detection unit (analog signal, square wave signal, sine wave signal, differential signal detection unit). The connection enables automated signal detection and data processing, and records and saves test results.

Benefits of technology

The test time is shortened, human error is eliminated, and the test results are fully recorded and automatically saved in the intermediate test process.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a universal system middle computer testing tool, which comprises an upper computer and a universal system middle computer testing module which correspond to each other, the upper computer is electrically connected with a central processing unit, and the output end of the central processing unit is connected with the input end of a universal system middle computer needing to be detected. A corresponding detection point is reserved on the universal system middle computer needing to be detected, the detection point of the universal system middle computer needing to be detected is in contact with a probe reserved by the signal detection unit, and the signal detection unit comprises an analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit and a differential signal detection unit. The signal output end of the signal detection unit is electrically connected with the input end of the A / D conversion module, the output end of the A / D conversion module is electrically connected with the central processing unit, and the signal detection unit converts analog signals into digital signals through the A / D conversion module and transmits the digital signals to the central processing unit. The central processing unit processes the received signals and then feeds the signals back to the upper computer.
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Description

Technical Field

[0001] The utility model belongs to the technical field of universal system host computer detection, and relates to a universal system host computer testing tool. Background Art

[0002] In the prior art, the general system host computer is used in the general system to collect the information of the equipment along the line and upload it to the general system host computer, and send the control instructions from the general system host computer to the equipment along the line, so as to ensure the normal operation of the general system. The general system host computer is a very important module when it is used, so the general system host computer needs to be tested before use, and the testing technology of the general system host computer in the prior art is a semi-automatic mode. The testing instrument in the prior art can only complete simple short circuit and open circuit tests in the general system host computer; the function and performance test of the general system host computer can only be completed manually. The shortcomings of this testing method are that the test time is long, there are human testing errors, the intermediate test process cannot be recorded, the test results are recorded by hand by the test personnel, etc., and the accuracy of the test results is not high. Summary of the invention

[0003] In view of this, the purpose of the utility model is to provide a more convenient, intuitive and accurate universal system host computer testing tool.

[0004] In order to achieve the above object, the utility model provides the following technical solutions:

[0005] A universal system host computer test tool comprises a corresponding host computer and a universal system host computer test module, wherein the host computer is electrically connected to a central processing unit, the output end of the central processing unit is connected to the input end of a universal system host computer to be tested, the universal system host computer to be tested has a corresponding test point, the test point of the universal system host computer to be tested contacts with a probe reserved by a signal detection unit, the signal detection unit comprises an analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit and a differential signal detection unit, the signal output ends of the analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit and the differential signal detection unit are electrically connected to the input end of an A / D conversion module respectively, the output end of the A / D conversion module is electrically connected to the central processing unit, the signal detection unit converts analog signals into digital signals through the A / D conversion module respectively, and transmits the signals to the central processing unit, the central processing unit processes the received signals and then feeds them back to the host computer, and the host computer displays the signals.

[0006] Further, the sine wave signal detection unit includes a dual-channel operational amplifier U32, wherein pin 4 of the dual-channel operational amplifier U32 is connected to one end of a capacitor C96, the other end of the capacitor C96 is connected to pin 5 of the dual-channel operational amplifier U32 and one end of a resistor R285, the other end of the resistor R285 is connected to one end of a capacitor C102, the other end of the capacitor C102 is connected to one end of a resistor R286, pins 6 and 7 of the dual-channel operational amplifier U32, and one end of a capacitor C98; the other end of the resistor R286 is connected to the input terminal IN; the other end of the capacitor C98 is connected to one end of a resistor R289, the base of a transistor Q53, and one end of a resistor R288; the other end of the resistor R289 is connected to a power supply DVCC; the other end of the resistor R288 is connected to One end of the resistor R287 and the emitter of the transistor Q58 are connected to the ground GND; the other end of the resistor R287 is connected to the emitter of the transistor Q53; the collector of the transistor Q53 is connected to one end of the resistor R296, the other end of the resistor R296 is connected to the base of the transistor Q58, the collector of the transistor Q58 outputs a signal, and the collector of the transistor Q58 is also connected to one end of the resistor R295, one end of the capacitor C99, and one end of the resistor R290; the other end of the resistor R290 is connected to one end of the capacitor C101, the other end of the capacitor C101 is connected to the other end of the capacitor C99 and the other end of the resistor R295; the pin 8 of the dual-channel operational amplifier U32 is connected to one end of the capacitor C97, and the other end of the capacitor C97 is grounded GND.

[0007] Further, the differential signal detection unit includes a bus communication isolation module U27, pin 1 of the bus communication isolation module U27 is connected to a 3.3V power supply; pin 2 of the bus communication isolation module U27 is grounded; pin 3 of the bus communication isolation module U27 is a signal input terminal IN1; the cathode terminal of the diode D15 is connected to one end of the capacitor C68 and the anode terminal of the diode D17; the cathode terminal of the diode D17 is connected to the anode terminal of the diode D18; the cathode terminal of the diode D18 is connected to the anode terminal of the diode D19; the cathode terminal of the diode D19 is connected to the anode terminal of the diode D20, and the cathode terminal of the diode D20 is connected to pin 3 of the bus communication isolation module U27;

[0008] Pin 4 of the bus communication isolation module U27 is the signal input terminal IN2, the positive terminal of the diode D5 is connected to one end of the capacitor C8 and the negative terminal of the diode D7; the positive terminal of the diode D7 is connected to the negative terminal of the diode D8; the positive terminal of the diode D8 is connected to the negative terminal of the diode D9; the positive terminal of the diode D9 is connected to the negative terminal of the diode 1, and the positive terminal of the diode D10 is connected to pin 4 of the bus communication isolation module U27;

[0009] Pin 5 of the bus communication isolation module U27 is connected to one end of the resistor R147; the other end of the resistor R147 is connected to one end of the resistor R148 and then grounded GND; the other end of the resistor R148 is connected to pin 6 of the bus communication isolation module U27; pins 11 and 10 of the bus communication isolation module U27 output differential signals to the A / D conversion module.

[0010] Furthermore, the analog signal detection unit includes a relay J1, a relay J2, and a relay J3 connected to each other and related peripheral circuits.

[0011] Furthermore, the square wave signal detection unit includes a multi-channel comparator U15 and a multi-channel comparator U17 connected to each other and related peripheral circuits.

[0012] The beneficial effects of the utility model are:

[0013] The utility model can shorten the test time, improve the test efficiency, eliminate the human test error, completely record the intermediate test process, and automatically save the test result. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the accompanying drawings:

[0015] Figure 1 This is a working principle diagram of an embodiment of the utility model;

[0016] Figure 2 A circuit diagram of an analog signal detection unit according to an embodiment of the present utility model;

[0017] Figure 3 A circuit diagram of a square wave signal detection unit according to an embodiment of the present utility model;

[0018] Figure 4 A circuit diagram of a sine wave signal detection unit according to an embodiment of the present utility model;

[0019] Figure 5 This is a circuit diagram of a differential signal detection unit according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0021] In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0022] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0024] like Figure 1 As shown, a universal system host computer test tool includes a corresponding host computer and a universal system host computer test module, the host computer is electrically connected to the central processing unit, the output end of the central processing unit is connected to the input end of the universal system host computer to be detected, the universal system host computer to be detected has a corresponding detection point, the detection point of the universal system host computer to be detected is in contact with the metal probe reserved by the signal detection unit, and the signal detection unit includes an analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit and a differential signal detection unit. The signal output ends of the analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit and the differential signal detection unit are respectively electrically connected to the input end of the A / D conversion module, and the output end of the A / D conversion module is electrically connected to the central processing unit. The analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit and the differential signal detection unit convert the analog signal into a digital signal through the A / D conversion module, and transmit it to the central processing unit. The central processing unit processes the received signal and then feeds it back to the host computer, and the host computer displays it.

[0025] like Figure 2 As shown, the analog signal detection unit includes a relay J1, a resistor R152 and a resistor R267 in parallel, a pin 4 of the relay J1 is connected to one end of the resistor R152 and the resistor R267 in parallel, a resistor R5 and a resistor R268 are connected in parallel, the other end of the resistor R152 and the resistor R267 in parallel is connected to one end of the resistor R5 and the resistor R268 in parallel, the other end of the resistor R5 and the resistor R268 in parallel is connected to the pin 4 of the relay J2 and one end of the resistor R32, and the other end of the resistor R32 is connected to the pin 5 of the relay J2 and then grounded GND.

[0026] Pin 3 of relay J1 is connected to power supply VDD, pin 6 of relay J1 is connected to pin REF, and pin 1 of relay J1 is connected to 5V power supply. Resistor R265 is connected in parallel with resistor R151, pin 5 of relay J1 is connected to one end of resistor R265 and resistor R151 connected in parallel, resistor R74 is connected in parallel with resistor R266, the other end of resistor R265 and resistor R151 connected in parallel is connected to one end of resistor R74 and resistor R266 connected in parallel, the other end of resistor R74 and resistor R266 connected in parallel is connected to pin 4 of relay J3 and one end of resistor R33, and the other end of resistor R33 is connected to pin 5 of relay J3. Pin 3 and pin 6 of relay J3 are connected to pin 3 and pin 6 of relay J2 respectively.

[0027] Pin 8 of relay J1 is connected to the anode of diode D1 and then to one end of the collector of transistor Q3. The emitter of transistor Q3 is grounded GND. The base of transistor Q3 is connected to one end of resistor R20. The other end of resistor R20 is connected to pin P-ON.

[0028] Pin 8 of relay J3 is connected to the positive electrode of diode D6 and then to one end of the collector of transistor Q6. The emitter of transistor Q6 is grounded GND. The base of transistor Q6 is connected to one end of resistor R47. The other end of resistor R47 is connected to pin A2. Pin A2 is the input port of the analog signal detection unit. The analog signal to be measured of the host computer of the general system is output and input to the analog signal detection unit from pin A2. The negative electrode of diode D6 is connected to pin 1 of relay J3 and then outputs the analog signal to the A / D conversion module.

[0029] like Figure 3As shown, the square wave signal detection unit includes a multi-way comparator U15 and a multi-way comparator U17, wherein the pin 5 of the multi-way comparator U15 is connected to the pin 2 of the multi-way comparator U15, one end of the capacitor C66, and the pin 5 of the multi-way comparator U17, and the pin 4 of the multi-way comparator U15 is connected to the other end of the capacitor C66 and the pin 3 of the multi-way comparator U17. The pin 2 of the multi-way comparator U15 is also connected to one end of the capacitor C67 and then connected to the ground GND. The other end of the capacitor C67 is connected to the pin 3 of the multi-way comparator U15 and then connected to a power supply of 3.3V voltage.

[0030] Pins 1 and 2 of the multi-way comparator U17 are connected to one end of a resistor R121, and the other end of the resistor R121 is connected to the non-inverting input of the operational amplifier U8.4. Pin 4 of the multi-channel comparator U17 is connected to one end of the capacitor C70 and then to the voltage of a 3.3V power supply. The other end of the capacitor C70 is connected to one end of a resistor R118. The other end of the resistor R118 is connected to the inverting input end of the operational amplifier U8.4, the capacitor C75, and one end of the resistor R109. The other ends of the capacitor C75 and the resistor R109 are connected and then to the output end of the operational amplifier U8.4 and one end of the resistor R119. The other end of the resistor R119 is connected to the base of the transistor Q20. The collector of the transistor Q20 is connected to the output port out. The emitter of the transistor Q20 is connected to one end of a resistor R123. The other end of the resistor R123 is connected to the positive electrode of the diode D53, one end of the resistor R143, and the output end of the operational amplifier U4.1. The negative electrode of the diode D53 and the other end of the resistor R143 are connected and then to a 3.3V power supply.

[0031] The positive power supply terminal of the operational amplifier U4.1 is connected to one end of the resistor R140 and one end of the capacitor C10 and then to a 5V power supply; the other end of the capacitor C10 is grounded GND; the other end of the resistor R140 is connected to the inverting input terminal of the operational amplifier U4.1 and one end of the resistor R142 and then to grounded GND; the other end of the resistor R142 is connected to the negative power supply terminal of the operational amplifier U4.1 and one end of the resistor R141 and then to grounded GND; the other end of the resistor R141 is connected to the non-inverting input terminal of the operational amplifier U4.1 and then to pin A1, pin A1 is the input of the square wave signal detection unit, and the output signal pin of the host computer of the general system is connected to pin A1.

[0032] The output end of the operational amplifier U4.2 is connected to one end of the resistor R154 and the positive electrode of the diode D52, and then the output end outputs a square wave signal to the A / D conversion module; the other end of the resistor R154 and the negative electrode of the diode D52 are connected and then connected to a 3.3V power supply. The non-inverting input end of the operational amplifier U4.2 is connected to one end of the resistor R153, and the other end of the resistor R153 is connected to the reverse input end of the operational amplifier U4.1 and then grounded GND.

[0033] like Figure 4 As shown, the sine wave signal detection unit includes a dual-channel operational amplifier U32, pin 4 of the dual-channel operational amplifier U32 is connected to one end of a capacitor C96, the other end of the capacitor C96 is connected to pin 5 of the dual-channel operational amplifier U32 and one end of a resistor R285, the other end of the resistor R285 is connected to one end of a capacitor C102, the other end of the capacitor C102 is connected to one end of a resistor R286, pins 6 and 7 of the dual-channel operational amplifier U32, and one end of a capacitor C98; the other end of the resistor R286 is connected to the input terminal IN, and the sine wave output pin of the universal system host is connected to the input terminal IN; the other end of the capacitor C98 is connected to one end of a resistor R289, the base of a transistor Q53, and one end of a resistor R288; the other end of the resistor R289 is connected to a power supply DVCC; The other end of resistor R288 is connected to one end of resistor R287 and the emitter of transistor Q58 and then grounded GND; the other end of resistor R287 is connected to the emitter of transistor Q53; the collector of transistor Q53 is connected to one end of resistor R296, the other end of resistor R296 is connected to the base of transistor Q58, the collector of transistor Q58 outputs a signal, and the collector of transistor Q58 is also connected to one end of resistor R295, one end of capacitor C99, and one end of resistor R290; the other end of resistor R290 is connected to one end of capacitor C101, the other end of capacitor C101 is connected to the other end of capacitor C99 and the other end of resistor R295; pin 8 of dual-channel operational amplifier U32 is connected to one end of capacitor C97, and the other end of capacitor C97 is grounded GND.

[0034] like Figure 5 As shown, the differential signal detection unit includes a bus communication isolation module U27, and pin 1 of the bus communication isolation module U27 is connected to a 3.3V power supply; pin 2 of the bus communication isolation module U27 is grounded; pin 3 of the bus communication isolation module U27 is a signal input terminal IN1; the cathode terminal of the diode D15 is connected to one end of the capacitor C68 and the positive terminal of the diode D17, and the other end of the capacitor C68 is the input end of the differential signal detection unit, and the other end of the capacitor C68 is connected to the differential signal of the board under test through the probe on the needle bed board; the cathode terminal of the diode D17 is connected to the positive terminal of the diode D18; the cathode terminal of the diode D18 is connected to the positive terminal of the diode D19; the cathode terminal of the diode D19 is connected to the positive terminal of the diode D20, and the cathode terminal of the diode D20 is connected to pin 3 of the bus communication isolation module U27.

[0035] Pin 4 of the bus communication isolation module U27 is the signal input terminal IN2, the positive terminal of the diode D5 is connected to one end of the capacitor C8 and the negative terminal of the diode D7; the other end of the capacitor C8 is the input port of the differential signal detection unit, and the other end of the capacitor C8 is connected to the differential signal of the board under test through the probe on the needle bed board, the positive terminal of the diode D7 is connected to the negative terminal of the diode D8; the positive terminal of the diode D8 is connected to the negative terminal of the diode D9; the positive terminal of the diode D9 is connected to the negative terminal of the diode 1, and the positive terminal of the diode D10 is connected to pin 4 of the bus communication isolation module U27.

[0036] Pin 5 of the bus communication isolation module U27 is connected to one end of the resistor R147; the other end of the resistor R147 is connected to one end of the resistor R148 and then grounded GND; the other end of the resistor R148 is connected to pin 6 of the bus communication isolation module U27; pins 11 and 10 of the bus communication isolation module U27 output differential signals to the A / D conversion module.

[0037] The working principle of this utility model:

[0038] The general system host computer test tooling mainly completes the test of the overall function of the general system host computer. The output of each functional module of the general system host computer has corresponding test points, which are connected to the corresponding signal detection unit of the general system host computer test module through metal probes. The tester operates the host computer and sends the "start test" command to the general system host computer test module. After receiving the command, the general system host computer test module starts the test. The entire test process is mainly controlled by the central processing unit. The central processing unit sets the detection timing and starts each signal detection unit in steps. After the signal detection unit is started, it starts to detect the output signal of the corresponding functional module in the general system host computer. After the detection is completed, the signal is converted into a digital quantity through the A / D conversion module and transmitted to the central processing unit. After all functional tests are completed, the central processing unit sends the test results to the host computer. The host computer displays and saves the test results.

[0039] Some signal detection results are provided below.

[0040] The results of the analog signal detection are shown in Table 1.

[0041] Table 1

[0042]

[0043]

[0044] The square wave signal detection results are shown in Table 2

[0045] Table 2

[0046]

[0047] The results of the sine wave signal detection are shown in Table 3.

[0048] Table 3

[0049]

[0050]

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A universal system host computer test tool, characterized by: The invention comprises a corresponding host computer and a universal system host computer test module. The host computer is electrically connected to a central processing unit. The output end of the central processing unit is connected to the input end of a universal system host computer to be detected. The universal system host computer to be detected has a corresponding detection point. The detection point of the universal system host computer to be detected contacts with a probe reserved by a signal detection unit. The signal detection unit comprises an analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit and a differential signal detection unit. The signal output ends of the analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit and the differential signal detection unit are electrically connected to the input end of an A / D conversion module respectively. The output end of the A / D conversion module is electrically connected to the central processing unit. The signal detection unit converts the analog signal into a digital signal through the A / D conversion module and transmits it to the central processing unit. The central processing unit processes the received signal and then feeds it back to the host computer, and the host computer displays it.

2. The universal system host machine test tool according to claim 1, characterized in that: The sine wave signal detection unit includes a dual-channel operational amplifier U32, wherein pin 4 of the dual-channel operational amplifier U32 is connected to one end of a capacitor C96, the other end of the capacitor C96 is connected to pin 5 of the dual-channel operational amplifier U32 and one end of a resistor R285, the other end of the resistor R285 is connected to one end of a capacitor C102, the other end of the capacitor C102 is connected to one end of a resistor R286, pins 6 and 7 of the dual-channel operational amplifier U32, and one end of a capacitor C98; the other end of the resistor R286 is connected to the input terminal IN; the other end of the capacitor C98 is connected to one end of a resistor R289, the base of a transistor Q53, and one end of a resistor R288; the other end of the resistor R289 is connected to a power supply DVCC; the other end of the resistor R288 is connected to a resistor One end of R287 and the emitter of transistor Q58 are connected and then grounded to GND; the other end of resistor R287 is connected to the emitter of transistor Q53; the collector of transistor Q53 is connected to one end of resistor R296, the other end of resistor R296 is connected to the base of transistor Q58, the collector of transistor Q58 outputs a signal, and the collector of transistor Q58 is also connected to one end of resistor R295, one end of capacitor C99, and one end of resistor R290; the other end of resistor R290 is connected to one end of capacitor C101, the other end of capacitor C101 is connected to the other end of capacitor C99 and the other end of resistor R295; pin 8 of the dual-channel operational amplifier U32 is connected to one end of capacitor C97, and the other end of capacitor C97 is grounded to GND.

3. The universal system host machine test tool according to claim 1, characterized in that: The differential signal detection unit includes a bus communication isolation module U27, wherein pin 1 of the bus communication isolation module U27 is connected to a 3.3V power supply; pin 2 of the bus communication isolation module U27 is grounded; pin 3 of the bus communication isolation module U27 is a signal input terminal IN1; the cathode terminal of the diode D15 is connected to one end of the capacitor C68 and the anode terminal of the diode D17; the cathode terminal of the diode D17 is connected to the anode terminal of the diode D18; the cathode terminal of the diode D18 is connected to the anode terminal of the diode D19; the cathode terminal of the diode D19 is connected to the anode terminal of the diode D20, and the cathode terminal of the diode D20 is connected to pin 3 of the bus communication isolation module U27; Pin 4 of the bus communication isolation module U27 is the signal input terminal IN2, the positive terminal of the diode D5 is connected to one end of the capacitor C8 and the negative terminal of the diode D7; the positive terminal of the diode D7 is connected to the negative terminal of the diode D8; the positive terminal of the diode D8 is connected to the negative terminal of the diode D9; the positive terminal of the diode D9 is connected to the negative terminal of the diode 1, and the positive terminal of the diode D10 is connected to pin 4 of the bus communication isolation module U27; Pin 5 of the bus communication isolation module U27 is connected to one end of the resistor R147; the other end of the resistor R147 is connected to one end of the resistor R148 and then grounded GND; the other end of the resistor R148 is connected to pin 6 of the bus communication isolation module U27; pins 11 and 10 of the bus communication isolation module U27 output differential signals to the A / D conversion module.

4. The universal system host machine test tool according to claim 1, characterized in that: The analog signal detection unit includes a relay J1, a relay J2, and a relay J3 which are connected to each other and related peripheral circuits.

5. The universal system host machine test tool according to claim 1, characterized in that: The square wave signal detection unit includes a multi-channel comparator U15 and a multi-channel comparator U17 connected to each other and related peripheral circuits.