Integrated circuit device

Abstract

An integrated circuit device includes a plurality of static random access memory (SRAM) cells, a first bit line, a capacitor, a write driver transistor and a negative voltage generator circuit. The first bit line is coupled to one row of the plurality of SRAM cells, wherein the first bit line extends substantially along a first direction. The capacitor includes a first electrode and a second electrode spaced apart from the first electrode. In a top view, the first electrode has at least one first metal line substantially extending along the first direction, and a length of the at least one first metal line is less than a length of the first bit line. The write driver transistor is coupled between the first bit line and the first electrode of the capacitor. The negative voltage generator circuit is coupled to the second electrode of the capacitor.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to integrated circuit devices. Background Art

[0002] One type of integrated circuit memory is a static random access memory (SRAM) device. An SRAM memory device includes an array of bit cells, wherein each bit cell has six transistors connected between an upper reference potential and a lower reference potential. Each bit cell has two storage nodes where information can be stored. The first node stores the desired information, while the supplementary information is stored at the second storage node. SRAM cells have the advantageous feature of retaining data without the need for refreshing. Utility Model Content

[0003] According to some embodiments of the present invention, an integrated circuit device includes a plurality of static random access memory (SRAM) cells, a first bit line, a capacitor, a write driver transistor, and a negative voltage generator circuit. The first bit line is coupled to a row of the SRAM cells, wherein the first bit line substantially extends along a first direction. The capacitor includes a first electrode and a second electrode spaced apart from the first electrode. In a top view, the first electrode has at least one first metal line substantially extending along the first direction, and the length of at least one first metal line is less than the length of the first bit line. The write driver transistor is coupled between the first bit line and the first electrode of the capacitor. The negative voltage generator circuit is coupled to the second electrode of the capacitor.

[0004] According to some embodiments of the present invention, an integrated circuit device includes: a first static random access memory (SRAM) cell, a second static random access memory cell, and a third static random access memory cell arranged in sequence substantially along a first direction in a top view; a first bit line coupled to the first SRAM cell to the third SRAM cell, wherein in the top view, the first bit line substantially extends along the first direction and overlaps with the first SRAM cell to the third SRAM cell; a capacitor including a first electrode and a second electrode spaced apart from the first electrode, wherein in the top view, the first electrode has at least one first metal line extending substantially along the first direction and overlapping with the first SRAM cell and the second SRAM cell, and the third SRAM cell does not overlap with the at least one first metal line; and a write driver transistor coupled between the first bit line and the first electrode of the capacitor, wherein the second electrode of the capacitor is coupled to a negative voltage level.

[0005] According to some embodiments of the present invention, an integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate; a static random access memory cell and a write driver transistor, which are located above the semiconductor substrate; a front-side interconnect structure, which is located above the static random access memory cell and the write driver transistor, wherein the front-side interconnect structure includes a bit line coupled to the static random access memory cell, wherein the bit line substantially extends along a first direction, wherein the bit line is electrically coupled between the static random access memory cell and the write driver transistor; and a back-side interconnect structure, which is located on a back side of the write driver transistor, wherein in a top view, one of the front-side interconnect structure and the back-side interconnect structure includes a first metal line electrically coupled to the write driver transistor and a second metal line adjacent to the first metal line, wherein the first metal line and the second metal line substantially extend along the first direction, and a length of the first metal line is less than a length of the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present invention can be best understood when reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figure 1 is a schematic circuit diagram of an integrated circuit device according to some embodiments of the present utility model;

[0008] Figure 2 is a schematic top view of an integrated circuit device according to some embodiments of the present invention;

[0009] Figure 3 is a schematic top view of an integrated circuit device according to some embodiments of the present invention;

[0010] Figure 4 is a schematic top view of an integrated circuit device according to some embodiments of the present invention;

[0011] Figure 5 is a schematic top view of an integrated circuit device according to some embodiments of the present invention;

[0012] Figures 6 to 9 Methods for making integrated circuit devices according to some embodiments of the present invention are described;

[0013] Fig.10 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0014] Fig.11is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0015] Fig.12 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0016] Fig.13 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0017] Fig.14 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0018] Fig.15 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0019] Fig.16 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention;

[0020] Fig.17 is an exemplary layout of a static random access memory (SRAM) cell according to some embodiments of the present invention.

[0021]

Explanation of symbols

[0022] 100: Integrated circuit device

[0023] 110:Semiconductor substrate

[0024] 120:SRAM cell

[0025] 120C: Cell Boundary

[0026] 122: Inverter

[0027] 124: Inverter

[0028] 130: Pull-down circuit

[0029] 132: Negative voltage generator circuit

[0030] 140: Pull-down circuit capacitor

[0031] 140L, L1: Length

[0032] 142: Electrode

[0033] 142a, 142b, 144a, 144b, BM11, BM12, M01, M02, M21, M22, M23, M41, M42: metal wire

[0034] 144: Electrode

[0035] 146: Dielectric Materials

[0036] BL, BLB: bit line

[0037] BM1, BM2, M0~M4: metallization layer

[0038] BMLI: Backside Interconnection

[0039] BV1: Conductive Via

[0040] CP: Contact Plug

[0041] DE:Device

[0042] DEL: Device layer

[0043] DL1: ILD layer

[0044] FMLI: Interconnection Structure

[0045] GS: Gate Structure

[0046] NVSS: Negative voltage level

[0047] OD: Active Zone

[0048] P1, P2: Current path

[0049] PD1, PD2: Pull-down transistors

[0050] PG1, PG2: Pass-gate transistors

[0051] PU1, PU2: Pull-up transistors

[0052] Q, QB: Node

[0053] SD: Source / Drain Region

[0054] SI:STI area

[0055] SP: Spacer

[0056] T7, T8: Transistor

[0057] TV: Conductive perforation

[0058] V1~V4: Conductive vias

[0059] VDD: Node

[0060] VSS:Node

[0061] WC, WT: control signal

[0062] WL: Character Line

[0063] X, Y, Z: direction DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of components and configurations described below are for simplifying the utility model. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the utility model may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0065] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0066] The present invention provides a process for improving the operation of a memory device (e.g., a static random access memory (SRAM)) by providing a pull-down circuit that pulls down the voltage of a ground voltage node (also referred to as node VSS) of the memory device to below the ground voltage via capacitive coupling.

[0067] Figure 1 1 is a schematic circuit diagram of an integrated circuit device 100 according to some embodiments of the present invention. For illustration purposes, the integrated circuit device 100 includes an array of static random access memory (SRAM) cells 120 and pull-down circuits 130. The pull-down circuits 130 are respectively coupled to rows of the SRAM cells 120. In some embodiments, the SRAM cells 120 are arranged in rows and columns in the memory cell array (not shown in the figure). For illustration purposes, Figure 1 Only two SRAM cells 120 coupled to the bit lines BL and BLB to receive the bit line signals are illustrated. A different number of SRAM cells 120 is within the contemplated scope of the present invention.

[0068] In some embodiments, the SRAM cell 120 includes pull-up transistors PU1 and PU2 as p-type Metal-Oxide-Semiconductor (PMOS) transistors and pull-down transistors PD1 and PD2 as n-type Metal-Oxide-Semiconductor (NMOS) transistors and pass-gate transistors PG1 and PG2. The gates of the pass-gate transistors PG1 and PG2 are controlled by a word line WL that determines whether the SRAM cell 120 is selected. The latch formed by the pull-up transistors PU1 and PU2 and the pull-down transistors PD1 and PD2 stores a bit, wherein the complementary value of the bit is stored in the storage data node Q and the storage data node QB. The stored bit can be written into or read from the SRAM cell 120 via the complementary bit lines including the bit line BL and the bit line BLB. The SRAM cell 120 is powered via a positive power supply node VDD having a positive power supply voltage. The SRAM cell 120 is also connected to a power supply voltage node VSS, which may be electrically grounded. Transistors PU1 and PD1 form a first inverter 122. Transistors PU2 and PD2 form a second inverter 124. The first inverter 122 and the second inverter 124 are cross-latched. For example, an input of the first inverter 122 (e.g., the gates of transistors PU1 and PD1) is connected to an output of the second inverter 124 (e.g., the drains of transistors PU2 and PD2), and an output of the first inverter 122 (e.g., the drains of transistors PU1 and PD1) is connected to an input of the second inverter 124 (e.g., the gates of transistors PU2 and PD2). The input of the first inverter 122 is also connected to transistor PG2. The output of the first inverter 122 is also connected to transistor PG1.

[0069] The sources of the pull-up transistors PU1 and PU2 are connected to the positive power supply node VDD. The sources of the pull-down transistors PD1 and PD2 are connected to the power supply voltage node VSS. The gates of the transistors PU1 and PD1 are connected to the drains of the transistors PU2 and PD2, which form a connection node called the storage data node QB. The gates of the transistors PU2 and PD2 are connected to the drains of the transistors PU1 and PD1, which are called the storage data node Q. The source / drain region of the pass gate transistor PG1 is connected to the bit line BL. The source / drain region of the pass gate transistor PG2 is connected to the bit line BLB. To illustrate the operation, a data latch including an inverter 122 and an inverter 124 is capable of storing data bits at a node Q. For illustration purposes, the voltage level on the node Q can be configured at different voltage levels. The voltage level of the node Q represents a logic "1" or a logic "0" corresponding to the logic data stored in the SRAM cell 120. The node QB has a logic level opposite to the logic level of the node Q. For convenience of explanation in the following description, logic "0" indicates a low level, and logic "1" indicates a high level. These indications are given for illustrative purposes.

[0070] The word line WL is used to select and trigger at least one of the SRAM cells 120 for write / read operations of the integrated circuit device 100. When the SRAM cell 120 is not selected in response to the corresponding word line signal, the SRAM cell 120 maintains the same voltage level on the node Q and the node QB.

[0071] In some embodiments, the pull-down circuit 130 is used to provide a negative voltage to the bit lines BL and BLB for assisting the write operation of the SRAM cell 120. For example, during the write operation of the SRAM cell 120, the voltage stored in the node QB is pulled down via the current path P1, and thus, the node QB is written as a logic "0". In order to enhance the write capability of the SRAM cell 120, during the write operation, the pull-down circuit 130 is used to provide a negative voltage to the bit line BLB so as to increase the voltage difference between the node QB and the bit line BLB, and thus enhance the discharge capability achieved via the current path P1, so that the node QB is efficiently written as a logic "0". As mentioned above, because the discharge capability from the node QB to the bit line BLB is enhanced in response to the negative voltage being provided to the bit line BLB, the write capability of the SRAM cell 120 is improved.

[0072] In some embodiments, the integrated circuit device 100 includes a write driver transistor T7 and a write driver transistor T8. The write driver transistor T7 is coupled between the pull-down circuit 130 and the bit line BL, and the write driver transistor T8 is coupled between the pull-down circuit 130 and the bit line BLB. To illustrate the operation, the write driver transistor T7 is used to transmit the negative voltage provided by the pull-down circuit 130 to the bit line BL in response to the control signal WC. The write driver transistor T8 is used to transmit the negative voltage provided by the pull-down circuit 130 to the bit line BLB in response to the control signal WT.

[0073] In some embodiments, the pull-down circuit 130 is also used to pull down the high voltage of the node VDD provided to the inverter 122 and the inverter 124. For example, during a write operation of the SRAM cell 120, the pull-down circuit 130 is used to pull down the high voltage of the node VDD provided to the inverter 122 and the inverter 124, and the charging capability achieved through the current path P2 is reduced. Since the charging capability achieved through the current path P2 is reduced, the SRAM cell 120 saves power during the write operation, thereby reducing the power consumption of the SRAM cell 120. In some embodiments, the pull-down circuit 130 is used to pull down the voltage stored in the node QB and the voltage independently provided to the inverter 122 and the inverter 124. In some other embodiments, the pull-down circuit 130 is used to pull down the voltage stored in the node QB and the second voltage provided to the inverter 122 and the inverter 124 at the same time.

[0074] Each of the pull-down circuits 130 may include a pull-down circuit capacitor 140. The pull-down circuit capacitor 140 may have a first electrode 142, a second electrode 144, and a dielectric material 146 located between the first electrode 142 and the second electrode 144. The first electrode 142 (also referred to as the first node of the pull-down circuit capacitor 140) may be connected to the bit lines BL and BLB via write driver transistors T7 and T8. The second electrode 144 may be coupled to a negative voltage level NVSS. In some embodiments, the negative voltage level NVSS is approximately equal to the voltage level of the node VDD. For example, the pull-down circuit 130 may include a negative voltage generator circuit 132 that provides the negative voltage level NVSS to the second electrode 144. The pull-down circuit 130 may also be referred to as a write assist circuit. The pull-down circuit capacitors 140 coupled to different rows (i.e., different bit lines BL / BLB) of the SRAM cell 120 may be electrically isolated from each other.

[0075] Figure 2is a schematic top view of an integrated circuit device 100 according to some embodiments of the present invention. An SRAM cell 120 may be formed above a semiconductor substrate 110. For example, the six transistors of the SRAM cell 120 are planar transistors or non-planar transistors (e.g., fin field-effect-transistor (FinFET) or gate-all-around (GAA) transistors) formed above the semiconductor substrate 110. The FinFET has an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). A GAA transistor (e.g., a nanosheet transistor or a nanowire transistor) has a gate structure that may extend partially or completely around a channel region to provide access to the channel region on two or more sides. In Figure 2 , seven SRAM cells 120 are illustratively illustrated in a row. Different numbers of SRAM cells 120 are within the contemplated scope of the present invention. The integrated circuit device 100 includes bit lines BL and BLB and word lines WL, and each of the SRAM cells is coupled to a bit line BL, a bit line BLB, and a word line WL. The bit lines BL and BLB may extend along a direction Y, and the word line WL may extend along a direction X that intersects the direction Y. For example, the direction Y is orthogonal to the direction X.

[0076] In some embodiments, the pull-down circuit capacitor 140 may be a coupling capacitor having a plurality of metal lines / conductors or a plurality of plates disposed parallel to each other. For example, the first electrode 142 includes two metal parallel lines (e.g., metal lines 142a and 142b) electrically connected to each other, and the second electrode 144 includes two metal parallel lines (e.g., metal lines 144a and 144b) interlaced with the metal lines of the first electrode 142. It should be noted that the number of metal parallel lines may vary according to device requirements, such as the size of the SRAM cell 120. For example, the number of metal parallel lines of the first electrode 142 may be in the range of about 1 to about 10, and the number of metal parallel lines of the second electrode 144 may be in the range of about 1 to about 10. The metal lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 may extend substantially along a direction (e.g., direction Y) parallel to the direction of the bit lines BL and BLB. With this configuration, the lengths of the metal lines of the first electrode 142 and the second electrode 144 can be adjusted according to the lengths of the bit lines BL and BLB, thereby mitigating the variation of the coupling NBL level with various bit line lengths.

[0077] In some embodiments of the present invention, the length 140L of the metal parallel lines (e.g., metal lines 142a, 142b, 144a, 144b) of the first electrode 142 and the second electrode 144 along the direction Y may be less than the length L1 of the bit lines BL and BLB along the direction Y. In some embodiments, the ratio of the length 140L to the length L1 may be in the range of about 0.1 to about 0.9. In some examples, the ratio of the length 140L to the length L1 may be in the range of about 0.1 to about 0.4, such as about 0.25. In some examples, the ratio of the length 140L to the length L1 may be in the range of about 0.4 to about 0.6, such as about 0.5. In some examples, the ratio of the length 140L to the length L1 may be in the range of about 0.6 to about 0.9, such as about 0.75. By reducing the length of the metal capacitor (e.g., the first electrode 142 and the second electrode 144), the overlap area between the bit line and the metal capacitor can be reduced, thereby solving the resistance and capacitance (RC) problem, which in turn will increase / reduce the write power due to the resistance and capacitance (RC) effect. In addition, by increasing the number of metal capacitor lines (e.g., metal lines 142a, 142b, 144a, 144b), capacitive coupling can be maintained.

[0078] In some embodiments of the present invention, by reducing the length of the metal wires of the electrodes 142 / 144, the number of SRAM cells 120 overlapping with one of the metal wires of the electrodes 142 / 144 (e.g., metal wires 142a, 142b, 144a, 144b) is less than the number of SRAM cells overlapping with one of the bit lines BL and BLB. Figure 2 , the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b) overlap four SRAM cells 120, while the bit lines BL and BLB overlap seven SRAM cells 120. In other words, the bit lines BL and BLB overlap all SRAM cells 120 in the same row, while the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b) overlap a portion of the SRAM cells 120 in the same row, and leave the other portions of the SRAM cells 120 in the same row not overlapped with the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b). In this context, in Figures 2 to 5 In the example, the cell boundary 120C of the SRAM cell 120 defines the cell boundary 120C of the SRAM cell 120 as described later in Fig.16 The area in which six transistors are generally arranged is illustrated.

[0079] The bit lines BL and BLB may extend across the SRAM array from one side of the SRAM array to the other side of the SRAM array, while the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b) may not extend across the SRAM array. For example, one end of the bit lines BL / BLB may be laterally aligned with the ends of the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b), and the other end may not be aligned with the other ends of the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b). For example, the bit lines BL and BLB may extend beyond the other ends of the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b). In some embodiments, the metal lines of the electrodes 142 / 144 (e.g., metal lines 142a, 142b, 144a, 144b) may terminate at a location directly above the SRAM cells 120. In some alternative embodiments, the metal lines of the electrodes 142 / 144 may terminate at a location above the space between the SRAM cells 120, rather than terminating at a location directly above the SRAM cells 120.

[0080] In some embodiments, the length of the metal lines 142a and 142b of the first electrode 142 is substantially equal to the length of the metal lines 144a and 144b of the second electrode 144. The lengths of the metal lines 142a and 142b of the first electrode 142 may be substantially equal to each other, and the lengths of the metal lines 144a and 144b of the second electrode 144 may be substantially equal to each other. Through this configuration, effective capacitive coupling may be established between the first electrode 142 and the second electrode 144. In addition, in some embodiments of the present invention, the distance between the metal lines 142a / 142b and the metal lines 144a / 144b may be smaller than the distance between the bit lines BL and BLB, thereby maintaining effective capacitive coupling.

[0081] In the illustrated embodiment, in a top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, the metal parallel lines (e.g., metal lines 142a, 142b, 144a, 144b) of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 are spaced apart from the bit lines BL and BLB. In some alternative embodiments, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, one or more of the metal parallel lines (e.g., metal lines 142a, 142b, 144a, 144b) of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 may overlap with the bit lines BL and BLB.

[0082] In the illustrated embodiment, in a top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, all of the metal parallel lines (e.g., metal lines 142a, 142b, 144a, 144b) of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 are located between the bit lines BL and BLB. In some alternative embodiments, in a top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, a portion of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 are located between the bit lines BL and BLB, while another portion of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 is not located between the bit lines BL and BLB. In some alternative embodiments, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140 , none of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 is located between the bit lines BL and BLB.

[0083] Figure 3 1 is a schematic top view of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 , except that in the top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, two of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 (e.g., metal lines 144a and 142b) are located between the bit lines BL and BLB, while the other two of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 (e.g., metal lines 142a and 144b) are not located between the bit lines BL and BLB. Figure 2 Other details of the present invention are similar to those described in the previous embodiments and will not be repeated here.

[0084] Figure 4 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 except that the number of metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 is 1. Figure 2 In the embodiment of the present invention, in the top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, the metal parallel lines of the first electrode 142 and the metal parallel lines of the second electrode 144 of the pull-down circuit capacitor 140 are located between the bit lines BL and BLB. Other details of the present invention are similar to the details described in the previous embodiment and will not be repeated here.

[0085] Figure 51 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 , except that in the top view, for the same row of SRAM cells 120 coupled to the same pull-down circuit capacitor 140, one of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 (e.g., the metal line of the second electrode 144) is located between the bit lines BL and BLB, and the other of the metal parallel lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 (e.g., the metal line of the first electrode 142) is not located between the bit lines BL and BLB. Figure 4 Other details of the present invention are similar to those described in the previous embodiments and will not be repeated here.

[0086] Figures 6 to 9 Methods for making integrated circuit devices according to some embodiments of the present invention are described. It should be understood that additional embodiments of the method may be Figures 11 to 14 Additional steps may be provided before, during, and after the steps shown in the drawings, and some of the steps described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0087] refer to Figure 6 One or more active and / or passive devices DE are formed on the semiconductor substrate 110 through a front-end of line (FEOL) process. An interlayer dielectric (ILD) layer DL1 may be formed covering the active and / or passive devices DE, and then a contact plug CP may be formed in the ILD layer DL1 to connect the active and / or passive devices DE. One or more active and / or passive devices DE are formed on Figure 6110 is illustrated as a single FinFET transistor. For example, the device DE may include a gate structure GS and a source / drain region SD above a region surrounded by a shallow trench isolation (STI) region SI. The gate structure GS may include a gate dielectric and a gate electrode located above the gate dielectric. Spacers SP may be formed on opposite sides of the gate structure GS. In some embodiments, the source and drain regions SD may be doped regions formed in the substrate 110. In some alternative embodiments, the source and drain regions SD may be epitaxial structures formed above the substrate 110. In some embodiments, one or more active and / or passive devices DE may include transistors (e.g., planar transistors or non-planar transistors, such as FinFETs and GAA transistors), capacitors, resistors, diodes, photodiodes, fuses, and the like. For example, one or more active and / or passive devices DE may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) devices. Moreover, one or more active and / or passive devices DE can be used as transistors of SRAM cell 120 and write driver transistors T7 and T8. It should be understood that the above examples are provided for illustrative purposes only and are not intended to limit the present invention in any way. For a given application, other circuit systems can also be formed as appropriate.

[0088] In some embodiments, a contact plug CP is formed in the ILD layer DL1. The contact plug CP is electrically coupled to the gate or source / drain region of the device DE. Fig.11 In the example illustrated in FIG. 2 , the contact plug CP makes electrical connection with the source / drain region SD of the FinFET device DE.

[0089] refer to Figure 7. After forming the contact plug CP, an interconnect structure FMLI may be formed above the contact plug CP via a back-end of line (BEOL) process. The interconnect structure FMLI may electrically interconnect one or more active and / or passive devices DE to form a functional circuit. In an embodiment of the utility model, the interconnect structure FMLI may include one or more dielectric layers and a metallization pattern located in the dielectric layer. In some embodiments, the dielectric layer of the interconnect structure FMLI may include undoped silicate glass (USG), a low-k dielectric material, an ultra-low-k dielectric material, SiO2 or other suitable materials. The dielectric layer of the interconnect structure FMLI may be referred to as an inter-metal dielectric (IMD) or an interlayer dielectric (ILD). The metallization pattern of the interconnect structure FMLI may include one or more horizontal interconnects extending horizontally or laterally in the dielectric layer of the interconnect structure FMLI, such as metallization layers M0~M2 including metal lines; and vertical interconnects extending vertically in the dielectric layer of the interconnect structure FMLI, such as conductive vias V1~V2.

[0090] In the embodiment of the present invention, the metallization layers M0-M2 are stacked on each other and spaced apart from each other along a direction Z substantially orthogonal to the directions X and Y. In some embodiments of the present invention, the metal lines of the metallization layers M0 and M2 extend along the direction Y, and the metal lines of the metallization layer M1 extend along the direction X. Each of the conductive vias V1-V2 can connect the metal lines of two adjacent ones of the metallization layers M0-M2 to each other. The metallization pattern (e.g., the metallization layers M0-M2 and the conductive vias V1-V2) can be made of a suitable conductive material (such as Cu).

[0091] In some embodiments, bit line BL and / or bit line BLB (see Figures 1 to 5 ) are metal lines of the same metallization layer (such as metallization layer M2). For example, metal line M21 of metallization layer M2 can be used as bit line BL and / or BLB. In some embodiments, word line WL (refer to Figures 1 to 5 ) is the metal line of the metallization layer M1.

[0092] refer to Figure 8 A conductive through-via TV may be formed through the device layer DEL and electrically connected to the interconnect structure FMLI. In this context, the device layer DEL may be referred to as a combination of the STI region SI, the device DE, the contact plug CP, and the ILD layer DL1 (refer to Figure 7 The backside metallization process may optionally remove the semiconductor substrate 110 (see Figure 7). Therefore, the device layer DEL may optionally include the remaining portion of the semiconductor substrate 110 (refer to Figure 7 ). In the embodiment of the present invention, the device DE may be a planar transistor or a non-planar transistor, such as a FinFET and a GAA transistor.

[0093] refer to Fig. 9 . A backside interconnect structure BMLI may be formed over the back side of the conductive through-hole TV through a backside metallization process. In an embodiment of the present invention, the backside interconnect structure BMLI may include one or more dielectric layers and a metallization pattern located in the dielectric layer. In some embodiments, the dielectric layer of the backside interconnect structure BMLI may include undoped silicate glass (USG), a low-k dielectric material, an ultra-low-k dielectric material, SiO2 or other suitable materials. The dielectric layer of the backside interconnect structure BMLI may be referred to as an inter-metal dielectric (IMD) or an interlayer dielectric (ILD). The metallization pattern of the backside interconnect structure BMLI may include one or more horizontal interconnects extending horizontally or laterally in the dielectric layer of the interconnect structure FMLI, such as metallization layers BM1 and BM2 including metal lines; and vertical interconnects extending vertically in the dielectric layer of the interconnect structure FMLI, such as conductive vias BV1. The metallization layers BM1 and BM2 overlap each other and are spaced apart from each other along the direction Z. In some embodiments of the present invention, the metal lines of the metallization layer BM1 extend along the direction Y, and the metal lines of the metallization layer BM2 extend along the direction X. The conductive via BV1 can connect the metal lines of two adjacent metallization layers BM1 and BM2 to each other. The metallization pattern (e.g., the metallization layers BM1 and BM2 and the conductive via BV1) can be made of a suitable conductive material (such as Cu).

[0094] The metal lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 (reference Figures 1 to 5 ) can track the bit lines BL and / or BLB. In the present embodiment, the first electrode 142 belongs to a metallization layer different from the metallization layer of the second electrode 144. For example, the metal line BM11 of the metallization layer BM1 and the metal line M01 of the metallization layer M0 can be used as the first electrode 142 (e.g. Figure 2 and Figure 3 The metal wires 142a and 142b or Figure 4 and Figure 5 A single metal line of the first electrode 142 in the embodiment) and a second electrode 144 (e.g. Figure 2 and Figure 3 The metal wires 144a and 144b or Figure 4 and Figure 5 In some embodiments, the metal line BM11 of the metallization layer BM1 (e.g., the first electrode 142) can be electrically connected to the write driver transistor T7 / T8 via the conductive via TV and the metallization pattern of the interconnect structure FMLI or via a suitable backside conductive contact connecting the metallization layer BM1 to the device DE. In some embodiments, the metal line M01 of the metallization layer M0 (e.g., the second electrode 144) can be electrically connected to the write driver negative voltage generator circuit 132, such as Figure 8 As shown in . In an embodiment of the present invention, electrodes 142 and 144 are described as belonging to metallization layers BM1 and M0, respectively. In some embodiments of the present invention, electrodes 142 and 144 may belong to any two of metallization layers BM2, BM1, and M0-M4, respectively, which have metal lines extending in the same direction as the bit lines BL / BLB. For example, electrodes 142 and 144 may belong to any two of metallization layers BM1, M0, M2, and M4, respectively, and their metal lines may extend in the same direction as the bit lines BL / BLB at the metallization layer M2. Other details of the embodiments of the present invention are similar to the details described above and are not repeated herein.

[0095] Fig.10 1 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. Except that in the present embodiment, at least two of the metal lines of the first electrode 142 belong to different metallization layers, and at least two of the metal lines of the second electrode 144 belong to different metallization layers, the details of the present embodiment are similar to Figures 6 to 9 For example, the metal line BM11 of the metallization layer BM1 and the metal line M01 of the metallization layer M0 can be used as the metal lines 142a and 142b of the first electrode 142, respectively (see Figure 2 and Figure 3 ), wherein the conductive via TV establishes a conductive path from the metal line BM11 of the metallization layer BM1 to the metal line M01 of the metallization layer M0. For example, the metal line BM12 of the metallization layer BM1 and the metal line M02 of the metallization layer M0 can be used as the metal lines 144a and 144b of the second electrode 144, respectively (refer to Figure 2 and Figure 3), wherein the conductive through hole TV establishes a conductive path from the metal line BM12 of the metallization layer BM1 to the metal line M02 of the metallization layer M0. In an embodiment of the present invention, at least two metal lines of the electrode 142 / 144 are described as belonging to the metallization layers BM1 and M0, respectively. In some embodiments of the present invention, at least two metal lines of the electrode 142 / 144 may belong to any two of the metallization layers BM1, BM2, M0 to M4, respectively, and have metal lines extending in the same direction as the bit line BL / BLB. For example, at least two metal lines of the electrode 142 / 144 may belong to any two of the metallization layers BM1, M0, M2 and M4, respectively, and their metal lines may extend in the same direction as the bit line BL / BLB at the metallization layer M2. Other details of the embodiments of the present invention are similar to the details described above and will not be repeated herein.

[0096] Fig.11 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. Except that in the present embodiment, the metal lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 belong to the same metallization layer, the details of the present embodiment are similar to those of the present invention. Figures 6 to 9 . For example, the metal lines BM11 and BM12 of the metallization layer BM1 can be used as the metal lines of the first electrode 142 and the second electrode 144, respectively. In some embodiments, the metal line BM11 of the metallization layer BM1 (e.g., the first electrode 142) can be electrically connected to the write driver transistor T7 / T8 via the metallization pattern of the conductive through via TV and the interconnect structure FMLI or via a suitable back-side conductive contact that connects the metallization layer BM1 to the device DE. Moreover, the metal line BM12 of the metallization layer BM1 (e.g., the first electrode 142) can be electrically connected to the negative voltage generator circuit 132 via the metallization pattern of the conductive through via TV and the interconnect structure FMLI or via a suitable back-side conductive contact that connects the metallization layer BM1 to the device DE. Other details of the embodiments of the utility model are similar to the details described above and are not repeated herein.

[0097] Fig.12 1 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 except that the metal lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 belong to the interconnect structure FMLI and the backside interconnect structure BMLI is omitted. Figures 6 to 9 Details described in .

[0098] The metallization pattern of the interconnect structure FMLI may include one or more horizontal interconnects extending horizontally or laterally in the dielectric layer of the interconnect structure FMLI, such as metallization layers M0-M4 including metal lines; and vertical interconnects extending vertically in the dielectric layer of the interconnect structure FMLI, such as conductive vias V1-V4. The metallization layers M0-M4 overlap each other and are spaced apart from each other along a direction Z substantially orthogonal to directions X and Y. In some embodiments of the present invention, the metal lines of the metallization layers M0, M2, and M4 extend along direction Y, while the metal lines of the metallization layers M1 and M3 extend along direction X. Each of the conductive vias V1-V4 may connect the metal lines of two adjacent ones of the metallization layers M0-M4 to each other. The metallization pattern (e.g., the metallization layers M0-M4 and the conductive vias V1-V4) may be made of a suitable conductive material (e.g., Cu).

[0099] In some embodiments of the present invention, the metal lines of the first electrode 142 and the second electrode 144 of the pull-down circuit capacitor 140 and the bit line BL and / or the bit line BLB belong to the same metallization layer. For example, the metal line M22 of the metallization layer M2 can be used as the metal line of the first electrode 142 (e.g. Figure 2 and Figure 3 The metal wires 142a and 142b or Figure 4 and Figure 5 The metal line M23 of the metallization layer M2 can be used as a metal line of the second electrode 144 (eg, Figure 2 and Figure 3 The metal wires 144a and 144b or Figure 4 and Figure 5 Other details of the embodiment of the present invention are similar to the details described above and will not be repeated herein.

[0100] Fig.13 14 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. In addition to the metal lines of the first electrode 142 and the second electrode 144 belonging to the bit line BL and / or the bit line BLB (refer to Figures 1 to 5 ) of the same metallization layer, the details of the embodiment of the utility model are similar to Fig.12 For example, the metal line M21 of the metallization layer M2 can be used as the bit line BL and / or BLB (see Figures 1 to 5 ), and the metal wires of the metallization layer M0 or M4 can be used as the metal wires of the first electrode 142 and the metal wires of the second electrode 144. Fig.13 As shown in FIG. 1 , the metal line M01 of the metallization layer M0 may be used as the metal line of the first electrode 142 (eg, Figure 2 and Figure 3The metal wires 142a and 142b or Figure 4 and Figure 5 The metal line M02 of the metallization layer M0 can be used as a metal line of the second electrode 144 (eg, Figure 2 and Figure 3 The metal wires 144a and 144b or Figure 4 and Figure 5 A single metal line of the second electrode 144 in FIG.

[0101] In the embodiment of the present invention, when viewed from the top, the metal line of the first electrode 142 and the metal line of the second electrode 144 (e.g., the metal lines M01 and M02 of the metallization layer M0) may be spaced apart from the bit line BL and / or the bit line BLB (e.g., the metal line M21 of the metallization layer M2). Other details of the embodiment of the present invention are similar to the details described above and are not repeated herein.

[0102] Fig.14 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 , except that at least one of the metal lines of the pull-down circuit capacitor 140 may overlap with the bit line BL and / or the bit line BLB when viewed from the top. Fig.12 In the embodiment of the present invention, the metal line M41 of the metallization layer M4 can be used as the metal line of the first electrode 142 (eg Figure 2 and Figure 3 The metal wires 142a and 142b or Figure 4 and Figure 5 The metal line M42 of the metallization layer M4 can be used as a metal line of the second electrode 144 (eg, Figure 2 and Figure 3 The metal wires 144a and 144b or Figure 4 and Figure 5 When viewed from the top, at least one of the metal lines of the first electrode 142 and the second electrode 144 (e.g., the metal lines M41 and M42 of the metallization layer M4) may overlap with the bit line BL and / or the bit line BLB (e.g., the metal line M21 of the metallization layer M2). Other details of the embodiments of the present invention are similar to those described above and are not repeated herein.

[0103] Fig.15 1 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of FIG. 1 except that the first electrode 142 belongs to a metallization layer different from the metallization layer of the second electrode 144. Fig.12For example, the metal line M22 of the metallization layer M2 and the metal line M41 of the metallization layer M4 can be used as the first electrode 142 (eg Figure 2 and Figure 3 The metal wires 142a and 142b or Figure 4 and Figure 5 A single metal line of the first electrode 142 in the embodiment) and a second electrode 144 (e.g. Figure 2 and Figure 3 The metal wires 144a and 144b or Figure 4 and Figure 5 In some embodiments of the present invention, electrodes 142 and 144 may belong to any two of metallization layers M0 to M4, respectively, which have metal lines extending in the same direction as bit lines BL / BLB. For example, electrodes 142 and 144 may belong to any two of metallization layers M0, M2, and M4, respectively, and their metal lines may extend in the same direction as bit lines BL / BLB at metallization layer M2. Other details of the embodiments of the present invention are similar to the details described above and are not repeated herein.

[0104] Fig.16 1 is a schematic diagram of an integrated circuit device according to some embodiments of the present invention. The details of the embodiments of the present invention are similar to those of Fig.12 For example, the metal line M22 of the metallization layer M2 and the metal line M41 of the metallization layer M4 can be used as the metal lines 142a and 142b of the first electrode 142, respectively (see Figure 2 and Figure 3 ), wherein the conductive via V3, the metallization layer M3, and the conductive via V4 in combination establish a conductive path from the metal line M22 of the metallization layer M2 to the metal line M41 of the metallization layer M4. For example, the metal line M23 of the metallization layer M2 and the metal line M42 of the metallization layer M4 can be used as the metal lines 144a and 144b of the second electrode 144, respectively (refer to Figure 2 and Figure 3), wherein the conductive via V3, the metallization layer M3, and the conductive via V4 in combination establish a conductive path from the metal line M23 of the metallization layer M2 to the metal line M42 of the metallization layer M4. In an embodiment of the present invention, at least two metal lines of the electrode 142 / 144 are described as belonging to the metallization layers M2 and M4, respectively. In some embodiments of the present invention, at least two metal lines of the electrode 142 / 144 may belong to any two of the metallization layers M0 to M4, respectively, having metal lines extending in the same direction as the bit line BL / BLB. For example, at least two metal lines of the electrode 142 / 144 may belong to any two of the metallization layers M0, M2, and M4, respectively, and their metal lines may extend in the same direction as the bit line BL / BLB at the metallization layer M2.

[0105] In some embodiments, the metal line 142a of the first electrode 142 (e.g., the metal line M22 of the metallization layer M2) may vertically overlap with the metal line 142b of the first electrode 142 (e.g., the metal line M41 of the metallization layer M4). In some alternative embodiments, the metal line 142a of the first electrode 142 (e.g., the metal line M22 of the metallization layer M2) may not overlap with the metal line 142b of the first electrode 142 (e.g., the metal line M41 of the metallization layer M4). Similarly, in some embodiments, the metal line 144a of the second electrode 144 (e.g., the metal line M23 of the metallization layer M2) may vertically overlap with the metal line 144b of the second electrode 144 (e.g., the metal line M42 of the metallization layer M4). In some alternative embodiments, the metal line 144a of the second electrode 144 (e.g., the metal line M23 of the metallization layer M2) may not overlap with the metal line 144b of the second electrode 144 (e.g., the metal line M42 of the metallization layer M4). Other details of the embodiment of the utility model are similar to the details described above and are not repeated herein.

[0106] Fig.17 1 is an exemplary layout of a static random access memory (SRAM) cell according to some embodiments of the present invention. The semiconductor substrate includes an active region OD defined by an STI region SI. The active region OD may be a semiconductor fin. A source / drain region SD is formed in or above the active region OD. The gate structure GS and the source / drain region SD form a device DE including pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, and pass gate transistors PG1 and PG2. However, it should be understood by those generally familiar with the art that the features of the various embodiments described herein may be used to form other types of devices, such as 8T-SRAM memory devices or other integrated circuits. The cell layout may be flipped or rotated to achieve higher packaging density.

[0107] Based on the above discussion, it can be seen that the present invention provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages. One advantage is that the capacitor of the pull-down circuit coupled to the bit line is designed to have a reduced metal capacitor length, thereby improving write power. Another advantage is that the metal capacitor can also track the length of the bit line. Another advantage is that the reduction in metal capacitor length can solve the RC effect while maintaining capacitive coupling.

[0108] According to some embodiments of the present invention, an integrated circuit device includes a plurality of static random access memory (SRAM) cells, a first bit line, a capacitor, a write driver transistor, and a negative voltage generator circuit. The first bit line is coupled to a row of the SRAM cells, wherein the first bit line substantially extends along a first direction. The capacitor includes a first electrode and a second electrode spaced apart from the first electrode. In a top view, the first electrode has at least one first metal line substantially extending along the first direction, and the length of at least one first metal line is less than the length of the first bit line. The write driver transistor is coupled between the first bit line and the first electrode of the capacitor. The negative voltage generator circuit is coupled to the second electrode of the capacitor.

[0109] In some embodiments, in the top view, the at least one first metal line of the first electrode overlaps the SRAM cell.

[0110] In some embodiments, a number of the SRAM cells overlapping the at least one first metal line of the first electrode is less than a number of the SRAM cells overlapping the first bit line.

[0111] In some embodiments, in the top view, the second electrode has at least one second metal line extending substantially along the first direction, and a length of the at least one second metal line is smaller than the length of the first bit line.

[0112] In some embodiments, the integrated circuit device further includes a second bit line coupled to the row of the static random access memory cell, wherein in the top view, a distance between the first metal line and the second metal line is smaller than a distance between the first bit line and the second bit line.

[0113] In some embodiments, the first metal line and the first bit line belong to a same metallization layer.

[0114] In some embodiments, the first metal line and the first bit line belong to different metallization layers.

[0115] In some embodiments, the plurality of first metal lines belong to a same metallization layer.

[0116] In some embodiments, at least two of the plurality of first metal lines belong to a plurality of different metallization layers.

[0117] According to some embodiments of the present invention, an integrated circuit device includes: a first static random access memory (SRAM) cell, a second static random access memory cell, and a third static random access memory cell arranged in sequence substantially along a first direction in a top view; a first bit line coupled to the first SRAM cell to the third SRAM cell, wherein in the top view, the first bit line substantially extends along the first direction and overlaps with the first SRAM cell to the third SRAM cell; a capacitor including a first electrode and a second electrode spaced apart from the first electrode, wherein in the top view, the first electrode has at least one first metal line extending substantially along the first direction and overlapping with the first SRAM cell and the second SRAM cell, and the third SRAM cell does not overlap with the at least one first metal line; and a write driver transistor coupled between the first bit line and the first electrode of the capacitor, wherein the second electrode of the capacitor is coupled to a negative voltage level.

[0118] In some embodiments, in the top view, the first bit line extends beyond one end of the at least one first metal line.

[0119] In some embodiments, one end of the at least one first metal line overlaps with the second SRAM cell.

[0120] In some embodiments, in the top view, the second electrode has at least one second metal line extending substantially along the first direction and overlapping with the first static random access memory unit and the second static random access memory unit, and the third static random access memory unit does not overlap with the at least one second metal line.

[0121] In some embodiments, in the top view, the plurality of second metal lines are interlaced with the plurality of first metal lines.

[0122] In some embodiments, the integrated circuit device further includes a second bit line coupled to the first static random access memory cell to the third static random access memory cell, wherein in the top view, the second bit line substantially extends along the first direction and overlaps with the first static random access memory cell to the third static random access memory cell.

[0123] According to some embodiments of the present invention, a method for manufacturing an integrated circuit device is provided. The method includes: forming a static random access memory (SRAM) cell and a write driver transistor above a semiconductor substrate; forming a front-side interconnect structure above the SRAM cell and the write driver transistor, wherein the front-side interconnect structure includes a bit line coupled to the SRAM cell, wherein the bit line substantially extends along a first direction, wherein the bit line is electrically coupled between the SRAM cell and the write driver transistor; and forming a back-side interconnect structure on the back side of the write driver transistor, wherein in a top view, one of the front-side interconnect structure and the back-side interconnect structure includes a first metal line electrically coupled to the write driver transistor and a second metal line adjacent to the first metal line, wherein the first metal line and the second metal line substantially extend along the first direction, and the length of the first metal line is less than the length of the bit line.

[0124] According to some embodiments of the present invention, an integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate; a static random access memory cell and a write driver transistor, which are located above the semiconductor substrate; a front-side interconnect structure, which is located above the static random access memory cell and the write driver transistor, wherein the front-side interconnect structure includes a bit line coupled to the static random access memory cell, wherein the bit line substantially extends along a first direction, wherein the bit line is electrically coupled between the static random access memory cell and the write driver transistor; and a back-side interconnect structure, which is located on a back side of the write driver transistor, wherein in a top view, one of the front-side interconnect structure and the back-side interconnect structure includes a first metal line electrically coupled to the write driver transistor and a second metal line adjacent to the first metal line, wherein the first metal line and the second metal line substantially extend along the first direction, and a length of the first metal line is less than a length of the bit line.

[0125] In some embodiments, a ratio of the length of the first metal line to the length of the bit line is in a range of 0.1 to 0.9.

[0126] In some embodiments, the first metal line and the second metal line belong to a same metallization layer of the front-side interconnect structure and the back-side interconnect structure.

[0127] In some embodiments, the first metal line and the second metal line belong to different metallization layers of the front-side interconnect structure and the back-side interconnect structure.

[0128] In some embodiments, the length of the first metal line is substantially equal to a length of the second metal line.

[0129] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, characterized in that: include: a plurality of static random access memory cells; A first bit line is coupled to a row of the plurality of static random access memory cells, wherein the first bit line substantially extends along a first direction; A capacitor, comprising a first electrode and a second electrode spaced apart from the first electrode, wherein in a top view, the first electrode has at least one first metal line extending substantially along the first direction, and a length of the at least one first metal line is less than a length of the first bit line; a write driver transistor coupled between the first bit line and the first electrode of the capacitor; and A negative voltage generator circuit is coupled to the second electrode of the capacitor.

2. The integrated circuit device according to claim 1, wherein: In the top view, the at least one first metal line of the first electrode overlaps with the static random access memory unit.

3. The integrated circuit device according to claim 2, wherein: A number of the plurality of static random access memory cells overlapping the at least one first metal line of the first electrode is less than a number of the plurality of static random access memory cells overlapping the first bit line.

4. The integrated circuit device according to claim 1, wherein: In the top view, the second electrode has at least one second metal line substantially extending along the first direction, and a length of the at least one second metal line is smaller than the length of the first bit line.

5. An integrated circuit device, characterized in that: include: The first static random access memory unit, the second static random access memory unit and the third static random access memory unit are substantially sequentially arranged along a first direction in a top view; a first bit line coupled to the first SRAM unit to the third SRAM unit, wherein in the top view, the first bit line substantially extends along the first direction and overlaps the first SRAM unit to the third SRAM unit; a capacitor comprising a first electrode and a second electrode spaced apart from the first electrode, wherein in the top view, the first electrode has at least one first metal line extending substantially along the first direction and overlapping the first static random access memory cell and the second static random access memory cell, and the third static random access memory cell does not overlap with the at least one first metal line; and A write driver transistor is coupled between the first bit line and the first electrode of the capacitor, wherein the second electrode of the capacitor is coupled to a negative voltage level.

6. The integrated circuit device according to claim 5, characterized in that In the top view, the first bit line extends beyond one end of the at least one first metal line.

7. The integrated circuit device according to claim 5, wherein: One end of the at least one first metal line overlaps with the second static random access memory unit.

8. An integrated circuit device, characterized in that: include: a semiconductor substrate; a static random access memory cell and a write driver transistor located above the semiconductor substrate; a front-side interconnect structure located above the SRAM cell and the write driver transistor, wherein the front-side interconnect structure includes a bit line coupled to the SRAM cell, wherein the bit line extends substantially along a first direction, wherein the bit line is electrically coupled between the SRAM cell and the write driver transistor; and A backside interconnect structure is located on a back side of the write driver transistor, wherein in a top view, one of the front-side interconnect structure and the back-side interconnect structure includes a first metal line electrically coupled to the write driver transistor and a second metal line adjacent to the first metal line, the first metal line and the second metal line substantially extend along the first direction, and a length of the first metal line is less than a length of the bit line.

9. The integrated circuit device according to claim 8, wherein: A ratio of the length of the first metal line to the length of the bit line is in a range of 0.1 to 0.

9.

10. The integrated circuit device according to claim 8, wherein: The first metal line and the second metal line belong to a same metallization layer of the front-side interconnection structure and the back-side interconnection structure.

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