Multi-chip 3D packaging structure

Abstract

The utility model relates to the field of chip packaging, and specifically provides a multi-chip 3D packaging structure comprising an upper bare chip and a lower bare chip which are stacked up and down in a back-to-back manner, and active surfaces of the upper bare chip and the lower bare chip are respectively provided with an upper electric connection bump and a lower electric connection bump. One side, far away from the upper bare chip, of the upper electric connection bump comprises a first wiring layer, one side, far away from the lower bare chip, of the lower electric connection bump comprises a second wiring layer, interlayer electric connection bumps are arranged between the first wiring layer and the second wiring layer, and the space between the interlayer electric connection bumps is filled with an interlayer insulation protection layer; a containing groove is formed between the first wiring layer and the second wiring layer, and the upper bare chip and the lower bare chip are embedded in the containing groove. The multi-chip 3D packaging structure in the scheme is more complex in wiring, smaller in size, more compact in structure, higher in degree of freedom and capable of achieving smaller packaging size, shortening the interconnection distance between elements, improving the electrical performance and improving the module integration degree.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a multi-chip 3D packaging structure. Background Art

[0002] In recent years, with the continuous development of circuit integration technology, packaging technology has also achieved rapid development. The demand for miniaturized and portable electronic products in the electronic product consumer market is also increasing. Packaging technology not only affects the performance of the product, but also restricts the miniaturization of the product. When packaging multiple chips traditionally, multiple chips are usually horizontally attached to the substrate to achieve an integrated packaging structure of multiple chips. The package size is relatively large, while the smaller 2.5D package is formed by stacking the chip, interposer and substrate in sequence, which has the disadvantage of high thickness.

[0003] The 3D chip packaging structure (three-dimensional stacking) can integrate multiple chips in a small package space, and use the vertical interconnection structure between chips to shorten the channel of electrical signal connection between chips. Therefore, this packaging structure has many advantages, such as: lower signal transmission loss, lower power consumption, lower signal delay, smaller package size, and can also achieve wafer-level three-dimensional packaging and three-dimensional heterogeneous integration. It is the development direction of high-end chip packaging technology in the future. In the existing technology, the following patents involve 3D chip packaging:

[0004] The invention patent with the patent number "202010670966.1" and the patent name "A multi-chip 3D packaging structure and its manufacturing method" includes a first bare chip, a second bare chip, a conductive column, a plastic sealing layer, a first solder pad, a protective layer, a second solder pad, a protective layer, a first solder pad, a first rewiring layer, a second rewiring layer and a pin arranged back to back. The first rewiring layer is led to the back of the plastic sealing layer through the conductive column, and the second rewiring layer is electrically connected to the first rewiring layer through the conductive column. The wiring of this multi-chip 3D packaging structure is relatively more complex, smaller in size, and has a higher degree of freedom.

[0005] The invention patent application with the patent number "202210665018.8" and the patent name "A 3D packaging structure for heterogeneous multi-chips and its manufacturing method" includes a first redistribution layer, a plastic packaging material layer, multiple groups of heterogeneous chip structures, a through-hole structure, a heterogeneous single chip, an adhesive layer, metal bumps and a second redistribution layer. The multiple groups of heterogeneous chip structures are interconnected by signals through the first redistribution layer and the second redistribution layer. The 3D packaging structure for heterogeneous multi-chips provided by the invention can meet the requirements of integration, high density and small size.

[0006] However, the above-mentioned prior art has the following problems: 1. The thickness of the protective layer is too thick, the overall package thickness is relatively thick, the interconnection distance between components is large, and the integration is not high; 2. The conductive structure is straight up and down, which makes it difficult to carry out complex wiring design. Although the wiring in Comparative Document 1 is convenient, the wiring complexity is also limited, and the chip performance is limited.

[0007] In summary, how to design a 3D chip packaging structure that is small in size, compact in structure, highly integrated and easy to design for wiring is a problem that needs to be solved urgently. Utility Model Content

[0008] In order to solve the above problems, the utility model provides a multi-chip 3D packaging structure, which can reduce the overall thickness, shorten the interconnection distance between components, increase the signal transmission speed, improve the module integration, greatly increase the wiring complexity, and improve the electrical performance.

[0009] To achieve the above-mentioned purpose, the utility model proposes the following technical scheme: a multi-chip 3D packaging structure, comprising an upper bare chip and a lower bare chip stacked up and down back to back, the active surfaces of the upper bare chip and the lower bare chip are respectively provided with a plurality of upper electrical connection bumps and a plurality of lower electrical connection bumps, the side of the upper electrical connection bump away from the upper bare chip includes a first wiring layer, the side of the lower electrical connection bump away from the lower bare chip includes a second wiring layer, a plurality of interlayer electrical connection bumps are provided between the first wiring layer and the second wiring layer, and an interlayer insulating protective layer is filled between the interlayer electrical connection bumps; an accommodating groove is formed between the first wiring layer and the second wiring layer, and the upper bare chip and the lower bare chip are buried in the accommodating groove.

[0010] Furthermore, the second wiring layer includes a bottom wiring area and a second side wiring area extending upward from both side ends of the bottom wiring area, the bottom wiring area and the second side wiring area enclose a receiving groove and the upper bare chip and the lower bare chip are located in the receiving groove; the first wiring layer is arranged above the second side wiring area, and the interlayer electrical connection bump is located between the first wiring layer and the second side wiring area.

[0011] Furthermore, the first wiring layer includes a top wiring area and a first side wiring area extending downward from both side ends of the top wiring area, the top wiring area and the first side wiring area enclose a receiving groove and the upper bare chip and the lower bare chip are located in the receiving groove; the second wiring layer is arranged below the first side wiring area, and the interlayer electrical connection bump is located between the second wiring layer and the first side wiring area.

[0012] Furthermore, the first wiring layer includes a top wiring area and a first side wiring area extending downward from both side ends of the top wiring area, and the second wiring layer includes a bottom wiring area and a second side wiring area extending upward from both side ends of the bottom wiring area; a receiving groove is formed between the top wiring area, the first side wiring area, the bottom wiring area and the second side wiring area, and the upper bare chip and the lower bare chip are located in the receiving groove; the interlayer electrical connection bump is located between the first side wiring area and the second side wiring area.

[0013] Furthermore, the active surface of the upper bare chip is not higher than the upper end surface of the second side wiring area, and a middle insulating protective layer is filled between the upper electrical connection bumps and between the upper electrical connection bumps and the interlayer electrical connection bumps, and the interlayer insulating protective layer is located on both sides of the middle insulating protective layer; the lower electrical connection bumps are welded to the lower bare chip and are located at the upper end of the bottom wiring area; and pins are provided at the lower end of the bottom wiring area.

[0014] Furthermore, the active surface of the lower bare chip is not lower than the lower end surface of the first side wiring area, and a middle insulating protective layer is filled between the lower electrical connection bumps and between the lower electrical connection bumps and the interlayer electrical connection bumps, and the interlayer insulating protective layer is located on both sides of the middle insulating protective layer; the upper electrical connection bumps are welded on the upper bare chip and are located at the lower end of the top wiring area; and a pin is provided at the lower end of the second wiring layer.

[0015] Furthermore, the upper electrical connection bump is welded on the upper bare chip and located at the lower end of the top wiring area, the lower electrical connection bump is welded on the lower bare chip and located at the upper end of the bottom wiring area, and the interlayer insulating protection layer is located on both sides of the upper bare chip and the lower bare chip; a pin is provided at the lower end of the bottom wiring area.

[0016] Further, the first wiring layer and the second wiring layer each include at least two layers.

[0017] Furthermore, the upper die and the lower die each include a die, and the passive surface of the upper die and the passive surface of the lower die are arranged back to back by gluing.

[0018] Furthermore, the interlayer insulating protection layer is made of insulating resin material or inorganic material.

[0019] The beneficial effects of the utility model are:

[0020] 1. The multi-chip 3D packaging structure of the present invention forms an embedded receiving groove between the first wiring layer and the second wiring layer. The chip is placed in the receiving groove, which can shorten the interconnection distance between components, increase the signal transmission speed, reduce signal crosstalk, noise and electromagnetic interference, improve electrical performance, reduce module size, increase module integration, save external space, and is of great significance for realizing high-performance, high-requirement, miniaturized and thin portable electronic devices.

[0021] 2. The thickness of the interlayer insulating protective layer and the middle insulating protective layer is shortened in the utility model, so that the paths of the upper electrical connection bump, the lower electrical connection bump and the interlayer electrical connection bump are shortened. Compared with the straight-up and straight-down electrical connection path with only one channel in the prior art, the complexity of the wiring design can be greatly increased. During wiring, the line can have space to turn repeatedly, which facilitates the conversion of the line and improves the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is an overall schematic diagram of the multi-chip 3D packaging structure provided in the first embodiment of the present utility model.

[0023] Figure 2 It is an overall schematic diagram of the multi-chip 3D packaging structure provided in the second embodiment of the present utility model.

[0024] Figure 3 It is an overall schematic diagram of the multi-chip 3D packaging structure provided in the third embodiment of the present utility model.

[0025] Figure numerals: upper bare chip 1, lower bare chip 2, upper electrical connection bump 3, lower electrical connection bump 4, first wiring layer 5, second wiring layer 6, interlayer electrical connection bump 7, interlayer insulating protection layer 8, accommodating groove 9, bottom wiring area 10, second side wiring area 11, top wiring area 12, first side wiring area 13, middle insulating protection layer 14, pin 15. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following Figure 1-3 It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation on the present invention. Embodiment 1

[0027] A multi-chip 3D packaging structure, such as Figure 1 As shown, it includes an upper die 1 and a lower die 2 stacked up and down back to back. In this embodiment, the upper die 1 and the lower die 2 each include one die. Those skilled in the art may also set other numbers of upper die 1 and lower die 2. The passive surface of the upper die 1 and the passive surface of the lower die 2 are bonded back to back by gluing. The back-to-back gluing position is as shown in FIG. Figure 1 As shown at L in the figure. The active surfaces of the upper die 1 and the lower die 2 are respectively as shown in FIG. Figure 1As shown at N and M in the figure, a plurality of upper electrical connection bumps 3 and a plurality of lower electrical connection bumps 4 are welded on the active surfaces of the upper bare chip 1 and the lower bare chip 2, respectively. The side of the upper electrical connection bump 3 away from the upper bare chip 1 includes a first wiring layer 5, and the side of the lower electrical connection bump 4 away from the lower bare chip 2 includes a second wiring layer 6. The first wiring layer 5 and the second wiring layer 6 each include at least two layers.

[0028] A plurality of interlayer electrical connection bumps 7 are provided between the first wiring layer 5 and the second wiring layer 6, and an interlayer insulating protection layer 8 is filled between the interlayer electrical connection bumps 7. The interlayer insulating protection layer 8 is an insulating resin material or an inorganic material, such as epoxy resin, and the upper electrical connection bumps 3 and the lower electrical connection bumps 4 are solder bumps, such as solder balls.

[0029] A receiving groove 9 is formed between the first wiring layer 5 and the second wiring layer 6, and the upper bare chip 1 and the lower bare chip 2 are buried in the receiving groove 9. The receiving groove 9 forms an embedded structure between the first wiring layer 5 and the second wiring layer 6. The upper bare chip 1 and the lower bare chip 2 are buried in the receiving groove 9, which can reduce the overall thickness of the packaging structure.

[0030] The second wiring layer 6 includes a bottom wiring area 10 and a second side wiring area 11 extending upward from both side ends of the bottom wiring area 10. The bottom wiring area 10 and the second side wiring area 11 enclose a receiving groove 9, and the upper bare chip 1 and the lower bare chip 2 are located in the receiving groove 9; the first wiring layer 5 is arranged above the second side wiring area 11, and the interlayer electrical connection bump 7 is located between the first wiring layer 5 and the second side wiring area 11.

[0031] The active surface of the upper bare chip 1 is not lower than the upper end surface of the second side wiring area 11. In this embodiment, the active surface of the upper bare chip 1 is flush with the upper end surface of the second side wiring area 11. The middle insulating protective layer 14 is filled between the upper electrical connection bumps 3 and between the upper electrical connection bumps 3 and the interlayer electrical connection bumps 7. The interlayer insulating protective layer 8 is located on both sides of the middle insulating protective layer 14. The middle insulating protective layer 14 is an insulating resin material or an inorganic material, such as epoxy resin. The lower electrical connection bump 4 is welded on the lower bare chip 2 and is located at the upper end of the bottom wiring area 10. A pin 15 is provided at the lower end of the bottom wiring area 10.

[0032] In this embodiment, the upper bare chip 1 and the lower bare chip 2 are buried in the buried receiving groove 9 formed on the second wiring layer 6, thereby reducing the thickness of the interlayer insulating protection layer 8 between the first wiring layer 5 and the second wiring layer 6, thereby reducing the overall volume and thickness, increasing the complexity of wiring, and improving electrical performance. Embodiment 2

[0033] like Figure 2As shown, the difference between this embodiment and the first embodiment is that the first wiring layer 5 includes a top wiring area 12 and a first side wiring area 13 extending downward from both side ends of the top wiring area 12, and a receiving groove 9 is formed between the top wiring area 12 and the first side wiring area 13. The upper bare chip 1 and the lower bare chip 2 are located in the receiving groove 9. The receiving groove 9 forms an embedded structure between the first wiring layer 5 and the second wiring layer 6. The upper bare chip 1 and the lower bare chip 2 are buried in the receiving groove 9, which can reduce the overall thickness of the packaging structure. The second wiring layer 6 is arranged below the first side wiring area 13, and the interlayer electrical connection bump 7 is located between the second wiring layer 6 and the first side wiring area 13.

[0034] The active surface of the lower bare chip 2 shown in M ​​is not lower than the lower end surface of the first side wiring area 13. In this embodiment, the active surface of the lower bare chip 2 is arranged flush with the lower end surface of the first side wiring area 13. The middle insulating protection layer 14 is filled between the lower electrical connection bumps 4 and between the lower electrical connection bumps 4 and the interlayer electrical connection bumps 7. The interlayer insulating protection layer 8 is located on both sides of the middle insulating protection layer 14. The upper electrical connection bumps 3 are welded on the upper bare chip 1 and are located at the lower end of the top wiring area 12. A pin 15 is provided at the lower end of the second wiring layer 6.

[0035] In this embodiment, the upper bare chip 1 and the lower bare chip 2 are buried in the buried receiving groove 9 formed on the first wiring layer 5, thereby reducing the thickness of the interlayer insulating protection layer 8 between the first wiring layer 5 and the second wiring layer 6, increasing the complexity of wiring, improving the electrical performance, and reducing the overall volume and size of the packaging structure. Embodiment 3

[0036] like Figure 3 As shown, the difference between this embodiment and the first embodiment is that the first wiring layer 5 includes a top wiring area 12 and a first side wiring area 13 extending downward from both side ends of the top wiring area 12, the second wiring layer 6 includes a bottom wiring area 10 and a second side wiring area 11 extending upward from both side ends of the bottom wiring area 10, the top wiring area 12, the first side wiring area 13, the bottom wiring area 10 and the second side wiring area 11 enclose a receiving groove 9, the upper bare chip 1 and the lower bare chip 2 are located in the receiving groove 9, the interlayer electrical connection bump 7 is located between the first side wiring area 13 and the second side wiring area 11, and the interlayer insulating protection layer 8 is located on both sides of the upper bare chip 1 and the lower bare chip 2.

[0037] The upper electrical connection bump 3 is welded on the upper bare chip 1 and is located at the lower end of the top wiring area 12, and the lower electrical connection bump 4 is welded on the lower bare chip 2 and is located at the upper end of the bottom wiring area 10. The lower end of the bottom wiring area 10 is provided with a pin 15. In this embodiment, the upper bare chip 1 and the lower bare chip 2 are buried in the accommodating groove 9 formed on the first wiring layer 5 and the second wiring layer 6, thereby reducing the thickness of the interlayer insulating protection layer 8 between the first wiring layer 5 and the second wiring layer 6.

[0038] Although the embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

[0039] The above specific implementation methods of the utility model do not constitute a limitation on the protection scope of the utility model. Any other corresponding changes and modifications made according to the technical concept of the utility model should be included in the protection scope of the claims of the utility model.

Claims

1. A multi-chip 3D packaging structure, characterized in that: The invention comprises an upper bare chip (1) and a lower bare chip (2) which are stacked up and down back to back, wherein the active surfaces of the upper bare chip (1) and the lower bare chip (2) are respectively provided with a plurality of upper electrical connection bumps (3) and a plurality of lower electrical connection bumps (4), the side of the upper electrical connection bumps (3) away from the upper bare chip (1) comprises a first wiring layer (5), and the side of the lower electrical connection bumps (4) away from the lower bare chip (2) comprises a second wiring layer (6), a plurality of interlayer electrical connection bumps (7) are provided between the first wiring layer (5) and the second wiring layer (6), and an interlayer insulating protective layer (8) is filled between the interlayer electrical connection bumps (7); and an accommodating groove (9) is formed between the first wiring layer (5) and the second wiring layer (6), and the upper bare chip (1) and the lower bare chip (2) are buried in the accommodating groove (9).

2. The multi-chip 3D packaging structure according to claim 1, characterized in that: The second wiring layer (6) comprises a bottom wiring area (10) and a second side wiring area (11) extending upward from both side ends of the bottom wiring area (10); a receiving groove (9) is formed between the bottom wiring area (10) and the second side wiring area (11), and the upper bare chip (1) and the lower bare chip (2) are located in the receiving groove (9); the first wiring layer (5) is arranged above the second side wiring area (11), and the interlayer electrical connection bump (7) is located between the first wiring layer (5) and the second side wiring area (11).

3. The multi-chip 3D packaging structure according to claim 1, characterized in that: The first wiring layer (5) comprises a top wiring area (12) and a first side wiring area (13) extending downward from both side ends of the top wiring area (12); a receiving groove (9) is formed between the top wiring area (12) and the first side wiring area (13), and the upper bare chip (1) and the lower bare chip (2) are located in the receiving groove (9); the second wiring layer (6) is arranged below the first side wiring area (13), and the interlayer electrical connection bump (7) is located between the second wiring layer (6) and the first side wiring area (13).

4. The multi-chip 3D packaging structure according to claim 1, characterized in that: The first wiring layer (5) comprises a top wiring area (12) and a first side wiring area (13) extending downward from both side ends of the top wiring area (12); the second wiring layer (6) comprises a bottom wiring area (10) and a second side wiring area (11) extending upward from both side ends of the bottom wiring area (10); the top wiring area (12), the first side wiring area (13), the bottom wiring area (10) and the second side wiring area (11) enclose a receiving groove (9), and the upper bare chip (1) and the lower bare chip (2) are located in the receiving groove (9); and the interlayer electrical connection bump (7) is located between the first side wiring area (13) and the second side wiring area (11).

5. The multi-chip 3D packaging structure according to claim 2, characterized in that: The active surface of the upper bare chip (1) is not higher than the upper end surface of the second side wiring area (11); a middle insulating protective layer (14) is filled between the upper electrical connection bumps (3) and between the upper electrical connection bumps (3) and the interlayer electrical connection bumps (7); the interlayer insulating protective layer (8) is located on both sides of the middle insulating protective layer (14); the lower electrical connection bumps (4) are welded to the lower bare chip (2) and are located at the upper end of the bottom wiring area (10); and a pin (15) is provided at the lower end of the bottom wiring area (10).

6. The multi-chip 3D packaging structure according to claim 3, characterized in that: The active surface of the lower bare chip (2) is not lower than the lower end surface of the first side wiring area (13); a middle insulating protective layer (14) is filled between the lower electrical connection bumps (4) and between the lower electrical connection bumps (4) and the interlayer electrical connection bumps (7); the interlayer insulating protective layer (8) is located on both sides of the middle insulating protective layer (14); the upper electrical connection bumps (3) are welded to the upper bare chip (1) and are located at the lower end of the top wiring area (12); and a pin (15) is provided at the lower end of the second wiring layer (6).

7. The multi-chip 3D packaging structure according to claim 4, characterized in that: The upper electrical connection bump (3) is welded on the upper bare chip (1) and is located at the lower end of the top wiring area (12); the lower electrical connection bump (4) is welded on the lower bare chip (2) and is located at the upper end of the bottom wiring area (10); an interlayer insulating protection layer (8) is located on both sides of the upper bare chip (1) and the lower bare chip (2); and a pin (15) is provided at the lower end of the bottom wiring area (10).

8. The multi-chip 3D packaging structure according to any one of claims 2 to 7, characterized in that: The first wiring layer (5) and the second wiring layer (6) each include at least two layers.

9. The multi-chip 3D packaging structure according to claim 8, characterized in that: The upper bare chip (1) and the lower bare chip (2) each comprise a bare chip, and the passive surface of the upper bare chip (1) and the passive surface of the lower bare chip (2) are bonded back to back by means of gluing.

10. The multi-chip 3D packaging structure according to claim 9, characterized in that: The interlayer insulating protective layer (8) is made of insulating resin material or inorganic material.

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