NAS hard disk power supply control system, circuit board and network attached storage device
By using a SOC processor connected to a power switch and hard drive socket in the NAS hard drive power supply control system, the problems of excessive startup current and high power management costs of portable hard drives are solved, achieving intelligent power supply and energy-saving effects.
Patent Information
- Application Number
- CN202421102092.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-05-17
AI Technical Summary
Existing technologies suffer from excessively high starting current for portable hard drives, high power requirements for power adapters when powering multiple hard drives, and an inability to intelligently control hard drive power supply based on system status, resulting in high costs and difficulty in achieving energy savings.
Design a NAS hard drive power supply control system. The system uses a SOC processor connected to multiple power switches and hard drive sockets. The SOC processor obtains the hard drive insertion status and system status, and controls the power switches to achieve intelligent power supply management.
No additional microcontroller is required, reducing design costs, and the system can automatically disconnect the hard drive power supply based on the system status, achieving energy-saving effects.
Smart Images
Figure CN222337923U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of mobile hard disks, in particular to a NAS hard disk power supply control system, a circuit board and a network attached storage device. Background Art
[0002] At present, the instantaneous current of mobile hard disk startup is too large, and when powering multiple hard disks at the same time, the power requirement of the power adapter is relatively high. In order to reduce the power of the power adapter, an additional single-chip microcomputer is generally added to the system for power supply control, so that it only powers group A hard disks first, and then powers group B hard disks after a set delay time, and keeps powering group A hard disks. Although this method can reduce the power demand of the power adapter, on the one hand, it requires an additional single-chip microcomputer, which makes the cost higher. On the other hand, it cannot intelligently control the on and off of the hard disk power supply according to different system states, making it difficult to achieve energy saving.
[0003] Therefore, it is very important for technicians in this field to design a low-cost NAS hard disk power supply control system, circuit board and network attached storage device that can intelligently control the hard disk power supply according to different system states. Utility Model Content
[0004] The embodiments of the utility model provide a NAS hard disk power supply control system, a circuit board and a network attached storage device with low cost and capable of intelligently controlling the hard disk power supply according to different system states, so as to solve the defect in the prior art that the hard disk power supply cannot be turned off after the system is turned on, making it difficult to achieve energy saving.
[0005] The utility model discloses a NAS hard disk power supply control system, which comprises: a SOC processor, a plurality of power switches and a plurality of hard disk sockets; the power switch is arranged on the power supply path of the hard disk socket, the input and output ends of the hard disk socket are connected with the input and output ends of the SOC processor to obtain data signals; the detection end of the SOC processor is connected with the hard disk socket to obtain the hard disk insertion state; the control end of the SOC processor is connected with the power switch to control the on and off of the power switch according to the hard disk insertion state and the system state.
[0006] Among them, a preferred solution is to include a first hard disk socket, wherein the first input end and the second input end of the first hard disk socket are both connected to the first output end of the SOC processor, and a first power switch is arranged between the first input end of the first hard disk socket and the first output end of the SOC processor, and a second power switch is arranged between the second input end of the first hard disk socket and the first output end of the SOC processor.
[0007] Among them, a preferred solution is that it also includes a second hard disk socket, the first input end and the second input end of the second hard disk socket are both connected to the second output end of the SOC processor, and a third power switch is arranged between the first input end of the second hard disk socket and the second output end of the SOC processor, and a fourth power switch is arranged between the second input end of the second hard disk socket and the second output end of the SOC processor.
[0008] Among them, a preferred solution is that the SOC processor includes a first detection end and a second detection end, the first detection end is connected to the first hard disk socket, and the second detection end is connected to the second hard disk socket, so as to receive a hard disk insertion signal.
[0009] Among them, a preferred solution is that a first protection resistor and a first protection capacitor are provided between the first detection end and the first hard disk socket, and a second protection resistor and a second protection capacitor are provided between the second detection end and the second hard disk socket.
[0010] Among them, a preferred solution is that the SOC processor includes a first control end and a second control end, the first control end of the SOC processor is respectively connected to the first power switch and the second power switch, and the second control end of the SOC processor is respectively connected to the third power switch and the fourth power switch.
[0011] Among them, a preferred solution is that the first control end outputs a high level when the first detection end is pulled low, and the second control end outputs a high level when the second detection end is pulled low.
[0012] Among them, a preferred solution is that a first MOS tube is arranged between the first power switch and the first control end of the SOC processor, the gate of the first MOS tube is connected to the first hard disk socket, and the drain of the first MOS tube is connected to the first control end of the SOC processor.
[0013] Among them, a preferred solution is that the EN pin of the fourth power switch as the enable end is connected to the second control end of the SOC processor, the voltage input pin of the fourth power switch is connected to the power supply, and the voltage output pin of the fourth power switch is connected to the 5V input pin of the second hard disk socket. When the external hard disk is inserted into the second hard disk socket, the hard disk itself acts as GND to pull down the PIN pin of the second hard disk socket, so that the second hard disk socket outputs a low level to the second detection end of the SOC processor, and the second control end of the SOC processor outputs a high level to the EN pin of the fourth power switch, and the fourth power switch is turned on and provides 5V power supply to the hard disk.
[0014] Among them, a preferred solution is that a second MOS tube is arranged between the third power switch and the second control end of the SOC processor, the gate of the second MOS tube is connected to the second hard disk socket, and the drain of the second MOS tube is connected to the second control end of the SOC processor.
[0015] Compared with the prior art, the NAS hard disk power supply control system provided by the embodiment of the utility model has the following beneficial effects: by designing a NAS hard disk power supply control system, including a SOC processor, multiple power switches and multiple hard disk sockets; and directly connecting the multiple hard disk sockets and multiple power switches to the SOC processor, on the one hand, there is no need to additionally set up a single-chip microcomputer for separate control, which effectively reduces the design cost of the whole machine; on the other hand, the SOC processor can not only obtain the power-on state and power-off state of the system, but also obtain the sleep and wake-up state of the system, and when the system is in sleep mode, disconnect the power supply of the NAS hard disk to achieve energy saving. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The technical solution of the utility model will be further described in detail below with reference to the accompanying drawings and embodiments, in which:
[0017] Figure 1 This is a module diagram of a NAS hard disk power supply control system provided by the embodiment of the utility model. Figure 1 ;
[0018] Figure 2 This is a module diagram of a NAS hard disk power supply control system provided by the embodiment of the utility model. Figure 2 ;
[0019] Figure 3 It is a circuit diagram of a first hard disk socket provided by an embodiment of the utility model;
[0020] Figure 4 It is a circuit diagram of a SOC processor provided by an embodiment of the utility model;
[0021] Figure 5 It is a circuit diagram of a second hard disk socket provided by an embodiment of the utility model;
[0022] Figure 6 is a circuit diagram of a first power switch provided in an embodiment of the utility model;
[0023] Figure 7 is a circuit diagram of a second power switch provided in an embodiment of the utility model;
[0024] Figure 8 is a circuit diagram of a third power switch provided in an embodiment of the utility model;
[0025] Fig. 9It is a circuit diagram of a fourth power switch provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. Now, in conjunction with the accompanying drawings, a preferred embodiment of the present utility model is described in detail.
[0027] like Figures 1 to 9 As shown, the utility model provides a specific embodiment of a NAS hard disk power supply control system.
[0028] A NAS hard disk power supply control system, reference Figure 1 The NAS hard disk power supply control system includes a SOC processor 1, multiple power switches 2 and multiple hard disk sockets 3; the power switch 2 is set on the power supply path of the hard disk socket 3, and the input end of the hard disk socket 3 is connected to the output end of the SOC processor 1 to obtain a data signal; the detection end 11 of the SOC processor 1 is connected to the hard disk socket 3 to obtain the hard disk insertion status; the control end 12 of the SOC processor 1 is connected to the power switch 2 to control the on and off of the power switch 2 according to the hard disk insertion status and the system status.
[0029] Specifically, refer to Figure 1 NAS hard disk is a hard disk drive for network storage, which is specially used for storing and sharing files. It is connected to the local area network through the network, so that multiple computer devices can easily access and share the storage space. Compared with ordinary hard disks, NAS hard disks are equipped with an operating system and are more intelligent; NAS hard disk power supply control system is mainly used for power supply control of NAS hard disks. SOC processor 1 is a highly integrated chip, which includes multiple functional modules such as CPU, memory controller, input / output interface, communication module, power management unit, etc.
[0030] In this embodiment, reference Figure 1 The SOC processor 1 is loaded with a Linux operating system, and the hard disk socket 3 specifically adopts a SATA connector. The signal input and output ends of the SOC processor 1 are connected to the input and output ends of the SATA connector to output SATA signals to the SATA connector. SATA is a data transmission interface standard for connecting computers and storage devices, which includes not only data signals but also power signals. The output end of the SOC processor 1 controls the power switch and can provide 12V and 5V power supply to the hard disk.
[0031] Further, refer to Figure 1The SOC processor 1 is configured with a detection terminal 11, and the detection terminal 11 of the SOC processor 1 is connected to the hard disk socket 3 to receive a hard disk insertion detection signal; when the hard disk is inserted into the hard disk socket 3, the hard disk itself acts as GND to pull down the PIN pin of the hard disk socket 3, so that the hard disk socket 3 outputs a low level to the detection terminal 11 of the SOC processor 1, thereby notifying the SOC processor 1 that a hard disk is inserted into the SATA connector.
[0032] Further, refer to Figure 1 The SOC processor 1 is configured with a control terminal 12, and the control terminal 12 of the SOC processor 1 is connected to the power switch 2. When the detection terminal 11 of the SOC processor 1 is pulled low, the control terminal 12 of the SOC processor 1 outputs a high level to the corresponding power switch 2, and the corresponding power switch 2 is turned on, so that the power supply path of the hard disk socket 3 is turned on and power is supplied to the hard disk.
[0033] Among them, when the system is in sleep, wake-up or shutdown, the SOC processor 1 can directly obtain the system's power-on signal and power-off signal to automatically turn off or turn on the power switch 2, and the SOC processor 1 as a CPU can automatically disconnect and turn on the power switch 2 according to the sleep state and wake-up state of the entire system to achieve energy saving.
[0034] In the prior art, the power supply control of a mobile hard disk is generally achieved by additionally setting up a single-chip microcomputer in the system. The single-chip microcomputer independently controls the power supply of the hard disk. When the system is turned on, the single-chip microcomputer powers on and outputs a high level to control the hard disk to be powered on, and when the system is turned off, the single-chip microcomputer powers off and outputs a low level to control the hard disk to be powered off. The single-chip microcomputer can only control the power on and power off of the hard disk by powering on and off respectively. In this way, after the system is turned on, the hard disk will always remain powered on, and the power supply to the hard disk cannot be turned off to achieve energy saving.
[0035] In this embodiment, a NAS hard disk power supply control system is designed, including a SOC processor, multiple power switches and multiple hard disk sockets; and the multiple hard disk sockets and multiple power switches are directly connected to the SOC processor. On the one hand, there is no need to set up an additional single-chip microcomputer for separate control, which effectively reduces the design cost of the whole machine; on the other hand, the SOC processor can not only obtain the power-on state and power-off state of the system, but also obtain the sleep and wake-up state of the system, and when the system is in sleep mode, disconnect the power supply of the NAS hard disk to achieve energy saving.
[0036] In one embodiment, reference Figure 2The NAS hard disk power supply control system includes a first hard disk socket 31, a first input end and a second input end of the first hard disk socket 31 are both connected to the first output end of the SOC processor 1, and a first power switch 21 is arranged between the first input end of the first hard disk socket 31 and the first output end of the SOC processor 1, and a second power switch 22 is arranged between the second input end of the first hard disk socket 31 and the first output end of the SOC processor 1.
[0037] Specifically, refer to Figures 2 to 4 The first hard disk socket 31 is a SATA connector, which includes an A+ pin, an A- pin, a B+ pin and a B- pin as signal input and output terminals. The A+ pin, A- pin, B+ pin and B- pin of the first hard disk socket 31 are all connected to the first signal input and output terminal of the SOC processor 1.
[0038] Further, refer to Figure 2 The first power switch 21 is used to control the 12V power supply of the hard disk. The SOC processor 1 includes a first control terminal 121. The control terminal 12 of the first power switch 21 is connected to the first control terminal 121 of the SOC processor 1 to be turned on or off according to the control signal of the SOC processor 1, so that the power supply path of the first hard disk socket 31 is turned on or off to turn on or cut off the 12V power supply of the hard disk.
[0039] Further, refer to Figure 2 The second power switch 22 is used to control the 5V power supply of the hard disk. The control end 12 of the second power switch 22 is connected to the first control end 121 of the SOC processor 1 to be turned on or off according to the control signal of the SOC processor 1, so that the power supply path of the first hard disk socket 31 is turned on or off to turn on or cut off the 5V power supply of the hard disk.
[0040] In one embodiment, reference Figure 2 The NAS hard disk power supply control system also includes a second hard disk socket 32, the first input end and the second input end of the second hard disk socket 32 are both connected to the second output end of the SOC processor 1, and a third power switch 23 is arranged between the first input end of the second hard disk socket 32 and the second output end of the SOC processor 1, and a fourth power switch 24 is arranged between the second input end of the second hard disk socket 32 and the second output end of the SOC processor 1.
[0041] Specifically, refer to Figure 2 , Figure 4 and Figure 5 The second hard disk socket 32 is also a SATA connector, which includes an A+ pin, an A- pin, a B+ pin and a B- pin as signal input and output terminals. The A+ pin, A- pin, B+ pin and B- pin of the second hard disk socket 32 are all connected to the signal input and output terminals of the SOC processor 1.
[0042] Further, refer to Figure 2 The third power switch 23 is used to control the 12V power supply of the hard disk. The SOC processor 1 also includes a second control terminal 122. The control terminal 12 of the third power switch 23 is connected to the second control terminal 122 of the SOC processor 1 to be turned on or off according to the control signal of the SOC processor 1, so that the power supply path of the second hard disk socket 32 is turned on or off to turn on or cut off the 12V power supply of the hard disk.
[0043] Further, refer to Figure 2 The fourth power switch 24 is used to control the 5V power supply of the hard disk. The control end 12 of the fourth power switch 24 is connected to the second control end 122 of the SOC processor 1 to be turned on or off according to the control signal of the SOC processor 1, so that the power supply path of the second hard disk socket 32 is turned on or off to turn on or cut off the 5V power supply of the hard disk.
[0044] In one embodiment, reference Figure 2 The SOC processor 1 includes a first detection terminal 111 and a second detection terminal 112. The first detection terminal 111 is connected to the first hard disk socket 31, and the second detection terminal 112 is connected to the second hard disk socket 32 for receiving a hard disk insertion signal.
[0045] Specifically, refer to Figure 2 The first detection terminal 111 is used to detect whether a hard disk is inserted into the first hard disk socket 31. When a hard disk is inserted into the first hard disk socket 31, the hard disk itself acts as GND to pull down the PIN pin of the first hard disk socket 31, so that the first hard disk socket 31 outputs a low level to the first detection terminal 111 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the first hard disk socket 31.
[0046] Further, refer to Figure 2 The second detection terminal 112 is used to detect whether a hard disk is inserted into the second hard disk socket 32. When a hard disk is inserted into the second hard disk socket 32, the hard disk itself acts as GND to pull down the PIN pin of the second hard disk socket 32, so that the second hard disk socket 32 outputs a low level to the second detection terminal 112 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the second hard disk socket 32.
[0047] In one embodiment, reference Figure 2 , Figure 3 and Figure 5 A first protection resistor R6 and a first protection capacitor C17 are provided between the first detection terminal 111 and the first hard disk socket 31 , and a second protection resistor R12 and a second protection capacitor C33 are provided between the second detection terminal 112 and the second hard disk socket 32 .
[0048] In one embodiment, reference Figure 2 , Figure 4 and Figure 6 The first power switch 21 adopts the SY6874DBC chip. The EN pin of the first power switch 21 as an enable end is connected to the first control end 121 of the SOC processor 1 to obtain a control signal. The EN pin of the first power switch 21 is also connected to the first detection end 111 of the SOC processor 1, and a first MOS tube is arranged between the EN pin of the first power switch 21 and the detection end 11 of the SOC processor 1. The gate of the first MOS tube is connected to the first hard disk socket 31, the drain of the first MOS tube is connected to the first control end 121 of the SOC processor 1, and the source of the first MOS tube is grounded.
[0049] Specifically, refer to Figure 2 , Figure 4 and Figure 6 , the voltage input pin of the first power switch 21 is connected to the 12V power supply, and the voltage output pin of the first power switch 21 is connected to the 12V input pin of the first hard disk socket 31. When the hard disk is inserted into the first hard disk socket 31, the hard disk itself acts as GND to pull down the PIN pin of the first hard disk socket 31, so that the first hard disk socket 31 outputs a low level to the first detection terminal 111 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the first hard disk socket 31, and the first control terminal 121 of the SOC processor 1 outputs a high level to the EN pin of the first power switch 21, the first power switch 21 is turned on, and provides 12V power supply for the hard disk.
[0050] In one embodiment, reference Figure 2 , Figure 4 and Figure 7 The second power switch 22 adopts the SY6874DBC chip. The EN pin of the second power switch 22 as the enable end is connected to the first control end 121 of the SOC processor 1 to obtain the control signal. The voltage input pin of the second power switch 22 is connected to the 5V power supply. The voltage output pin of the second power switch 22 is connected to the 5V input pin of the first hard disk socket 31. When the hard disk is inserted into the first hard disk socket 31, the hard disk itself acts as GND to pull down the PIN pin of the first hard disk socket 31, so that the first hard disk socket 31 outputs a low level to the detection end 11 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the first hard disk socket 31. The control end 12 of the SOC processor 1 outputs a high level to the EN pin of the first power switch 21, and the first power switch 21 is turned on and provides 5V power supply for the hard disk.
[0051] In one embodiment, reference Figure 2 , Figure 4 and Figure 8The third power switch 23 adopts the SY6874DBC chip. The EN pin of the third power switch 23 as the enable end is connected to the second control end 122 of the SOC processor 1 to obtain the control signal. The EN pin of the third power switch 23 is also connected to the second detection end 112 of the SOC processor 1, and a second MOS tube is arranged between the EN pin of the third power switch 23 and the second detection end 112 of the SOC processor 1. The gate of the second MOS tube is connected to the second hard disk socket 32, the drain of the second MOS tube is connected to the second control end 122 of the SOC processor 1, and the source of the second MOS tube is grounded.
[0052] Specifically, refer to Figure 2 , Figure 4 and Figure 8 , the voltage input pin of the third power switch 23 is connected to the 12V power supply, and the voltage output pin of the third power switch 23 is connected to the 12V input pin of the second hard disk socket 32. When the hard disk is inserted into the second hard disk socket 32, the hard disk itself acts as GND to pull down the PIN pin of the second hard disk socket 32, so that the second hard disk socket 32 outputs a low level to the second detection terminal 112 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the second hard disk socket 32. The second control terminal 122 of the SOC processor 1 outputs a high level to the EN pin of the third power switch 23, and the third power switch 23 is turned on and provides 12V power supply for the hard disk.
[0053] In one embodiment, reference Figure 2 , Figure 4 and Fig. 9 The fourth power switch 24 adopts the SY6874DBC chip. The EN pin of the fourth power switch 24 as the enable end is connected to the second control end 122 of the SOC processor 1 for obtaining the control signal. The voltage input pin of the fourth power switch 24 is connected to the 5V power supply. The voltage output pin of the fourth power switch 24 is connected to the 5V input pin of the second hard disk socket 32. When the hard disk is inserted into the second hard disk socket 32, the hard disk itself acts as GND to pull down the PIN pin of the second hard disk socket 32, so that the second hard disk socket 32 outputs a low level to the second detection end 112 of the SOC processor 1, thereby informing the SOC processor 1 that a hard disk is inserted into the fourth hard disk socket 3. The second control end 122 of the SOC processor 1 outputs a high level to the EN pin of the fourth power switch 24, and the fourth power switch 24 is turned on and provides 5V power supply to the hard disk.
[0054] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present utility model rather than to limit it. For those skilled in the art, the technical solutions described in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents; and all these modifications and replacements should fall within the scope of protection of the claims attached to the present utility model.
Claims
1. A NAS hard disk power supply control system, applied to a network attached storage device, characterized in that: include: SOC processor, multiple power switches and multiple hard disk sockets; The power switch is arranged on the power supply path of the hard disk socket, and the input and output ends of the hard disk socket are connected to the input and output ends of the SOC processor to obtain data signals; the detection end of the SOC processor is connected to the hard disk socket to obtain the hard disk insertion status; the control end of the SOC processor is connected to the power switch to control the on and off of the power switch according to the hard disk insertion status and the system status.
2. The NAS hard disk power supply control system according to claim 1, characterized in that: It includes a first hard disk socket, wherein the first input end and the second input end of the first hard disk socket are both connected to the first output end of the SOC processor, and a first power switch is arranged between the first input end of the first hard disk socket and the first output end of the SOC processor, and a second power switch is arranged between the second input end of the first hard disk socket and the first output end of the SOC processor.
3. The NAS hard disk power supply control system according to claim 2, characterized in that: It also includes a second hard disk socket, wherein the first input end and the second input end of the second hard disk socket are both connected to the second output end of the SOC processor, and a third power switch is arranged between the first input end of the second hard disk socket and the second output end of the SOC processor, and a fourth power switch is arranged between the second input end of the second hard disk socket and the second output end of the SOC processor.
4. The NAS hard disk power supply control system according to claim 3, characterized in that: The SOC processor includes a first detection end and a second detection end, wherein the first detection end is connected to the first hard disk socket, and the second detection end is connected to the second hard disk socket, for receiving a hard disk insertion signal.
5. The NAS hard disk power supply control system according to claim 4, characterized in that: A first protection resistor and a first protection capacitor are arranged between the first detection end and the first hard disk socket, and a second protection resistor and a second protection capacitor are arranged between the second detection end and the second hard disk socket.
6. The NAS hard disk power supply control system according to claim 4, characterized in that: The SOC processor includes a first control end and a second control end. The first control end of the SOC processor is connected to the first power switch and the second power switch respectively. The second control end of the SOC processor is connected to the third power switch and the fourth power switch respectively.
7. The NAS hard disk power supply control system according to claim 6, characterized in that: The enable terminal of the fourth power switch is connected to the second control terminal of the SOC processor, the voltage input terminal of the fourth power switch is connected to the power supply, and the voltage output terminal of the fourth power switch is connected to the second hard disk socket.
8. The NAS hard disk power supply control system according to claim 6, characterized in that: The first control end outputs a high level when the first detection end is pulled low, and the second control end outputs a high level when the second detection end is pulled low.
9. The NAS hard disk power supply control system according to claim 6, characterized in that: A first MOS tube is arranged between the first power switch and the first control end of the SOC processor, the gate of the first MOS tube is connected to the first hard disk socket, and the drain of the first MOS tube is connected to the first control end of the SOC processor.
10. The NAS hard disk power supply control system according to claim 3, characterized in that: A second MOS tube is arranged between the third power switch and the second control terminal of the SOC processor, the gate of the second MOS tube is connected to the second hard disk socket, and the drain of the second MOS tube is connected to the second control terminal of the SOC processor.
11. A circuit board, characterized in that: The circuit board is integrated with the NAS hard disk power supply control system as described in any one of claims 1 to 10.
12. A network attached storage device, characterized in that: The network attached storage device includes the circuit board as claimed in claim 11, or includes the NAS hard disk power supply control system as claimed in any one of claims 1-10.