Burning method of memory in field programmable system-on-chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses a burning method for memories in a field programmable system-on-chip. The field programmable system-on-chip comprises a processor system PS and a programmable logic PL, the PS comprises a first JTAG protocol conversion module, a first communication bus, a first memory controller and a first memory, and the PL comprises a second JTAG protocol conversion module, a second communication bus, a second memory controller and a second memory. The first communication bus and the second communication bus are connected through a PCAP interface; the method comprises the following steps: burning all or part of chip original information on a PS side to a first memory through a first JTAG protocol conversion module via a first communication bus and a first memory controller, and executing read-back verification; and burning all or part of the original information of the chip at the PL side to the second memory through the second JTAG protocol conversion module via the second communication bus and the second memory controller, and / or through the first JTAG protocol conversion module via the PCAP interface, the second communication bus and the second memory controller, and executing read-back verification. The chip design efficiency can be improved, and the chip design cost can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for burning a memory in a field programmable system-on-chip. Background Art

[0002] In Field Programmable SoC (FPSOC) products, there is usually an electronic fuse (EFUSE) on the processor system (PS) side and the programmable logic (PL) side, which are used to store the factory keys, verification information and control enable signals of some key modules on the PS and PL sides. The control logic of the EFUSE on both sides is relatively independent, which makes the EFUSE burning and readback verification process cumbersome and complicated when the FPSOC chip leaves the factory, greatly reducing production efficiency. Conventional FPSOC products are mainly divided into the following steps when performing EFUSE burning and readback verification:

[0003] 1. Configure FPSOC's PL JTAG and connect;

[0004] 2. Burn the EFUSE on the PL side;

[0005] 3. Perform a readback check on the EFUSE on the PL side;

[0006] 4. Configure PS JTAG of FPSOC and connect or switch;

[0007] 5. Burn EFUSE on the PS side;

[0008] 6. Perform a readback check on the EFUSE on the PS side.

[0009] In the above process, if you want to operate the EFUSE on the PL (PS) side while operating the EFUSE on the PS (or PL) side, you need to connect and switch the JTAG interface, which makes the configuration process complicated and reduces production efficiency.

[0010] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application. Summary of the invention

[0011] The purpose of this application is to provide a method for burning memory in a field programmable system-on-chip, which can be applied to conventional FPSOC chip design, greatly improving chip design efficiency and reducing chip design costs.

[0012] The present application discloses a method for programming a memory in a field programmable system-level chip, wherein the field programmable system-level chip comprises a processor system and a programmable logic, wherein the processor system comprises a first JTAG protocol conversion module, a first communication bus, a first memory controller and a first memory, wherein the programmable logic comprises a second JTAG protocol conversion module, a second communication bus, a second memory controller and a second memory, wherein the first communication bus and the second communication bus are connected via a processor configuration interface; the programming method comprises:

[0013] Burn all or part of the chip original factory information on the processor system side into the first memory via the first communication bus and the first memory controller in sequence through the first JTAG protocol conversion module and perform a read-back check;

[0014] Burn all or part of the chip original factory information on the programmable logic side into the second memory via the second communication bus and the second memory controller in sequence through the second JTAG protocol conversion module and perform a read-back check;

[0015] All or part of the chip original factory information on the programmable logic side is burned into the second memory via the first JTAG protocol conversion module in sequence via the first communication bus, the processor configuration interface, the second communication bus and the second memory controller, and a read-back check is performed.

[0016] In a preferred example, both the first memory and the second memory are one-time programmable memories.

[0017] In a preferred example, the chip factory information on the processor system side burned into the first memory includes any one or more of the following items: encryption module key information on the processor system side, specific function enable or disable control information, software reserved function storage space, and analog module calibration information on the processor system side.

[0018] In a preferred example, the chip original factory information on the programmable logic side burned into the second memory includes any one or more of the following: chip DNA information, encryption module key information on the programmable logic side, and analog module calibration information on the programmable logic side.

[0019] In a preferred example, the processor system also includes any one or more of the following groups: an application processing unit, a real-time processing unit, a neural network processing unit, and an image processing unit; the programmable logic also includes any one or more of the following groups: an embedded memory, a lookup table, a random access memory, and a phase-locked loop.

[0020] In a preferred example, it also includes: burning a user code stream into the programmable logic via the processor configuration interface through the first JTAG protocol conversion module.

[0021] In a preferred example, the first JTAG protocol conversion module and the second JTAG protocol conversion module each include: a TDO interface, a TCK interface, a TMS interface and a TDI interface.

[0022] The present application also discloses a device for burning a memory in a field programmable system-level chip, comprising:

[0023] a memory for storing computer executable instructions; and,

[0024] A processor, coupled to the memory, is configured to implement the steps in the method described above when executing the computer executable instructions.

[0025] The present application also discloses a non-transitory computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the steps in the method described above are implemented.

[0026] The present application also discloses a computer program product, which includes computer executable instructions. When the computer executable instructions are executed by a processor, the steps in the method described above are implemented.

[0027] When the field programmable system-level chip of the implementation mode of the present application burns the memory, it can reuse the processor configuration interface PCAP used for code stream configuration. When burning the memory on the processor system side or the memory on the programmable logic side, when you want to burn the memory on the other side, there is no need for any switching. Different memory burning or readback operations can be performed directly, which simplifies the process, greatly improves the chip design efficiency, and reduces the chip design cost.

[0028] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a field programmable system-on-chip according to an embodiment of the present application.

[0030] Figure 2 It is a flowchart of a method for burning a memory in a field programmable system-on-chip according to an embodiment of the present application.

[0031] In the accompanying drawings, the symbols are as follows:

[0032] 100-Field Programmable System-on-Chip

[0033] 101-processor system;

[0034] 102-Programmable logic;

[0035] 103-first JTAG protocol conversion module;

[0036] 104- a first communication bus;

[0037] 105-a first memory controller;

[0038] 106-first memory;

[0039] 107-processor configuration interface;

[0040] 108- a second communication bus;

[0041] 109-a second memory controller;

[0042] 110 - second memory;

[0043] 111-the second JTAG protocol conversion module. DETAILED DESCRIPTION

[0044] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0045] Description of some concepts:

[0046] Field Programmable System on Chip (FPSOC) is a highly integrated chip that integrates programmable logic devices (such as FPGA) with system-level components (such as processors, memory, and peripheral interfaces). FPSOC combines the advantages of system-on-chip (SoC) and field programmable gate array (FPGA). Through the built-in programmable logic unit, developers can dynamically configure and reconfigure hardware functions according to needs to achieve customized application solutions. This makes FPSOC particularly useful in projects with rapid iterations and short development cycles. The integrated dedicated hardware acceleration module can significantly improve the processing speed of specific tasks, such as signal processing, image processing, and encryption operations. Due to programmable logic, FPSOC can adapt to different application requirements, support multiple communication protocols and interface standards, and is suitable for a variety of application scenarios. With the development of emerging technologies such as the Internet of Things (IoT), 5G communications, artificial intelligence (AI), and edge computing, the demand for FPSOC continues to grow. In the future, FPSOC will develop towards higher integration, lower power consumption, and stronger processing capabilities to meet the changing market needs. In addition, the continuous optimization of software tools and development environment will further lower the development threshold of FPSOC and promote its application in more fields.

[0047] The JTAG (Joint Test Action Group) protocol is a standard interface for testing and debugging electronic systems. The JTAG protocol conversion module is a hardware module used to convert JTAG signals between different devices or interface standards, aiming to achieve compatibility between devices, improve debugging efficiency, and expand the application scope of the JTAG interface.

[0048] Processor Configuration Access Port (PCAP) is an interface used to implement communication and configuration between processors and programmable logic (such as FPGA) in a system-on-chip (SoC). PCAP allows the processor to directly access and control the programmable logic part, realizing dynamic configuration, data exchange and collaborative work.

[0049] Electronic fuses, commonly known as EFUSE, are semiconductor devices used for circuit protection, designed to replace traditional fuses or mechanical fuses. Electronic fuses use semiconductor technology to achieve fast, accurate and controllable overcurrent protection, and are widely used in various electronic devices and systems, such as consumer electronics, communication equipment, automotive electronics and industrial control systems.

[0050] In order to make the objectives, technical solutions and advantages of the present application more clear, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0051] One embodiment of the present application relates to a method for programming a memory in a field programmable system-on-chip. Figure 1 is a schematic diagram of the structure of a field programmable system-on-chip 100 in an embodiment, Figure 2 The flowchart of the method for burning the memory in one embodiment is shown in FIG. 1. The field programmable system-level chip 100 includes a processor system (PS) 101 and a programmable logic (PL) 102, and the processor system (PS) 101 and the programmable logic (PL) 102 are connected via a processor configuration access port (PCAP) 107.

[0052] In one embodiment, the processor system 101 includes a first JTAG protocol conversion module 103, a first communication bus 104, a first memory controller 105, and a first memory 106. In one embodiment, the processor system 101 may also include any one or more of the following groups: an application processing unit (Application Processor Unit, APU), a real-time processing unit (Real time Processor Unit, RPU), a neural network processing unit (Neural Processor Unit, NPU), and an image processing unit (JPEG Processor Unit, JPU).

[0053] In one embodiment, the first memory 106 is a one-time programmable memory.

[0054] In one embodiment, the first JTAG protocol conversion module 103 includes: a TDO interface, a TCK interface, a TMS interface and a TDI interface.

[0055] In one embodiment, the programmable logic 102 includes a second JTAG protocol conversion module 108, a second communication bus 109, a second memory controller 110 and a second memory 111. In one embodiment, the programmable logic 102 may also include any one or more of the following: embedded RAM, lookup tables (LUTS), random access memory (RAM), phase locked loop (PLL).

[0056] In one embodiment, the first memory 110 is a one-time programmable memory.

[0057] The PCAP interface 107 connects the first communication bus 104 of the processor system (PS) side 101 and the second communication bus 108 of the programmable logic (PL) side 102. The PCAP interface 107 is used to implement the configuration of the user code stream.

[0058] In one embodiment, the second JTAG protocol conversion module 111 includes: a TDO interface, a TCK interface, a TMS interface and a TDI interface.

[0059] It should be noted that a one-time programmable memory (OTP) is a non-volatile memory that is programmed during manufacture or first use, and its contents cannot be modified or erased after programming. This type of memory is usually used in electronic devices that need to permanently store data, code, or configuration information, such as firmware storage, key storage, and device identification. In this embodiment, the one-time programmable memory may be an electronic fuse (EFUSE).

[0060] refer to Figure 2 As shown, the burning method comprises the following steps:

[0061] Step 201 : The first JTAG protocol conversion module 103 sequentially burns all or part of the chip original factory information on the processor system 101 side into the first memory 106 via the first communication bus 104 and the first memory controller 105 and performs a read-back check.

[0062] In one embodiment, the chip factory information on the processor system 101 side burned into the first memory 106 may include any one or more of the following groups: encryption module key information on the processor system 101 side, specific function enable or disable control information, software reserved function storage space, and analog module calibration information on the processor system side.

[0063] Step 202 : burn all or part of the chip original factory information on the programmable logic 102 side into the second memory 110 through the second JTAG protocol conversion module 111 via the second communication bus 108 and the second memory controller 109 in sequence and perform a read-back check.

[0064] Step 203, the first JTAG protocol conversion module 103 sequentially burns all or part of the chip original factory information on the programmable logic 102 side to the second memory 110 via the first communication bus 104, PCAP interface 107, second communication bus 108 and second memory controller 109 and performs a read-back check.

[0065] In one embodiment, the chip original information of the programmable logic 102 side burned into the second memory 110 may include any one or more of the following: chip DNA information, encryption module key information of the programmable logic side, and analog module calibration information of the programmable logic side.

[0066] The readback check is mainly for the content that has been downloaded into EFUSE, to make a factory confirmation before delivery, to ensure that the content is in line with expectations. If there is something that does not meet expectations, such as something that should be burned but is not burned, it can be burned again. If something that should not be burned is burned, there may be a chip function loss or the chip is scrapped.

[0067] It should be understood that burning the chip factory information into the first memory 106 on the processor system 101 side can be achieved through the JTAG protocol conversion module 103 on the processor system 101 side via the first communication bus 104 and the first memory controller 105, while burning the chip factory information into the second memory 110 on the programmable logic 102 side can be achieved through the JTAG protocol conversion module 103 on the processor system 101 side via the first communication bus 104, the PCAP interface 107, the second communication bus 108 and the second memory controller 109, or can also be achieved through the JTAG protocol conversion module 111 on the programmable logic 102 side via the second communication bus 108 and the second memory controller 109. That is to say, there is one path for burning into the first memory 106 on the processor system 101 side, while there are two paths for burning into the second memory 110 on the programmable logic 102 side. When burning into the second memory 110, the user can make a choice according to actual conditions. For example, when the user needs to burn into the first memory 106 and the second memory 110 at the same time, the user can burn through the JTAG protocol conversion module 103 on the processor system 101 side at the same time, without switching to the connection of the JTAG protocol conversion module on the programmable logic 102 side. For another example, when only the first memory 106 or the second memory 110 needs to be burned, such as when supplementary burning is required, the user can make a judgment based on the currently connected JTAG protocol conversion module.

[0068] In the actual programming process, the processor system 101 side and the programmable logic 102 side need to be programmed separately. In this embodiment, when programming the memory on the processor system 101 side or the programmable logic 102 side, if you want to program the memory on the other side, you don't need to switch, just execute different memory programming or readback operations. The EFUSE programming process in this application can flexibly select different programming methods.

[0069] It should be noted that the electronic fuse (EFUSE) includes many storage bits, each of which is one-time programmable. When programming the EFUSE, not all memory bits may be programmed. For the memory bits that are not programmed, they can be reprogrammed when needed later.

[0070] In one embodiment, the burning method further includes: burning the user code stream to the programmable logic via the PCAP interface through the first JTAG protocol conversion module. The programmable logic 102 side is the user logic, and the IP instantiated by the user through the software or the hardware circuit written in Verilog will actually call the corresponding resources in the programmable logic 102 in the end. These resources can realize the functions of the IP instantiated by the user or the functions of the hardware circuit written in Verilog, that is, the user code stream is burned into the programmable logic 102, reaching each user instantiated IP for configuration or calling LUT / RAM, etc. for logical connection and function realization.

[0071] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0072] like Figure 1 The FPSOC EFUSE burning architecture shown in the figure is highly flexible and can realize a JTAG configuration connection once to complete the burning and readback verification of the EFUSE on the PS+PL side, which can improve the production efficiency of FPSOC chips. The FPSOC EFUSE burning and readback verification after optimization using this solution can be simplified as follows:

[0073] 1. Connect to PS JTAG of FPSOC;

[0074] 2. Burn the EFUSE of PL and PS;

[0075] 3. Read back and verify the EFUSE of PL and PS.

[0076] In the above process, if you want to operate the EFUSE on the PL (PS) side while operating the EFUSE on the PS (or PL) side, no switching is required. You only need to perform different EFUSE programming or readback operations, which simplifies the process and improves production efficiency.

[0077] Moreover, the architecture retains the ability to independently burn EFUSE on the PS side and the PL side. It is a universal design solution that can be applied to conventional FPSOC chip design, greatly improving chip design efficiency and reducing chip design costs.

[0078] Accordingly, the embodiments of the present application also provide a computer-readable storage medium, in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition herein, computer-readable storage media do not include transient computer-readable media (transitory media), such as modulated data signals and carriers.

[0079] In addition, the embodiment of the present application also provides a burning device for a memory in a field programmable system-level chip, which includes a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method implementation when executing the computer executable instructions in the memory. Among them, the processor can be a central processing unit (Central Processing Unit, referred to as "CPU"), a graphic processing unit (Graphic Processing Unit, referred to as "GPU"), a digital signal processor (Digital Signal Processor, referred to as "DSP"), a microcontroller unit (Microcontroller Unit, referred to as "MCU"), a neural network processor (referred to as "NPU"), an application specific integrated circuit (Application Specific Integrated Circuit, referred to as "ASIC"), a field programmable gate array (Field Programmable Gate Array, referred to as "FPGA") or other programmable logic devices, etc. The aforementioned memory can be a read-only memory (read-only memory, referred to as "ROM"), a random access memory (random access memory, referred to as "RAM"), a flash memory (Flash), a hard disk or a solid state drive, etc. The steps of the method disclosed in each embodiment of the present invention can be directly embodied as a hardware processor to be executed, or a combination of hardware and software modules in the processor to be executed.

[0080] In addition, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and when the computer executable instructions are executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0081] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0082] The serial numbers used in describing the steps of the method do not themselves constitute any limitation on the order of these steps. For example, the step with a larger serial number does not necessarily have to be executed after the step with a smaller serial number. The step with a larger serial number may be executed first and then the step with a smaller serial number. They may also be executed in parallel, as long as the execution order is reasonable to those skilled in the art. For another example, multiple steps with consecutive serial numbers (e.g., step 201, step 202, step 203, etc.) do not limit other steps that can be executed in between. For example, there may be other steps between step 201 and step 202.

[0083] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0084] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0085] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for programming a memory in a field programmable system-on-chip, characterized in that: The field programmable system-level chip includes a processor system and a programmable logic, the processor system includes a first JTAG protocol conversion module, a first communication bus, a first memory controller and a first memory, the programmable logic includes a second JTAG protocol conversion module, a second communication bus, a second memory controller and a second memory, and the first communication bus and the second communication bus are connected through a processor configuration interface; the burning method includes: Burn all or part of the chip original factory information on the processor system side into the first memory via the first communication bus and the first memory controller in sequence through the first JTAG protocol conversion module and perform a read-back check; Burn all or part of the chip original factory information on the programmable logic side into the second memory via the second communication bus and the second memory controller in sequence through the second JTAG protocol conversion module and perform a read-back check; All or part of the chip original factory information on the programmable logic side is burned into the second memory via the first JTAG protocol conversion module in sequence via the first communication bus, the processor configuration interface, the second communication bus and the second memory controller, and a read-back check is performed.

2. The method for burning a memory as claimed in claim 1, characterized in that: The first memory and the second memory are both one-time programmable memories.

3. The method for burning a memory as claimed in claim 1, characterized in that: The chip factory information on the processor system side burned into the first memory includes any one or more of the following groups: encryption module key information on the processor system side, specific function enable or disable control information, software reserved function storage space, and analog module calibration information on the processor system side.

4. The method for burning a memory as claimed in claim 1, characterized in that: The chip original information on the programmable logic side burned into the second memory includes any one or more items in the following group: chip DNA information, encryption module key information on the programmable logic side, and analog module calibration information on the programmable logic side.

5. The method for burning a memory as claimed in claim 1, characterized in that: The processor system also includes any one or more of the following groups: an application processing unit, a real-time processing unit, a neural network processing unit, and an image processing unit. The programmable logic also includes any one or more of the following groups: an embedded memory, a lookup table, a random access memory, and a phase-locked loop.

6. The method for burning a memory as claimed in claim 1, characterized in that: Also includes: The user code stream is burned into the programmable logic through the processor configuration interface by the first JTAG protocol conversion module.

7. The method for burning a memory as claimed in claim 1, characterized in that: The first JTAG protocol conversion module and the second JTAG protocol conversion module each include: a TDO interface, a TCK interface, a TMS interface and a TDI interface.

8. A device for burning memory in a field programmable system-on-chip, characterized in that: include: A memory for storing computer executable instructions; as well as, A processor, coupled to the memory, configured to implement the steps of the method according to any one of claims 1 to 7 when executing the computer executable instructions.

9. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps in the method according to any one of claims 1 to 7 are implemented.

10. A computer program product comprising computer executable instructions, characterized in that: When the computer executable instructions are executed by a processor, the steps in the method described in any one of claims 1 to 7 are implemented.

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