Level conversion circuit
By using a level conversion circuit combining resistors and transistors, the problem of existing level conversion circuits being incompatible with multiple levels is solved, enabling flexible level conversion and low-cost design.
Patent Information
- Application Number
- CN202420677844.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-03
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-04-03
AI Technical Summary
Existing level conversion circuits are only compatible with SOC outputs of 3.3V or 5V, and cannot convert low levels, which is a significant limitation.
By employing a first adjustment unit, a second adjustment unit, and a third adjustment unit, and through a combination of resistors and transistors, the conversion of various output levels of the SOC can be achieved.
It achieves compatible conversion of multiple voltage levels, with a simple circuit structure and low cost.
Smart Images
Figure CN222339380U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit design, in particular to a level conversion circuit. Background Art
[0002] At present, level conversion circuits are generally used for voltage or logic level conversion. In the related art, the current level conversion circuit is only compatible with SOC output 3.3V or 5V, and then converted to 5V or 3.3V, but cannot convert low levels, and has minor limitations. Utility Model Content
[0003] The purpose of the utility model is to overcome the shortcomings of the prior art and provide a level conversion circuit that is compatible with SOC outputs of various types of levels and completes the conversion.
[0004] The purpose of this utility model is achieved through the following technical solutions:
[0005] In a first aspect, the present application provides a level conversion circuit, comprising: an input end; a conversion module, comprising a first adjustment unit, a second adjustment unit and a third adjustment unit, the first adjustment unit is electrically connected to the input end, the second adjustment unit is electrically connected to the first adjustment unit, and the third adjustment unit is electrically connected to the second adjustment unit; and an output end, the output end is electrically connected to the third adjustment unit.
[0006] The first adjustment unit includes a resistor R1, a transistor T1 and a first output voltage point, the first end of the resistor R1 is electrically connected to the input end, the second end of the resistor R1 is electrically connected to the first end of the transistor T1, the second end of the transistor T1 is grounded, and the third end of the transistor T1 is electrically connected to the first output voltage point.
[0007] The first adjustment unit further includes a resistor R2, and a first end of the resistor R2 is electrically connected to the first output voltage point.
[0008] The first adjustment unit further includes a first pin, and the first pin is electrically connected to the second end of the resistor R2.
[0009] The second adjustment unit includes a transistor T2 and a second output voltage point, wherein a first end of the transistor T2 is electrically connected to the first output voltage point, a second end of the transistor T2 is grounded, and a third end of the transistor T2 is electrically connected to the second output voltage point.
[0010] The second adjustment unit further includes a resistor R3 and a second pin. The first end of the resistor R3 is electrically connected to the second output voltage point, and the second end of the resistor R3 is electrically connected to the second pin.
[0011] The third adjustment unit includes a third pin and a MOSFET Q1 , the third pin is electrically connected to the drain of the MOSFET Q1 , and the gate of the MOSFET Q1 is electrically connected to the second output voltage point.
[0012] The third adjustment unit also includes a resistor R4 and a third output voltage point. The first end of the resistor R4 is electrically connected to the third output voltage point. The third output voltage point is electrically connected to the source of the MOS tube Q1. The third output voltage point is also electrically connected to the output end.
[0013] The third adjustment unit further includes a fourth pin, and the fourth pin is electrically connected to the second end of the resistor R4.
[0014] The third adjustment unit further includes a resistor R5, a first end of the resistor R5 is grounded, and a second end of the resistor R5 is electrically connected to the third output voltage point.
[0015] Compared with the prior art, the utility model has at least the following advantages:
[0016] The present application can convert various types of levels of SOC outputs through the first adjustment unit, the second adjustment unit and the third adjustment unit. In addition, the present application has a simple circuit structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for use in the embodiments are briefly introduced below.
[0018] Figure 1 It is a schematic diagram of the structure of a level conversion circuit in an embodiment of the utility model;
[0019] Figure 2 FIG. 4 is a circuit diagram of a level conversion circuit in an embodiment of the present invention. DETAILED DESCRIPTION
[0020] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.
[0021] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0022] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, or a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0023] See also Figure 1 and Figure 2 A level conversion circuit includes: an input end 100, a conversion module 200 and an output end 300, the conversion module 200 includes a first adjustment unit, a second adjustment unit and a third adjustment unit, the first adjustment unit is electrically connected to the input end 100, the second adjustment unit is electrically connected to the first adjustment unit, and the third adjustment unit is electrically connected to the second adjustment unit; the output end 300 is electrically connected to the third adjustment unit.
[0024] It should be noted that the present application can convert various types of levels of SOC outputs through the first adjustment unit, the second adjustment unit and the third adjustment unit. In addition, the circuit structure of the present application is simple and the cost is low. Among them, the input end 100 is DLG_EN and the output end 300 is DLG L / S.
[0025] See also Figure 2 Specifically, the first adjustment unit includes a resistor R1, a transistor T1 and a first output voltage point, the first end of the resistor R1 is electrically connected to the input end 100, the second end of the resistor R1 is electrically connected to the first end of the transistor T1, the second end of the transistor T1 is grounded, and the third end of the transistor T1 is electrically connected to the first output voltage point. Specifically. The first adjustment unit also includes a resistor R2, the first end of the resistor R2 is electrically connected to the first output voltage point. Specifically, the first adjustment unit also includes a first pin, the first pin is electrically connected to the second end of the resistor R2.
[0026] It should be noted that the first pin is connected to an external 3.3V voltage for starting the transistor T2. Further, the first output voltage point is Figure 2 B in.
[0027] See also Figure 2 Specifically, the second adjustment unit includes a transistor T2 and a second output voltage point, the first end of the transistor T2 is electrically connected to the first output voltage point, the second end of the transistor T2 is grounded, and the third end of the transistor T2 is electrically connected to the second output voltage point. Specifically, the second adjustment unit also includes a resistor R3 and a second pin, the first end of the resistor R3 is electrically connected to the second output voltage point, and the second end of the resistor R3 is electrically connected to the second pin.
[0028] It should be noted that the second pin is used to connect to an external 12V circuit to start the MOS tube Q1. Further, the second voltage output point is Figure 2 C in.
[0029] See also Figure 2 Specifically, the third adjustment unit includes a third pin and a MOSFET Q1, the third pin is electrically connected to the drain of the MOSFET Q1, and the gate of the MOSFET Q1 is electrically connected to the second output voltage point. Specifically, the third adjustment unit also includes a resistor R4 and a third output voltage point, the first end of the resistor R4 is electrically connected to the third output voltage point, the third output voltage point is electrically connected to the source of the MOSFET Q1, and the third output voltage point is also electrically connected to the output terminal 300. Specifically, the third adjustment unit also includes a fourth pin, and the fourth pin is electrically connected to the second end of the resistor R4. Specifically, the third adjustment unit also includes a resistor R5, the first end of the resistor R5 is grounded, and the second end of the resistor R5 is electrically connected to the third output voltage point.
[0030] It should be noted that the fourth pin is connected to an external 3.3V voltage, and the third output voltage point is Figure 2 D in.
[0031] The following describes the principle of specific level conversion in this application:
[0032] First, a level signal is input to the input end, and after the resistor R1 is connected in series, the first end of the transistor T1 is connected, the second end of the transistor T1 is grounded, and the third end of the transistor T1 is pulled up by the resistor R2 and connected to the 3.3V of the first pin. If the level of the input end is low or floating at this time, the transistor T1 is cut off, so the first output voltage point B is at a high level of 3.3V; when the level of the input end is high, the transistor T1 is turned on, and the first output voltage point B is at a low level of 0.3V.
[0033] Furthermore, the first end of transistor T2 is connected to the first voltage output point, the third end of transistor T2 pull-up resistor R3 is connected to the 12V of the second pin, and is also connected to the gate of MOS tube Q1. If the first voltage output point B is at a low level of 0.3V, transistor T2 is turned off, and the second voltage output point C is at a high level of 12V; if the first voltage output point B is at a high level of 3.3V, transistor T2 is turned on, and the second voltage output point C is at a low level of 0.3V.
[0034] Furthermore, the drain of the MOS tube Q1 is directly connected to the 3.3V of the third pin, the source is connected to the resistor R5 to the ground, and the pull-up resistor R4 is also connected to 3.3V. Specifically, the resistors R4 and R5 divide the voltage to convert the voltage of the third voltage output point D into 1.8V. If the second voltage output point C is a low level of 0.3V at this time, the MOS tube Q1 is turned off, and the third voltage output point D outputs 1.8V, that is, the output end outputs 1.8V; when the second voltage output point C is a high level of 12V, the MOS tube Q1 is turned on, the drain voltage flows into the source, and the third voltage output point D outputs 3.3V, that is, the output end outputs 3.3V.
[0035] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of the various embodiments have their own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the specification are not necessarily required for the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application can be adjusted in order, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.
[0036] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A level conversion circuit, characterized in that: include: Input terminal; A conversion module, comprising a first adjustment unit, a second adjustment unit and a third adjustment unit, wherein the first adjustment unit is electrically connected to the input end, the second adjustment unit is electrically connected to the first adjustment unit, and the third adjustment unit is electrically connected to the second adjustment unit; An output end, wherein the output end is electrically connected to the third adjustment unit.
2. The level conversion circuit according to claim 1, characterized in that: The first adjustment unit includes a resistor R1, a transistor T1 and a first output voltage point, the first end of the resistor R1 is electrically connected to the input end, the second end of the resistor R1 is electrically connected to the first end of the transistor T1, the second end of the transistor T1 is grounded, and the third end of the transistor T1 is electrically connected to the first output voltage point.
3. The level conversion circuit according to claim 2, characterized in that: The first adjustment unit further includes a resistor R2, and a first end of the resistor R2 is electrically connected to the first output voltage point.
4. The level conversion circuit according to claim 3, characterized in that: The first adjustment unit further includes a first pin, and the first pin is electrically connected to the second end of the resistor R2.
5. The level conversion circuit according to claim 3, characterized in that: The second adjustment unit includes a transistor T2 and a second output voltage point, wherein a first end of the transistor T2 is electrically connected to the first output voltage point, a second end of the transistor T2 is grounded, and a third end of the transistor T2 is electrically connected to the second output voltage point.
6. The level conversion circuit according to claim 5, characterized in that: The second adjustment unit further includes a resistor R3 and a second pin. The first end of the resistor R3 is electrically connected to the second output voltage point, and the second end of the resistor R3 is electrically connected to the second pin.
7. The level conversion circuit according to claim 5, characterized in that: The third adjustment unit includes a third pin and a MOSFET Q1 , the third pin is electrically connected to the drain of the MOSFET Q1 , and the gate of the MOSFET Q1 is electrically connected to the second output voltage point.
8. The level conversion circuit according to claim 7, characterized in that: The third adjustment unit also includes a resistor R4 and a third output voltage point. The first end of the resistor R4 is electrically connected to the third output voltage point. The third output voltage point is electrically connected to the source of the MOS tube Q1. The third output voltage point is also electrically connected to the output end.
9. The level conversion circuit according to claim 8, characterized in that: The third adjustment unit further includes a fourth pin, and the fourth pin is electrically connected to the second end of the resistor R4.
10. The level conversion circuit according to claim 8, characterized in that: The third adjustment unit further includes a resistor R5, a first end of the resistor R5 is grounded, and a second end of the resistor R5 is electrically connected to the third output voltage point.