Conversion and constraint type network transmission processing circuit

Abstract

The utility model discloses a conversion and constraint type network transmission processing circuit, belongs to the technical field of electronics, and relates to a network intelligent control technology. Comprising a decoding part, a decoding conversion part, a decoding constraint part, a double-control part and a password part, wherein the decoding part comprises a decoding integrated circuit and a decoding electronic circuit, so that binary and decimal output end series can be formed, the binary output end series is connected to the input end series of the decoding conversion and decoding constraint part, and the decimal output end series is connected to the input end series of the double-control and password part. Therefore, a network control relationship can be formed; the password part comprises a password setting unit, a memory unit and a locking unit which are connected according to a certain rule, so that passwords can be generated and set randomly, a certain anti-cracking function is achieved, and the conversion and constraint type network transmission processing circuit is composed of the most common electronic digital circuit, so that the conversion and constraint type network transmission processing circuit has multiple characteristics.

Description

Technical Field

[0001] The invention belongs to the field of electronic technology and relates to network intelligent control technology. Background Art

[0002] Due to the huge advantages of the existence of the Internet, the market has researched and developed many network-related intelligent control products.

[0003] However, with the progress of society, the requirements for products are getting higher and higher, and the following situations become areas where the need for enrichment is felt.

[0004] The first situation is that many products require the cooperation of a smartphone or the installation of corresponding modules at the same time, or require corresponding software; or for the first time application, the software needs to be installed, connected, and confirmed, which increases the technical content and causes inconvenience or scientific illiteracy.

[0005] The second type of situation is that a type of product uses the method of directly transmitting the 12 key signals of the keyboard through the telephone communication network. This type of product can overcome the various shortcomings of the above-mentioned first type of products. Similar to the situation of this type of product, that is, using the telephone communication network to transmit the 12 key signals of the telephone keyboard to achieve the purpose of controlling the object. However, the technical solutions are completely different, and the various functions, performances and effects are completely different.

[0006] There are the following difficulties in implementing the measures.

[0007] 1. It is difficult to use the 12 buttons of a telephone to control 100 controllable objects without creative efforts.

[0008] 2. Based on the first point, the function of allowing users to set and change multi-digit passwords by themselves is added, which further increases the difficulty.

[0009] 3. This measure is implemented using classic traditional digital circuits, without the use of single-chip microcomputers or microprocessor high-precision devices, which improves the advantages in many aspects, but also increases the difficulties in many aspects. Summary of the invention

[0010] The main objectives of the study:

[0011] A circuit for processing information transmitted over a network is proposed, which is composed of mature and common electronic digital circuit devices. The circuit can, firstly, achieve the purpose of being able to control a large number of objects; secondly, it is equipped with a password part, which can set and change the password arbitrarily; thirdly, it has multiple characteristics, the advantage of price comparability, and a wide range of uses.

[0012] The technical solution is as follows:

[0013] A conversion and constraint type network transfer processing circuit is proposed, which includes a decoding part, a decoding conversion part, a decoding constraint part, and a dual control part.

[0014] Wherein, the decoding part includes a decoding unit and a decoding unit.

[0015] The decoding unit is composed of a decoding integrated circuit and an external circuit. The decoding unit is an electronic decoding circuit that translates binary into decimal. The input end of the decoding integrated circuit is the input end of this part, which is connected to a certain point of the audio system of the matching telephone. The output end series of the decoding integrated circuit is the binary output end series of this unit and this part, which are respectively connected to the input end series of the decoding conversion part and the input end series of the decoding constraint part, and send signals that can be processed into two new meanings to these two parts respectively. The output end series of the decoding integrated circuit is also connected to the input end series of the decoding unit described in this part. The output end series of the decoding unit is the decimal output end series of this part, which is connected to the input end of the dual control part and outputs a state control signal to the dual control part.

[0016] Among them, the decoding and conversion part includes a conversion circuit unit and a conversion and decoding integrated circuit unit with decoding properties. The signal input terminal series of the decoding and conversion part is connected to the binary output terminal series in the decoding part; the conversion control terminal of the decoding and conversion part is connected to the output terminal of the dual-control part and is controlled by the conversion of the dual-control part; the multi-bit output terminal of the decoding and conversion part is a first-type signal output terminal series of a conversion and constraint type network transmission processing circuit.

[0017] Among them, the decoding constraint part includes a constraint circuit unit and a constraint decoding integrated circuit unit. The signal input terminal series of the decoding constraint part is correspondingly connected to the binary output terminal of the decoding part to receive the signal decoded by the decoding part. The decoding constraint part also has a constraint input terminal series, one of the constraint input terminal series is connected to the corresponding output terminal of the dual control part to accept the constraint control of the dual control part. The multi-bit output terminal of the constraint decoding integrated circuit unit becomes a second type of output terminal series of a conversion and constraint type network transmission processing circuit.

[0018] Among them, the dual-control part includes a dual-control memory circuit with the properties of a memory circuit, the input end of the dual-control part is connected to the decimal output end of the decoding part, and the output end of the dual-control part is respectively connected to the conversion input end of the decoding conversion part and one of the constraint input end series of the decoding constraint part; a dual-control control signal is sent to the decoding conversion part and the constraint part.

[0019] The output terminal series of the decoding conversion part and the decoding constraint part are two output terminal series of a conversion and constraint type network transfer processing circuit.

[0020] Specifically, the conversion and constraint type network transmission processing circuit further includes a password part, and the password part includes a password setting unit and a password memory unit.

[0021] The connection relationship between the two units in the password part is: all the input terminal series of the password setting unit are the input terminal series of this part, which are connected to the decimal output terminal series of the decoding part, and all the output terminal series of the password setting unit are correspondingly connected to the input terminal series of the password memory unit.

[0022] The password setting unit comprises a plurality of movable connection elements with movable on-off properties; the ten movable connection elements constitute a password setting unit, and the password setting unit comprises a plurality of the password setting units. The input terminals of the ten movable connection elements in each of the password setting units are the input terminal series of the password setting unit and the password part, and are respectively connected to the decimal output terminal series 0-9 output terminals of the decoding part. The output terminals of the ten movable connection elements in each of the password setting units are connected together to form a single-bit output terminal of the password setting unit, and the output terminals of the plurality of password setting units constitute the output terminal series of the password setting unit.

[0023] The password memory unit includes multiple memory circuits and selection circuits, which are connected in the following manner: the signal input end of the first memory circuit is the first input end of the password memory unit, which is connected to the first output end of the password setting unit; the first input end of the first selection circuit is connected to the output end of the first memory circuit; the second input end of the first selection circuit is the second signal input end of the password memory unit; the output end of the first selection circuit is connected to the signal input end of the second memory circuit; the first input end of the second selection circuit is connected to the output end of the second memory circuit; the second input end of the second selection circuit is the third signal input end of this unit; the output end of the second selection circuit is connected to the signal input end of the third memory circuit; all the selection circuits and memory circuits are connected in the same way; the output end of the last memory circuit is the output end of the password part, which is connected to one of the constraint input end series of the decoding constraint part to send out a password constraint signal.

[0024] The password setting unit is composed of multiple small electronic switches, each of which is a password setting unit. Each small electronic switch contains ten micro switches that can be turned on and off. The input ends of the ten micro switches in the multiple small electronic switches are the input end series of the password setting unit and the password part. The output ends of the ten micro switches in each small electronic switch are connected together to form the output end of a unit. The output ends of the multiple small electronic switches constitute the output end series of the password setting unit.

[0025] The password part also includes a password locking unit, which includes a differential circuit, a timing circuit and a phase circuit composed of a third inverter. The output end of the timing circuit is connected to the input end of the phase circuit. The output end of the phase circuit is the output end of the password locking unit. The input end of the differential circuit is connected to a certain point of a logic start power supply of a conversion and constraint type network transmission processing circuit. The output end of the differential circuit is connected to the signal input end of the timing circuit; the reset input end of the timing circuit is connected to a certain output end in the decimal output end series of the decoding part; the output end of the password locking unit is connected to the reset input end of the memory circuit in the password memory unit.

[0026] Specifically, the decoding conversion part includes a conversion circuit unit with delay circuit properties and a conversion decoding integrated circuit unit with decoding properties; the conversion circuit unit is composed of four independent delay circuits, the input ends of the four independent delay circuits are respectively connected to the binary output end series of the decoding part, and the output ends of the four independent delay circuits are respectively connected to the four-bit input ends of the conversion decoding integrated circuit unit; the conversion decoding integrated circuit unit has a working enable end that can control the conversion decoding integrated circuit to the required logical working state, and the working enable end is the conversion input end of the decoding conversion part, connected to the output end of the dual control part, and the output end series of the conversion decoding integrated circuit unit is this part and also a first type of output end series of a conversion and constraint type network transmission processing circuit.

[0027] The delay circuit in the decoding conversion part is composed of a passive RC integration circuit.

[0028] Specifically, the decoding constraint part includes a constraint circuit unit and a constraint decoding integrated circuit unit, the constraint circuit unit is a circuit of logic and circuit nature, and the constraint decoding integrated circuit unit is a decoding integrated circuit; the signal input terminal series of the constraint decoding integrated circuit is connected to the binary output terminal series of the decoding part to receive the signal decoded by the decoding part, and the constraint decoding integrated circuit output terminal series is also an output terminal series of a conversion and constraint type network transmission processing circuit in this part; the constraint decoding integrated circuit has a working use terminal that can control the constraint decoding integrated circuit to a required logical working state, and the working use terminal of the constraint decoding integrated circuit is connected to the output terminal of the constraint circuit, and the constraint circuit has multiple input terminal series of logic and nature, one of which is a constraint input terminal connected to the output terminal of the dual control part to receive the program constraint signal issued by the dual control part.

[0029] Specifically, the dual-control part includes a dual-control memory circuit with the properties of a memory circuit. The signal input end and the reset input end of the dual-control part are respectively connected to two or more output ends in the decimal series of the decoding part. One or two output ends of the dual-control part are respectively connected to the conversion input end of the decoding conversion part and the constraint input end of the decoding constraint part; and dual-control control signals are sent to the decoding conversion and constraint parts.

[0030] The dual-control memory circuit in the dual-control part is composed of a first inverter and a second inverter; the input ends of the first inverter and the second inverter are respectively connected in series through isolation resistors, and then connected in series with the output ends of the first inverter and the second inverter. The input ends of the first inverter and the second inverter are respectively two input trigger ends of the dual-control memory circuit, which are respectively connected to two or more input ends of the decimal output end series of the decoding part, and the two output ends of the first inverter and the second inverter are two output ends of the dual-control part.

[0031] Specifically, the conversion and constraint type network transmission processing circuit also includes a compensation part, which is composed of multiple compensation logic and circuits with logic and properties. The compensation logic and circuit is directly divided into multiple groups, and each of the groups is composed of multiple compensation logic and circuits. The one-bit input terminals of multiple compensation logics and in each group form an input terminal series. Each group has multiple input terminal series. Each one-bit input terminal of each logic and in each group is connected to one type of input terminal. Each group contains a conversion input terminal series. The conversion input terminals of each group are respectively connected to one-bit output terminals of the output series of the decoding conversion part; two terminals of the multiple compensation logic and inputs in each group are respectively connected to one-bit output terminals in the output terminal series of the decoding constraint part. The multiple compensation logic and circuit output terminals are this part and also the third output terminal series of a conversion and constraint type network transmission processing circuit.

[0032] advantage

[0033] 1. There are many controllable objects, up to 100. With the cooperation of other achievements of the applicant, the state control of the objects can be further realized.

[0034] 2. Equipped with a random password setting circuit, the password can be multiple digits, and the specific numbers of the password can also be randomly changed, which can be used in places with high requirements.

[0035] 3. Easy to use and does not cause scientific illiteracy.

[0036] First, there is no need to download and use software, which significantly simplifies the technical difficulty in the use process. Second, 100 objects only need to operate two procedures: category and number determination; third, the category and number operands correspond to the keyboard numbers; fourth, the telephone that sends the command is not restricted; fifth, it can generate two control methods: network remote control and on-site direct operation.

[0037] 4. Easy to produce, low price and reliable operation.

[0038] The component requirements are low, and no precise devices such as single-chip microcomputers are used, which relatively relaxes the requirements in many aspects and improves reliability. No broadband network transmission and related devices are used, which makes maintenance simple.

[0039] 5. Easy to match with patented optimization and detailed engineering secondary design.

[0040] 6. Due to the above reasons, prices are highly comparable and easy to popularize. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram showing the relationship among a decoding part, a decoding conversion part, a decoding constraint part, and a dual control part.

[0042] In the figure: 1, decoding part; 1R, signal input end of decoding part; 1.1, decoding unit; 1.2, decoding unit; 1C1, binary output end series of decoding part; 1C2, decimal output end series of decoding part; 2, decoding conversion part; 2R, signal input end series of decoding conversion part; 2R1, conversion input end of decoding conversion part; 2.1, conversion circuit unit; 2.2, conversion decoding integrated circuit unit; 2C, output end series of decoding conversion part; 3, decoding constraint part; 3R, signal input terminal of the decoding constraint part; 3R1, password constraint input terminal of the decoding constraint part; 3R2, program constraint input terminal of the decoding constraint part; 3R3, backup constraint input terminal of the decoding constraint part; 3.1, constraint circuit unit; 3.2, constraint decoding integrated circuit unit; 3C, output terminal series of the decoding constraint part; 4, dual-control part; 4R1, signal input terminal of the dual-control part; 4R2, reset input terminal of the dual-control part; 4C1, conversion output terminal of the dual-control part; 4C2, constraint output terminal of the dual-control part.

[0043] FIG2 is a schematic diagram showing the relationship between the password part, the decoding part and the decoding constraint part after the password part is added.

[0044] In the figure: 1, decoding part; 1C2, decimal output terminal series of the decoding part; 3, decoding constraint part; 3R1, password constraint input terminal of the decoding constraint part; 5, password part; 5R, input terminal series of the password part; 5.1, password setting unit; 5.2, password memory unit; 5C, output terminal of the password part.

[0045] FIG3 is a schematic diagram showing the relationship between the password setting unit and the password memory unit in the password part.

[0046] In the figure: 1, decoding part; 1C2, decimal output terminal series of the decoding part;

[0047] 5. Password part; 5R. Input terminal series of password part; 5.1. Password setting unit;

[0048] 5.1R, input terminal series of password setting unit; 1, first small electronic switch;

[0049] 5.11R, the first electronic small switch inlet terminal series; 5.11C, the first electronic small switch outlet terminal;

[0050] 5.1N, the last small electronic switch;

[0051] 5.1NR, the last electronic small switch inlet terminal series; 5.1NC, the last electronic small switch outlet terminal;

[0052] 5.1C, output terminal series of password setting unit;

[0053] 5.2, password memory unit; 5.2R, signal input terminal series of password memory unit;

[0054] 5.2-X1, first selection circuit;

[0055] 5.2-X1R1, a first input terminal of a first selection circuit; 5.2-X1R2, a second input terminal of the first selection circuit;

[0056] 5.2-X1C, output end of the first selection circuit; 5.2-J1, first memory circuit;

[0057] 5.2-J1R, signal input terminal of the first memory circuit; 5.2-J1C, output terminal of the first memory circuit;

[0058] 5.2-J2, second memory circuit;

[0059] 5.2-J2R, signal input terminal of the second memory circuit; 5.2-J2C, output terminal of the second memory circuit;

[0060] 5.2-XN, the last selection circuit;

[0061] 5.2-XNR1, the first input terminal of the last selection circuit; 5.2-XNR2, the second input terminal of the last selection circuit;

[0062] 5.2-XNC, the output of the last selection circuit; 5.2-JN, the last memory circuit;

[0063] 5.2-JNR, signal input terminal of the last memory circuit; 5.2-JNC, output terminal of the last memory circuit;

[0064] 5.2C, output end of password memory unit; 5C, output end of password part.

[0065] FIG. 4 is a schematic diagram of adding a password locking unit to the password part.

[0066] In the figure: 1. Decoding part;

[0067] 1C2, decimal output terminal series of the decoding part;

[0068] 5. Password part; 5.2. Password memory unit;

[0069] 5.2-XS, a selection circuit with a similar structure not shown; 5.2-JS, a memory circuit with a similar structure not shown;

[0070] 5.2-XN, the last selection circuit; 5.2-JN, the last memory circuit;

[0071] 5.2-JNR, signal input terminal of the last memory circuit; 5.2-JNC, output terminal of the last memory circuit;

[0072] 5.2-JNQ, the reset input terminal of the last memory circuit;

[0073] 5.2C, output end of password memory unit; 5.2Q, reset input end of password memory unit; 5C, output end of password part;

[0074] 5.3, password locking unit; 5.3R1, signal input terminal of password locking unit; 5.3R2, reset input terminal of password locking unit;

[0075] 5.31, differential circuit; 5.31R, input end of the differential circuit; 5.31C, output end of the differential circuit;

[0076] 5.32, timing circuit; 5.32R1, signal input terminal of timing circuit; 5.32R2, reset input terminal of timing circuit; 5.32C, output terminal of timing circuit;

[0077] 5.33, phase circuit; 5.33R, input end of the phase circuit; 5.33C, output end of the phase circuit; 5.3C, output end of the password locking unit.

[0078] FIG. 5 is a schematic diagram showing the relationship between the dual-control part formed by the first inverter and the second inverter.

[0079] In the figure: 1, decoding part; 1C2, decimal output terminal series of the decoding part; 4, dual control part; 4R1, signal input terminal of the dual control part; 4R2, reset input terminal of the dual control part; 4.1, first inverter of the dual control part; 4.1R, input terminal of the first inverter; 4.11, first isolation resistor; 4.1C, output terminal of the first inverter; 4.2, second inverter of the dual control part; 4.2R, input terminal of the second inverter; 4.21, second isolation resistor; 4.2C, output terminal of the second inverter; 4C, two output terminals of the dual control part.

[0080] FIG6 is a schematic diagram showing the relationship between the decoding and conversion parts.

[0081] In the figure: 1, decoding part; 1C1, binary output terminal series of decoding part; 2, decoding conversion part; 2R, input terminal series of decoding conversion part; 2R1, conversion input terminal of decoding conversion part; 2.1, conversion circuit unit; 2.1R, input terminal series of conversion circuit unit; 2.11, first delay circuit; 2.11R, input terminal of first delay circuit; 2.11C, output terminal of first delay circuit; 2.12, second delay circuit; 2.13, third delay circuit; 2.14, fourth delay circuit; 2.1C, output terminal series of conversion circuit unit; 2.2, conversion and decoding integrated circuit unit; 2.2R, input terminal series of conversion and decoding integrated circuit unit; 2.2R1, work enable terminal of conversion and decoding integrated circuit unit; 2.2C, output terminal series of conversion and decoding integrated circuit unit; 2C, output terminal series of decoding conversion part; 4, dual control part; 4C1, conversion output terminal of dual control part; 4C2, constraint output terminal of dual control part.

[0082] FIG. 7 is a schematic diagram showing the relationship of the decoding constraint part.

[0083] In the figure: 1, decoding part; 1C1, binary output terminal series of the decoding part; 3, decoding constraint part; 3R, signal input terminal series of the decoding constraint part; 3R1, password constraint input terminal of the decoding constraint part; 3R2, program constraint input terminal of the decoding constraint part; 3R3, backup constraint input terminal of the decoding constraint part; 3.1, constraint circuit unit; 3.1R1, password constraint input terminal of the constraint circuit unit; 3.1R2, program constraint input terminal of the constraint circuit unit; 3.1R3, backup constraint input terminal of the constraint circuit unit; 3.1C, output terminal of the constraint circuit unit; 3.2, constraint decoding integrated circuit unit; 3.2R, input terminal series of constraint decoding integrated circuit unit; 3.2R1, working enable terminal of constraint decoding integrated circuit unit; 3.2C, output terminal series of constraint decoding integrated circuit unit; 3C, output terminal series of decoding constraint part; 4, dual control part; 4C1, conversion output terminal of dual control part; 4C2, constraint output terminal of dual control part; 5, password part; 5C, output terminal of password part.

[0084] FIG8 is a schematic diagram showing the relationship between the added compensation part, the decoding conversion part and the decoding constraint part.

[0085] In the figure: 2, decoding conversion part; 2C, output terminal series of decoding conversion part; 2C-1, the first conversion output terminal of the output terminal series of decoding conversion part; 2C-10, the tenth conversion output terminal of the output terminal series of decoding conversion part; 3, decoding constraint part; 3C, output terminal series of decoding constraint part; 3C-1, output terminal numbered 1 in the output terminal series of decoding constraint part; 3C-10, output terminal numbered 10 in the output terminal series of decoding constraint part;

[0086] 7. The compensation part consists of compensation logic and circuit;

[0087] 7R2. The numbered input terminal series of the complementary logic AND circuits in each group; 7.1. The first group having ten complementary logic AND circuits;

[0088] 7.1R1-1, the first conversion series input terminal of the first group of compensation logic and; 7.1-1, the first compensation logic and circuit of the first group;

[0089] 7.1-1R1, the first conversion input terminal of the first group that makes up the logic AND circuit;

[0090] 7.1-1R2, the first input terminal No. 1 of the first group to compensate for the logic AND circuit; 7.1-1R3, the first backup input terminal of the first group to compensate for the logic AND circuit;

[0091] 7.1-10, the tenth compensation logic and circuit of the first group;

[0092] 7.1-10R1, the tenth conversion input terminal of the first group of complementary logic and circuits;

[0093] 7.1-10R2, input terminal number 10 of the tenth complementary logic AND circuit in the first group; 7.1-10R3, backup input terminal of the tenth complementary logic AND circuit in the first group;

[0094] 7.1R3, the first set of backup input terminal series for compensating the logic and circuit; 7.1C, the first set of output terminal series for compensating the logic and circuit;

[0095] 7.2-9, the groups numbered 7.2-7.9 omitted in the compensation part; 7.10, the tenth group consisting of ten compensation logic and circuits;

[0096] 7.10R1-10, the tenth conversion series input terminal of the tenth group of complementary logic and circuits; 7.10-1, the first complementary logic and circuit of the tenth group;

[0097] 7.10-1R1, the first conversion input terminal of the tenth group that makes up the logic and circuit;

[0098] 7.10-1R2, the first input terminal No. 1 of the tenth group to compensate for the logic AND circuit; 7.10-1R3, the first backup input terminal of the tenth group to compensate for the logic AND circuit;

[0099] 7.10-10, the tenth compensatory logic and circuit of the tenth group;

[0100] 7.10-10R1, the tenth conversion input terminal of the tenth group of the compensation logic and circuit;

[0101] 7.10-10R2, input terminal number 10 of the tenth complementary logic AND circuit in the tenth group; 7.10-10R3, backup input terminal of the tenth complementary logic AND circuit in the tenth group;

[0102] 7.10R3, the tenth group of backup input terminals for making up for the logic and circuit;

[0103] 7.10C, the tenth group of output terminals that make up for the logical AND;

[0104] 7C, make up for part of the output series. DETAILED DESCRIPTION

[0105] 1. Decoding part

[0106] 1.1. The main functions of this section are:

[0107] The first is to track and decode the keyboard signals transmitted by the network, and the second is to be able to output two different types of signals to meet the needs of the connected processing circuit.

[0108] 1.2. Brief description of this part of the plan:

[0109] It is mainly composed of a decoding integrated circuit and a decoding electronic circuit that translates binary into decimal, which are connected to each other.

[0110] The output of the decoder integrated circuit is a series of binary output terminals, and the decoder circuit outputs a second series of decimal output terminals.

[0111] 1.3. Logical characteristics of this part:

[0112] First, it can track and decode the dual audio signals of the keys, and second, it can provide two different types of signals, binary and decimal, which are suitable for the needs of the related parts connected.

[0113] 2. Decoding and conversion part (as shown in Figure 6) 2.1. Function of decoding and conversion part:

[0114] 2.11. Convert the binary signal output by the decoding part into a new meaning of a classified signal.

[0115] That is, 100 controlled units can be converted into 10 types or 10 groups of signals. The first reason is that the first program is operated, and then the subsequent programs are operated. The second reason is that under the above premise, the 0 to 10 ...

[0116] The 9 series can be understood as a large number of objects can be divided into ten groups or ten categories. When any digit from 0 to 9 of the signal is output, it can be understood as a specific number in the selected ten groups or categories.

[0117] Based on the above transformation meaning, the principle of a conversion and constraint network transfer processing circuit is to divide the numerous control objects into ten categories, namely 10 groups. The second step is to determine the specific number in each group, which is also called the numbering number. This part is an important part required to implement the classification procedure in the first step.

[0118] 2.12. Operation classification procedures:

[0119] That is to select specific classification numbers of many control objects. You can select repeatedly during program operation, which is very convenient to use.

[0120] 2.13. Determine the classification procedure:

[0121] That is the final determination after the operational classification procedure in Article 2.12.

[0122] 2.2. Brief description of technical measures in this section:

[0123] The four input terminals of four independent RC delay circuits are respectively connected to the binary output terminal series of the decoding part, and the output terminals of the four delay circuits are respectively connected to the four-bit input terminals of the conversion decoding integrated circuit; the working enable terminal of the conversion decoding integrated circuit that can control the required logical working state of the conversion decoding integrated circuit is the conversion input terminal of the decoding conversion part, and is connected to the output terminal of the dual control part in a conversion and constraint type network transfer processing circuit. The output terminal series of the conversion decoding integrated circuit is this part and also the first type of output terminal series of a conversion and constraint type network transfer processing circuit.

[0124] 2.3. Working principle and logic points of the decoding conversion part:

[0125] 2.31. When the working enable terminal of the conversion decoding integrated circuit in this section is not selected, the output terminal series of the decoding integrated circuit can synchronously track and decode a series of binary output terminal signals of the decoding part in a conversion and constraint network transmission processing circuit. These signals are the corresponding decoding signals formed in each key operation process. After being processed by this part, they become a decimal corresponding signal converted into a new meaning of the grouping category.

[0126] 2.32. When the work enable terminal is selected, the decoding conversion part is in a memory holding state, that is, the output terminal series of this part will stay on the decimal signal corresponding to the previous data input terminal, and no new changes will occur. At this time, if there is a new signal at the data input terminal, the output terminal will not change by tracking the new signal of the input data. The signal selected by the confirmation key, such as the # key signal, is called the confirmation key signal of the classification program.

[0127] 2.33. Since the signal at the signal input end of the conversion-decoding integrated circuit of this part is provided by the output end of the decoding part after a delay; and the conversion confirmation signal at the working enable end of this part of the conversion-decoding integrated circuit is provided by a signal without a delay, there is a time difference between the two signals, so it can be ensured that the signal output from the output end series of the conversion-decoding integrated circuit is one of the 0-9 input of the previous data line, rather than the conversion confirmation signal of the enable end such as the # signal.

[0128] 2.34. According to the connection relationship, the signal for selecting and exiting the working enable terminal of the conversion and decoding integrated circuit of this part can be provided by the dual control operation part.

[0129] 2.35. According to the circuit structure, this part can output signals of 0-9, and can only output one unique signal. Since there is a second program after this program, the first program mentioned above can be understood as indicating that many signals can be divided into ten groups. This unique output signal can be understood as one of the group number signals finally determined after many control objects are divided into ten groups.

[0130] 2.36. The output terminal series of this section is a first-class output terminal series of a conversion and constraint type network transfer processing circuit, and also provides necessary conditions for a third-class output of a conversion and constraint type network transfer processing circuit.

[0131] 3. Decoding Constraints (as shown in Figure 7) 3.1. Function and significance of decoding constraints:

[0132] 3.11. After the binary signal output by the decoding part is converted into the meaning of the group, the new meaning of the specific number in the group is determined again.

[0133] The reason is that, based on the completion of the previous conversion program, it means that a specific unique category number, that is, a specific group number, has been determined. To operate this part of the logic program again, the numerous control objects are once again converted into specific numbers in the category number. Because this part still has 0-9 specific output terminals, and each output is unique in all output series, such logic is correct and the new meaning is reasonable. For the convenience of description, this program is called the operation number program, and the specific number of the program result is also called the number.

[0134] 3.12. Complete the numbering procedure.

[0135] The meaning is that after the number of categories of a large number of control objects is determined, the specific number of the control object in the category number is determined by operating the buttons of the telephone.

[0136] 3.13 This section is a second-class output series of a conversion and constraint type network transfer processing circuit. It also provides necessary conditions for the third-class output of a conversion and constraint type network transfer processing circuit.

[0137] 3.14. This part has the function of a master switch for all outputs of the conversion and constraint network transmission processing circuit. That is, when this part has no output, the decoding conversion part will not issue a control instruction even if it has output. The relevant part in the following text will explain this issue.

[0138] 3.15. The output of this part must meet all constraints.

[0139] First, the passwords must be completely correct; second, the decoding and conversion part has completed the confirmation procedure; third, there is signal input at the backup input terminal connected to the applicant's other achievements.

[0140] 3.2. Brief description of the technical solution for the decoding constraint part:

[0141] The signal input terminal series of the decoding integrated circuit of this part is connected to the binary output terminal series of the decoding part, and its output terminal is the output terminal series of this part, which is also a conversion and constraint type network transmission processing circuit; the output terminal of an AND gate circuit is connected to the working end that can control the constraint decoding integrated circuit to the required logical working state. The AND gate has multiple input terminals, one of which is connected to the output terminal of the dual control part of a conversion and constraint type network transmission processing circuit. Two of the input terminals are connected to the output terminal of the password part of a conversion and constraint type network transmission processing circuit. Three or more of the input terminals become a backup input terminal series, which become the input terminals of the product secondary development optimization project.

[0142] 3.3. The logic and effects of the decoding constraint part and related points:

[0143] 3.31. The binary signal output by the decoding part can be converted into a new meaning of a specific number within the determined group.

[0144] 3.32. The constraint input terminal series can work normally only if it fully meets all the constraint conditions. These constraint conditions are: first, all passwords must be completely correct, and second, the dual control part must output relevant signals. Therefore, the constraint conditions can ensure the correct logic of the password part and the decoding conversion part.

[0145] 3.33. On the contrary, when the constraint input terminal series does not meet all constraint requirements, all output terminal series of the constraint decoding integrated circuit will only output zero and will not send out control signals. This ensures that no interference signals will be generated during the operation of the previous password program and classification program. Second, it verifies the correctness of the logic from the opposite perspective.

[0146] 3.34. The numbering program can be operated normally because when the constraint input terminal series is fully satisfied, the decoding constraint part can work normally, that is, it can track and translate the signal output by the telephone key.

[0147] 3.35. The logical relationship of the password part added in the dependent claims is correct.

[0148] 3.36. The operation procedure of a conversion and constraint type network transmission processing circuit is: first, the password recognition procedure of the operation involving the password part, second, the classification operation procedure of the operation involving the decoding conversion part, and third, the numbering operation procedure of the operation involving the decoding constraint part. The three procedures do not interfere with each other. Moreover, the decoding conversion and decoding constraint parts will only output unique signals.

[0149] 4. Dual control part (as shown in Figure 5)

[0150] 4.1. The significance of dual control:

[0151] 4.11. Complete the conversion of a conversion and constraint-based network transfer processing circuit operation program.

[0152] 4.12. Confirmation of the classification operation procedures involving the decoding and conversion part, and the automatic start of the programming program simultaneously.

[0153] 4.13. Both category and number procedures can be operated repeatedly to complete the control of 100 controlled objects.

[0154] 4.2. Brief description of the technical solution for the dual control part:

[0155] 4.21. The dual-control part is composed of a dual-control memory circuit with the properties of a memory circuit. The signal input terminal and the reset input terminal of this part are respectively connected to two or more output terminals in the decimal output terminal series of the decoding part, and one or two output terminals of this part are respectively connected to the conversion input terminal of the decoding conversion part and the constraint input terminal of the decoding constraint part.

[0156] 4.22. The dual-control memory circuit in the dual-control part is composed of a first inverter and a second inverter. The input ends of the first inverter and the second inverter are connected in series and then connected in series with the output ends of the first inverter and the second inverter. The input ends of the first inverter and the second inverter are the two input trigger ends of the circuit, respectively. The two output ends of the first inverter and the second inverter are the two output ends of this part.

[0157] It should be noted here that if one output end of the operation part can simultaneously satisfy the interlocking logic state of the connected decoding conversion part and decoding constraint part, only one output end is needed. In the example, since the decoding integrated circuits in the decoding conversion and constraint parts use the same model 4514, two output ends with opposite polarities are used due to the phase requirement.

[0158] 4.23. The double-ended trigger memory circuit used in the examples in this section is the example circuit description of Section 4.22.

[0159] The example memory circuit in this section is composed of a first inverter and a second inverter, which are connected in series again after being connected in series with an isolation resistor. As shown in the attached figure, the series resistor acts to isolate the trigger signal, and the connection of the first inverter and the second inverter circuit ensures the correctness of the logical relationship. The input terminals of the first inverter and the second inverter are the two input trigger terminals of the memory circuit, and the two output terminals of the first inverter and the second inverter are the two output terminals of this section.

[0160] This double-ended trigger memory circuit has the following logical effects and characteristics.

[0161] First, for the same state, only one trigger signal is needed instead of using two signals to trigger at the same time, which makes the trigger circuit simpler; second, each trigger input terminal can be conveniently input multiple signals by using a diode to form an OR gate input method, which is conducive to the secondary development of the patent optimization design; third, the trigger signal can be triggered by a high-order signal, which is consistent with the phase of the high output terminal of the decoding part of a conversion and constraint type network transfer processing circuit; fourth, the integrated circuit has six inverter units, and the remaining four units can be in other places, and the overall circuit comprehensive rate is high; fifth, the memory circuit still has feedback components, so it is fast in the state reversal process; sixth, the output terminals of the first inverter and the second inverter are two output terminals with opposite polarities, which meet the requirements of this part. Therefore, the double-terminal trigger memory circuit has greater advantages than other forms in a conversion and constraint type network transfer processing circuit.

[0162] 4.3. The logical points of the dual control part are as follows:

[0163] 4.31. When a key is pressed, the input end of this part can track the decoding part and change into two corresponding different states.

[0164] 4.32. The dual control relationship formed by the dual control part to the decoding conversion part and the decoding constraint part is a mutually interlocking relationship.

[0165] That is, when the decoding conversion part is in the state of not being selected and working normally with decoding output, the decoding constraint part is in the state of being selected to close the door and have no output. Conversely, when the decoding conversion part is in the selected state of selecting to keep memory, the decoding constraint part is in the decoding state of being unconstrained and having output and can work normally.

[0166] 4.33. Because of the reason in the previous item, when executing the classification operation procedure, a conversion and constraint type network transmission processing circuit will not generate interference models of classification numbers 0-9. When the classification operation procedure is confirmed to be completed, the numbering operation procedure can be executed.

[0167] 4.34. You can repeatedly operate the signal and clear the input terminal signal such as the # key and the * key to change the state of the dual control part and generate the next new program until all the final programs are completed.

[0168] 4.35. The controlled object can be controlled by operating the buttons of an external telephone, or by transmitting the network to a telephone equipped with a conversion and constraint type network transmission processing circuit. The 100 objects can also be directly operated by using the keyboard buttons of a telephone equipped with a conversion and constraint type network transmission processing circuit.

[0169] 5. Compensation part (as shown in Figure 8) 5.1. Main functions of the compensation part:

[0170] 5.11, the compensation part can directly become a conversion and constraint type network transfer processing circuit. The third output terminal series can be directly connected to the device related to the controlled object to produce a form of controlling 100 objects. A conversion and constraint type network transfer processing circuit is also explained and analyzed based on the output principle of this compensation part.

[0171] 5.12. The applicant has many achievements, and a conversion and constraint type network transfer processing circuit is only one of them. In the existing achievements, the first and second types of output terminal series of the decoding conversion and constraint part can become the main components. On this basis, this part can make some supplements.

[0172] 5.13. Through the analysis in this section, we can see that the logic of the cooperation between the various parts of the conversion and constraint network transfer processing circuit is correct, and secondly, it can be seen that there will be no interference when operating each program.

[0173] 5.2. Description of the composition and connection method of the compensation part:

[0174] This part is composed of a plurality of complementary logic AND circuits with the properties of logic AND circuits, each of which has a plurality of input terminals. In the example, the complementary logic AND circuit is expressed in the form of an AND gate.

[0175] Each AND gate has one or more input terminals that are connected to a signal. Many AND gate circuits can form a variety of connection methods. This example introduces one of them.

[0176] It is composed of 100 AND gate circuits, which are directly divided into 10 "groups", and each "group" is composed of 10 AND gate circuits. So there are 100 AND gate circuits in total, and the output end of each AND gate circuit becomes the output end of this part, which is also a conversion and constraint type network transfer processing circuit. So a conversion and constraint type network transfer processing circuit has a total of

[0177] 100 output terminals. Only the first and tenth groups are shown in the figure, and the other groups are ellipsised.

[0178] Each AND gate circuit has multiple input terminals, each of which is connected to a signal. The connection method of multiple signal input terminals is as follows.

[0179] 5.21. “Conversion Input Terminal”

[0180] That is, one end of the input of the 10 AND gates in each group is connected together to become a "conversion input end" of the "group".

[0181] The ten groups have ten "conversion input terminals" in total. The connection method is that the "conversion input terminals" of the ten groups are respectively connected in sequence to one of the 0-9 ten-bit output terminals of the decoding conversion part.

[0182] 5.22, “Number input terminal”.

[0183] That is, two terminals of the inputs of the ten selection circuits in each group are respectively connected to one of the output terminals 0-9 in the output series of the decoding constraint part.

[0184] The connection method of this type of input terminal is further described as follows:

[0185] The second input terminal of the first AND gate circuit in each group is connected to the output terminal of the decoding constraint part which translates "1".

[0186] Connect the second input terminal of the second AND gate circuit of each group to the output terminal of the decoded constraint that translates "2".

[0187] Connect the second input terminal of the third AND gate circuit in each group to the output terminal of the decoding constraint that translates "3"... Use the same method to connect the second input terminals of the AND gate circuits in all groups.

[0188] 5.23. “Backup Input Port”

[0189] That is, the three or more input terminals in each group are connected together to form one or more new input terminal series of this part; a conversion and constraint type network transmission processing circuit refers to such input terminals as backup input terminals. Connected to the new function output terminal related to the applicant.

[0190] 5.3. Explanation of the logical points formed by the supplementary part:

[0191] 5.31. For each operation, because the decoding conversion and constraint parts will only produce a unique output terminal respectively, and this part is a logic and circuit, among the many output terminals of this part, only a unique output terminal can have an output.

[0192] 5.32. During the first operation of the category program, the decoding constraint part is closed and no interference signal is generated

[0193] 5.33. The logic and circuit in this section will have output only when all conditions are met at the input; conversely, the numbering procedure can also be implemented after the constraints are met.

[0194] 5.4. Make up for the final connection of some output terminals:

[0195] 5.41. Method 1: This part of the output end can be directly connected to the controlled equipment connected to the controlled object.

[0196] 5.42. Method 2: Using remote control, the simplest way is to connect each output end of a conversion and constraint type network transmission processing circuit to a bit input data line in each coding integrated circuit. Since a conversion and constraint type network transmission processing circuit has 100 independent AND gate output ends, 100 objects can be controlled. At present, the characteristic of many coding integrated circuits is that when the data input line is in a high state, the corresponding position line will generate transmission.

[0197] 6. Password part (as shown in Figure 3 and Figure 4)

[0198] 6.1、The function of password part:

[0199] The telephone number of the telephone set of the conversion and constraint type network transmission processing circuit can become the first password of the conversion and constraint type network transmission processing circuit. And the most important thing is that the user can set and change the multi-digit password value at any time, and this part completes this function.

[0200] 6.2. Brief description of the technical solution for the password part:

[0201] 6.21. The password part includes a password setting unit and a password memory unit (as shown in FIG. 3 ).

[0202] The connection relationship between the two units described in the password part is that all the input terminal series of the password setting unit are the input terminal series of this part, which are connected to the decimal output terminal series of the decoding part, and all the output terminal series of the setting unit are correspondingly connected to the input terminal series of the password memory unit.

[0203] The password setting unit is composed of a plurality of movable connection elements with movable switching properties. Ten movable connection elements form a unit. The setting unit contains a plurality of units. The input terminals of the ten movable connection elements in each unit are the input terminal series of the unit and the password part, and are respectively connected to the decimal output terminal series 0-9 output terminals of the decoding part of a conversion and constraint type network transmission processing circuit. The output terminals of the ten movable connection elements of each unit are connected together to form a single-bit output terminal of the unit, and the output terminals of multiple units form a plurality of password output terminal series of the setting unit.

[0204] The password memory unit is composed of a plurality of circuits of memory circuit nature and a selection circuit. The connection method is that the signal input end of the first memory circuit and the second input end of the selection circuit are the input end series of the password memory unit. The first input end of the selection circuit is connected to the output end of the previous level memory circuit, and the output end of the selection circuit is connected to the input end of the current level memory circuit.

[0205] The output terminal of the last memory circuit is the output terminal of the password part, which is connected to one of the constraint input terminal series of the decoding constraint part in a conversion and constraint type network transfer processing circuit.

[0206] 6.22. The password setting unit adopts an electronic small switch to replace the movable plate of the password setting unit. The structure of the electronic small switch is that each electronic small switch contains ten micro switches that can be turned on and off. Each electronic small switch constitutes a password setting unit.

[0207] 6.23. The password part also includes a password locking unit (as shown in Figure 4), which is composed of a differential input circuit, a timing circuit and a phase circuit that meets the connection requirements, which are connected to each other. The input end of the differential circuit is connected to a certain point of the logic start power supply of a conversion and constraint network transmission processing circuit, the output end of the differential circuit is connected to the signal input end of the timing circuit, the output end of the timing circuit is connected to the input end of the phase circuit, the output end of the phase circuit is the output end of the password locking unit, the reset input end of the timing circuit is connected to one of the output ends in the decimal output end series of the decoding part; the output end of the password locking unit is connected to the control point of the reset input end of the memory circuit in the password memory unit.

[0208] 6.3. Working logic and technical points of password setting unit:

[0209] 6.31. The small switch in the password setting unit can be flexibly closed and connected. According to the composition and connection relationship of the switch unit, when a micro switch in each unit is closed, it means that this unit has selected one of the digits in the 0-9 series. Therefore, the specific digits of the password can be flexibly adjusted.

[0210] 6.32. A small electronic switch can form a password setting unit, so you can customize the number of digits in the password.

[0211] 6.33. When the signal at the password input end is correct, that is, it matches the password signal value selected by the password setting switch.

[0212] 6.34. According to the connection relationship between the electronic memory circuit and the selection circuit in the second unit of the password part, that is, the electronic memory circuit, it can be known that only after the previous memory circuit generates memory and the password signal at the input end of this level is double correct, the memory circuit of this level will have memory characteristics such as high-bit output. In this way, the final result of the repeated continuous memory, constraint, and memory... logical relationship is that only when all the operation passwords and the set password values ​​match the sequence, the last memory circuit will have memory characteristics such as high-bit output. Otherwise, there is no output, so the standard for a completely correct password is that the password must be correct in both numbers and sequence.

[0213] 6.35. After all the passwords in the password part are correct, the decoding constraint part has the necessary conditions for output, that is, the necessary conditions for the numbering program.

[0214] 6.36. Since the output of the password part is a self-maintaining memory circuit, once it is output, it will not be affected by the classification and numbering program operations.

[0215] 6.37. The password lock circuit is formed on the principle that the password operation must be completed within a certain time range. After the time is exceeded, the memory circuit resets the input terminal and there is a signal input. At this time, even if the correct password is entered again, the memory circuit has been reset, and the output terminal cannot output the correct valid signal such as a high position. The function is to prevent others from guessing the password for a long time to enhance confidentiality. The logical relationship principle of this unit is: when the system is turned on, the timing circuit starts to start timing. When the time is up, the memory circuit will be reset, so the password operation can only be controlled within a certain time range. If the user operates normally, first, the password will not time out, and second, in the 100 control objects, although the total time required is long, but because it is a group operation, the time for each group operation is not much. After completing each group operation, a key such as the # key will be pressed to confirm, and the password timing circuit will be reset to start timing again, providing a new time for the next program.

[0216] VII. Operational procedures and logic points of a conversion and constraint-type network transfer processing circuit

[0217] 7.1. First, press a key, such as the "*" key, to put the decoding constraint part in a closed state. That is, no interference model will be generated during the password setting and category program operation.

[0218] 7.2. The operation complies with all correct passwords.

[0219] 7.3. Operation Category Procedure:

[0220] If you press the key "3", it means that among the ten groups of categories from 0 to 9, the "3rd" category is selected.

[0221] 7.4. Confirm the operation category program and start the numbering program simultaneously:

[0222] Based on the previous point 8.22, if you press the "#" key to confirm, it means that the last confirmed category is "3", not the other number keys pressed before. At this time, the decoding constraint part meets the conditions synchronously and is in a workable state without sealing the door.

[0223] 7.5. Operation number procedure:

[0224] If you press key "5" again based on the previous one, the final selection is the controlled object numbered "5" in category "3". At this time, among the 100 AND gate outputs, only the AND gate outputs in category 3 and specifically number 5 are high.

[0225] 7.6. After completing the first category of ten specific numbered numbers, repeatedly operate the * and # keys to allow the decoding conversion and constraint parts to continuously change their states, generating new programs one by one until all 100 control objects are completed.

[0226] 7.7. During the repeated operation of the previous item, since the output end of the password part is always in a self-maintaining memory state, no logical disorder will occur.

[0227] 7.8. After completing the operations of each group of ten objects, the lock section in the password section is tracked and cleared to provide the time required for the new program.

[0228] 8. Explanation of relevant points

[0229] 8.1 A conversion and constraint type network transmission processing circuit only completes the call command to 100 control objects. The control of the object state is completed by other results.

[0230] 8.2. The decoding constraint part uses the circuit input of the AND gate, because only the digital signals of 1 and 0 need to be connected. This is very conducive to the secondary design of "refined engineering" and "optimized engineering".

[0231] 8.3. A circuit that controls 100 objects can be formed, and part of its output can also be used to form a series of control circuits that control less than 100 objects.

[0232] Various embodiments of a conversion and constraint-type network transfer processing circuit have been described above. The above description is exemplary, not exhaustive, and is not limited to other described embodiments.

[0233] The terms used in this article are intended to best explain the principles of each embodiment, rather than to limit it. Devices with the same logical functions but different names also fall within the scope of protection.

[0234] It should be understood that a conversion and constraint type network transfer processing circuit is not limited to the structure described above and shown in the drawings, and the units therein can be freely combined and formed by certain modifications and changes, which also fall within the scope of protection.

Claims

1. A conversion and constraint type network transfer processing circuit, characterized in that: It includes decoding part, decoding conversion part, decoding constraint part and dual control part; The decoding part includes a decoding unit and a decoding unit; The decoding unit is composed of a decoding integrated circuit and an external circuit. The decoding unit is an electronic decoding circuit that converts binary into decimal. The input end of the decoding integrated circuit is the input end of this part, which is connected to a certain point of the audio system of the matching telephone. The output end series of the decoding integrated circuit is the binary output end series of this unit and this part, which are respectively connected to the input end series of the decoding conversion part and the input end series of the decoding constraint part, and send signals that can be processed into two new meanings to these two parts respectively. The output end series of the decoding integrated circuit is also connected to the input end series of the decoding unit described in this part. The output end series of the decoding unit is the decimal output end series of this part, which is connected to the input end of the dual control part and outputs a state control signal to the dual control part: The decoding conversion part includes a conversion circuit unit and a conversion decoding integrated circuit unit with decoding properties. The signal input terminal series of the decoding conversion part is connected to the binary output terminal series in the decoding part. The conversion control terminal of the decoding conversion part is connected to the output terminal of the dual control part and is controlled by the conversion of the dual control part. The multi-bit output terminal of the decoding conversion part is a first-type signal output terminal series of a conversion and constraint type network transmission processing circuit. The decoding constraint part includes a constraint circuit unit and a constraint decoding integrated circuit unit. The signal input terminal series of the decoding constraint part is correspondingly connected to the binary output terminal of the decoding part to receive the signal decoded by the decoding part. The decoding constraint part also has a constraint input terminal series. One of the constraint input terminal series is connected to the corresponding output terminal of the dual control part to accept the constraint control of the dual control part. The multi-bit output terminal of the constraint decoding integrated circuit unit becomes a second type of output terminal series of a conversion and constraint type network transmission processing circuit. The dual-control part includes a dual-control memory circuit having the properties of a memory circuit. The input end of the dual-control part is connected to the decimal output end of the decoding part. The output end of the dual-control part is respectively connected to the conversion input end of the decoding conversion part and one of the constraint input end series of the decoding constraint part. The dual-control control signal is sent to the decoding conversion part and the constraint part: The output terminal series of the decoding conversion part and the decoding constraint part are two output terminal series of a conversion and constraint type network transfer processing circuit.

2. The conversion and constraint type network transfer processing circuit according to claim 1, characterized in that: It also includes a password part, which includes a password setting unit and a password memory unit. The connection relationship between the two units in the password part is: all the input terminal series of the password setting unit are the input terminal series of this part, connected to the decimal output terminal series of the decoding part, and all the output terminal series of the password setting unit are correspondingly connected to the input terminal series of the password memory unit: the password setting unit includes a plurality of movable connection elements with movable on-off properties; the ten movable connection elements constitute a password setting unit, and the password setting unit contains a plurality of password setting units. The input terminals of the ten movable connection elements in each password setting unit are the input terminal series of the password setting unit and the password part, and are respectively and correspondingly connected to the output terminals of the decimal output terminal series 0-9 of the decoding part, and the output terminals of the ten movable connection elements in each password setting unit are connected together to become a single-bit output terminal of the password setting unit, and the output terminals of the plurality of password setting units constitute the output terminal series of the password setting unit; The password memory unit includes multiple memory circuits and selection circuits, which are connected in the following manner: the signal input end of the first memory circuit is the first input end of the password memory unit, which is connected to the first output end of the password setting unit; the first input end of the first selection circuit is connected to the output end of the first memory circuit; the second input end of the first selection circuit is the second signal input end of the password memory unit; the output end of the first selection circuit is connected to the signal input end of the second memory circuit; the first input end of the second selection circuit is connected to the output end of the second memory circuit; the second input end of the second selection circuit is the third signal input end of this unit; the output end of the second selection circuit is connected to the signal input end of the third memory circuit; all the selection circuits and memory circuits are connected in the same way; the output end of the last memory circuit is the output end of the password part, which is connected to one of the constraint input end series of the decoding constraint part to send out a password constraint signal.

3. The conversion and constraint type network transfer processing circuit according to claim 2, characterized in that: The password setting unit is composed of multiple small electronic switches, each of which is a password setting unit. Each small electronic switch contains ten micro switches that can be turned on and off. The input ends of the ten micro switches in the multiple small electronic switches are the input end series of the password setting unit and the password part. The output ends of the ten micro switches in each small electronic switch are connected together to form the output end of a unit. The output ends of the multiple small electronic switches constitute the output end series of the password setting unit.

4. The conversion and constraint type network transfer processing circuit according to claim 2, characterized in that: The password part also includes a password locking unit, which includes a differential circuit, a timing circuit and a phase circuit composed of a third inverter. The output end of the timing circuit is connected to the input end of the phase circuit. The output end of the phase circuit is the output end of the password locking unit. The input end of the differential circuit is connected to a certain point of a logic start power supply of a conversion and constraint type network transmission processing circuit. The output end of the differential circuit is connected to the signal input end of the timing circuit; the reset input end of the timing circuit is connected to a certain output end in the decimal output end series of the decoding part; the output end of the password locking unit is connected to the reset input end of the memory circuit in the password memory unit.

5. The conversion and constraint type network transfer processing circuit according to claim 1, characterized in that: The decoding conversion part includes a conversion circuit unit with delay circuit properties and a conversion decoding integrated circuit unit with decoding properties; the conversion circuit unit is composed of four independent delay circuits, the input ends of the four independent delay circuits are respectively connected to the binary output end series of the decoding part, and the output ends of the four independent delay circuits are respectively connected to the four-bit input ends of the conversion decoding integrated circuit unit; the conversion decoding integrated circuit unit has a working enable end that can control the conversion decoding integrated circuit to the required logical working state, and the working enable end is the conversion input end of the decoding conversion part, connected to the output end of the dual control part, and the output end series of the conversion decoding integrated circuit unit is this part and also a first type of output end series of a conversion and constraint type network transmission processing circuit.

6. The conversion and constraint type network transfer processing circuit according to claim 5, characterized in that: The delay circuit in the decoding conversion part is composed of a passive RC integration circuit.

7. The conversion and constraint type network transfer processing circuit according to claim 1, characterized in that: The decoding constraint part includes a constraint circuit unit and a constraint decoding integrated circuit unit. The constraint circuit unit is a circuit of logic and circuit nature. The constraint decoding integrated circuit unit is a decoding integrated circuit: the signal input terminal series of the constraint decoding integrated circuit is connected to the binary output terminal series of the decoding part to receive the signal decoded by the decoding part. The constraint decoding integrated circuit output terminal series is also an output terminal series of a conversion and constraint type network transmission processing circuit. The constraint decoding integrated circuit has a working use terminal that can control the constraint decoding integrated circuit to a required logical working state. The working use terminal of the constraint decoding integrated circuit is connected to the output terminal of the constraint circuit. The constraint circuit has multiple input terminal series of logic and nature, one of which is a constraint input terminal connected to the output terminal of a dual control part of a conversion and constraint type network transmission processing circuit to receive a program constraint signal issued by the dual control part.

8. The conversion and constraint type network transfer processing circuit according to claim 1, characterized in that: The dual-control part includes a dual-control memory circuit with the properties of a memory circuit. The signal input end and the reset input end of the dual-control part are respectively connected to two or more output ends in the decimal series of the decoding part. One or two output ends of the dual-control part are respectively connected to the conversion input end of the decoding conversion part and the constraint input end of the decoding constraint part; a dual-control control signal is sent to the decoding conversion and constraint parts.

9. The conversion and constraint type network transfer processing circuit according to claim 8, characterized in that: The dual-control memory circuit in the dual-control part is composed of a first inverter and a second inverter; the input ends of the first inverter and the second inverter are respectively connected in series through isolation resistors, and then connected in series with the output ends of the first inverter and the second inverter; the input ends of the first inverter and the second inverter are respectively two input trigger ends of the circuit, which are respectively connected to two or more input ends of the decimal output end series of the decoding part, and the two output ends of the first inverter and the second inverter are the two output ends of the dual-control part.

10. The conversion and constraint type network transfer processing circuit according to claim 1, characterized in that: The conversion and constraint type network transmission processing circuit also includes a compensation part, which is composed of multiple compensation logic and circuits with logic and properties. The compensation logic and circuit is directly divided into multiple groups, and each of the groups is composed of multiple compensation logic and circuits. The multiple compensation logic and one-bit input terminals in each group form an input terminal series. Each group has multiple input terminal series. Each one-bit input terminal of each logic and in each group is connected to one type of input terminal. Each group contains a conversion input terminal series. The conversion input terminals of each group are respectively connected to one-bit output terminals of the output series of the decoding conversion part: two terminals of the multiple compensation logic and inputs in each group are respectively connected to one-bit output terminals in the output terminal series of the decoding constraint part. The multiple compensation logic and circuit output terminals are this part and also the third output terminal series of a conversion and constraint type network transmission processing circuit.

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