Integrated circuit

Abstract

Various embodiments of the utility model relate to an integrated circuit. The integrated circuit comprises a substrate; a well formed over a portion of the substrate; a stack structure formed over the first portion of the well; a doped epitaxial structure formed over a second portion of the well adjacent to the stack structure and below a plane defined by an upper surface of the first portion of the well; and a source / drain region formed over the doped epitaxial structure.

Description

Technical Field

[0001] The embodiment of the utility model relates to an integrated circuit. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are made by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a substrate, and patterning the various material layers using photolithography to form circuit components and components on the various material layers. As the semiconductor industry moves toward nanotechnology process nodes in pursuit of higher device density, improved performance, and lower costs, challenges from both manufacturing and design issues have led to the development of a large number of three-dimensional designs, including, for example, Metal-Oxide-Silicon Field Effect Transistor (MOS-FET), Field Effect Transistor (FET), Fin Field Effect Transistor (FinFET), Gate-All-Around (GAA) devices (nanowires), and Multi-Bridge Channel Field Effect Transistor (MBCFET) devices (nanosheets (NS)).

[0003] Integrated circuit (IC) manufacturing processes are generally divided into front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing. FEOL processes generally include those processes associated with fabricating functional components such as transistors and resistors in or on a semiconductor substrate. For example, FEOL processes generally include forming isolation features, gate electrodes and dielectrics, and source and drain features (also referred to as source / drain or S / D features). BEOL processes generally include those processes associated with fabricating multilayer interconnect (MLI) features that interconnect functional IC components and structures fabricated during FEOL processing to provide connections to and enable operation of the resulting IC device. Process modifications and structural modifications used to reduce process complexity and / or size of features (associated with, for example, gate electrodes and related structures and multilayer interconnect structures) tend to reduce the overall size of the IC device, improve cycle time, and / or increase yield and reliability. Utility Model Content

[0004] One aspect of the utility model provides an integrated circuit. The integrated circuit includes: a substrate, a well, a stacked structure, a doped epitaxial structure, and a source / drain region. The well is formed on a portion of the substrate. The stacked structure is formed on a first portion of the well. The doped epitaxial structure is formed on a second portion of the well adjacent to the stacked structure and is located below a plane defined by an upper surface of the first portion of the well. The source / drain region is formed on the doped epitaxial structure.

[0005] Another aspect of the utility model provides an integrated circuit. The integrated circuit includes: a semiconductor substrate, a well region, a stacked structure, a first groove, an epitaxial layer, and a source / drain (S / D) structure. The well region has a first dopant concentration and is located on the semiconductor substrate. The stacked structure is located on a first portion of the well region. The first groove is located in a second portion of the well region. The epitaxial layer is located in the first groove, wherein the epitaxial layer includes a first implanted dopant. The source / drain (S / D) structure is located on the epitaxial layer.

[0006] Another aspect of the utility model provides a method for manufacturing an integrated circuit device. The method includes: forming a well region having a first dopant concentration on a semiconductor substrate. The method also includes: forming a stacked structure on a first region of the well region. The method also includes: etching a first portion of the well region adjacent to the stacked structure to form a first groove and a mesa region. The method also includes: filling the first groove with an undoped epitaxial layer. The method also includes: implanting a first dopant substance of a first dopant dose into the undoped epitaxial layer with an implantation energy to form a first doped epitaxial region. The method also includes: forming a source / drain (S / D) structure on the first doped epitaxial region, wherein the second dopant concentration in the first doped epitaxial region is sufficient to cause the device junction to deviate from the stacked structure.

[0007] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1F is a cross-sectional view of a semiconductor device during a manufacturing process according to some embodiments.

[0009] Figure 2 is a cross-sectional view of a semiconductor device during a manufacturing process according to some embodiments.

[0010] Figure 3 is a table of implantation parameters according to some embodiments.

[0011] Figure 4 is a flow chart of a manufacturing process for producing an IC device according to some embodiments.

[0012] Figure 5 is a schematic diagram of a system for fabricating a FET device according to some embodiments.

[0013] Figure 6 is a flow chart of IC device design, IC device manufacturing, and IC device programming according to some embodiments.

[0014] Figure 7 is a schematic diagram of a processing system for fabricating IC devices according to some embodiments. DETAILED DESCRIPTION

[0015] The present invention provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. It is expected that there are other components, values, operations, materials, arrangements, etc. For example, in the following description, forming a first feature on a second feature or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0016] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] The structures and methods described in detail below generally relate to improved structures, designs, and methods of manufacturing IC devices that include source / drain regions disposed proximate to other regions (e.g., mesa regions of a well) that provide one or more potential current leakage paths due to drain induced barrier lowering (DIBL). Excessive leakage currents tend to degrade the yield and / or performance of the resulting integrated circuit. Therefore, in some embodiments, employing structures and methods that tend to reduce or eliminate such leakage currents enables the size of functional components to be reduced by reducing insignificant physical separations and / or interruptions of leakage paths that degrade the yield and / or performance of the resulting integrated circuit.

[0018] Although the structures and methods will be discussed with respect to nanosheet (NS) devices (e.g., multi-bridge channel field effect transistors (MBCFETs)), the structures and methods are not limited thereto, but are also suitable for inclusion in the manufacturing processes of other types and other configurations of IC devices, including but not limited to bulk semiconductor devices (bulk semiconductor devices) and silicon-on-insulator (SOI) devices, metal oxide silicon field effect transistors (MOSFETs or FETs), fin field effect transistors (FinFETs), nanosheet field effect transistors, nanowire field effect transistors, and gate-all-around (GAA) devices.

[0019] Figure 1A is a cross-sectional view of a portion of an integrated circuit device at an intermediate operation during a fabrication process according to some embodiments. Figure 1A The IC device 100A in the embodiment includes a well region 102 formed in or on a semiconductor substrate 101 and a stacked structure 104 formed above a mesa region 106 of the well region 102. The term "stacked structure 104" is used as an inclusive reference to various materials and structures arranged in a composite vertical stack above the mesa region 106 at various stages of the manufacturing operation, and the stacked structure 104 includes but is not limited to a dummy gate structure, a gate structure, a gate dielectric, a channel region, a sidewall, a hard mask, and a spacer. Then, the portion of the well region 102 not covered by the stacked structure 104 is etched to form a recessed region 108 on the opposite side of the remaining mesa region 106 of the well region 102.

[0020] In some embodiments, the etching parameters used to form the recessed region 108 will cause some undercutting of the stacked structure 104 and increase the possibility of parasitic leakage at this point. In some embodiments, an anti-doping region 110 is formed in the upper portion of the well region 102 adjacent to the stacked structure 104, below the recessed region 108, and below the edge of the stacked structure 104 using an anti-doping implant. In some embodiments, the anti-doping implant dopant concentration is between 5E 18 Per cubic centimeter (cm -3 ) and 5E 19 per cubic centimeter, for example, 1E 19 per cubic centimeter. In some embodiments, the counter-doping implant dopant concentration changes the location and / or sensitivity of junctions associated with parasitic leakage to a level that satisfies predetermined performance parameters. In some embodiments, the dopant, dopant concentration, and implantation energy are selected to control the positioning of transistor junctions relative to mesa region 106 as a means of suppressing current leakage.

[0021] In some embodiments, the etching process for forming the mesa region 106 is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etching solution. In some embodiments, the liquid chemical etching solution includes one or more etchants, such as citric acid (C 6 H 8 O 7 ), hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), sulfuric acid (H 2 SO 4 ), hydrochloric acid (HCl), acetic acid (CH 3 CO 2 H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H 3 PO 4 ), ammonium fluoride (NH 4 F), potassium hydroxide (KOH), ethylenediaminecatechol (EDP), TMAH (tetramethylammonium hydroxide) or a combination thereof.

[0022] In some embodiments, the etching process is a dry etching process or a plasma etching process performed using a halogen-containing reactive gas that is excited by an electromagnetic field to dissociate into ions that are then accelerated toward the material being etched. The reactive gas or etchant gas includes, for example, CF 4 , SF 6 NF 3 , Cl 2 , CCl 2 F 2 、SiCl 4 , BCl 2 and combinations thereof, but other semiconductor material etchant gases are also contemplated to be within the scope of the present disclosure.

[0023] In some embodiments, a series of alternating silicon (Si) layers 112 and silicon germanium (SiGe) layers 114 are fabricated during formation of the stacked structure 104. In some embodiments, a series of etching operations and deposition operations are then used to remove a portion of the silicon germanium layer 114 to form a recessed region (not shown) on the sidewalls, with the top and bottom of the recessed region defined by the adjacent silicon layer 112. In some embodiments, a dielectric spacer 116 (e.g., silicon dioxide, silicon nitride, or a combination thereof) is then formed in the recessed region, leaving the lateral surface of the silicon layer 112 exposed. In some embodiments, inserting more layers in the series of alternating silicon (Si) layers 112 and silicon germanium (SiGe) layers 114 tends to increase the drive current, but the associated increase in contact resistance with the underlying layers via the adjacent source / drain (S / D) regions limits the gain in drive current and weakens the advantage of more layers. In some embodiments, the number of nanosheets utilized in the stacked structure is set between 3 and 4 layers to provide a satisfactory tradeoff between performance and manufacturability, but other embodiments also include different numbers of nanosheets.

[0024] In some embodiments, the dielectric spacer 116 is formed using a material having a high dielectric constant (high-k) (eg, κ>3.9). In some embodiments, the high-k dielectric material includes HfO 2 、TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 、ZrSiO 2 、LaO、AlO、ZrO、TiO、Ta 2 O 5 , Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N 4 、SiO x N yThe insulating / dielectric material may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), thermal oxidation, self-aligned monolayer (SAM) deposition, and / or one or more other suitable methods.

[0025] Figure 1A The IC device 100A in the embodiment includes a series of nanoplates (NP) or nanosheets (NS) including a silicon layer 112 embedded in a stacked structure 104. In some embodiments, the stacked structure 104 includes one or more conductive materials selected from the group including polysilicon, metals, metal alloys and / or metal silicides. In some embodiments, the conductive materials will include various combinations of materials (including, for example, liner layers, diffusion barrier layers, wetting layers, adhesion layers, metal filler layers and / or one or more other suitable layers) to improve device performance and / or device life. In some embodiments, the conductive materials will be selected from Si, Ge, SiGe, Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni and other conductive materials suitable for use in combination with polysilicon, silicides and combinations and alloys thereof.

[0026] Figure 1B According to some embodiments, Figure 1A A cross-sectional view of a portion of an integrated circuit device after the operations shown and that may be used in intermediate operations in fabricating the IC device. Figure 1B1 is a cross-sectional view of an IC device 100B after depositing a non-doped silicon epitaxial (NSE) layer 118 in the recessed region 108. In some embodiments, a central region of the epitaxial layer 118 is recessed relative to both a peripheral region of the epitaxial layer and an upper surface of the mesa region 106 of the well region 102. In some embodiments, both the central region and the peripheral region of the epitaxial layer 118 are recessed relative to an upper surface (not shown) of the mesa region 106 of the well region 102. A first distance between a first plane defined by the upper surface of the mesa region 106 of the well region 102 and a central surface region of the epitaxial layer 118 defines an NSE recess height (RH) 109. In some embodiments, the recessed arcuate surface of the recessed region 108 places the halo implant deeper in the well region 102. In some embodiments, the recessed arcuate surface of the recessed region in combination with the tilted implant places a portion of the halo implant further into the mesa region 106 and below the undercut edge portion of the stacked structure 104. If the recess 108 is too shallow, the halo implant will be placed above the thicker portion of the well region 102 and will not tend to extend below the edge of the stack 104 even with tilted implantation. If the recess is too deep, the well region 102 will be excessively thinned and the effect of the halo implant near the mesa region 106 will be reduced. The second distance between the central surface region of the epitaxial layer 118 and the lower surface of the epitaxial layer 118 defines the NSE thickness 111 (T NSE ).

[0027] Figure 1C According to some embodiments, Figure 1B A cross-sectional view of a portion of an integrated circuit device after the operations shown and that may be used in intermediate operations in fabricating the IC device. Figure 1C 1 is a cross-sectional view of an IC device 100C in which a halo implantation is performed to implant one or more dopant species 120 into the epitaxial layer 118 and form a doped halo region 122 in the epitaxial layer 118. In some embodiments, the implanted species is selected from the group consisting of an n-type dopant and a p-type dopant, including, for example, arsenic (As), phosphorus (P), antimony (Sb), boron (B), boron difluoride (BF 2 ), gallium (Ga), and combinations thereof. In some embodiments, the combination of implant species and implant energy is selected to produce an epitaxial thickness less than 111 (T NSE ) implantation range, thereby ensuring that most of the implantation dose remains in the epitaxial layer 118.

[0028] By confining the majority of the implant dose to the epitaxial layer 118, the halo implant utilized in some embodiments limits or eliminates implant-induced damage in the well region 102 while still providing a doping level that tends to suppress leakage current flow into the well region. In some embodiments, the implant species and implant energy are selected to produce a thickness of less than NSE 111 (T NSE ). In some embodiments, the implant range is reduced to slightly less than the NSE thickness 111 to maintain a residual undoped buffer zone (not shown) in the epitaxial layer 118 below the doped halo region 122. In some embodiments, the implant species and implant energy are selected to generate a thickness close to the NSE thickness 111 (T NSE ) implantation range, thereby providing a doped halo region 122 of increased thickness while still retaining a majority of the dopants within the epitaxial layer 118.

[0029] In some embodiments, the halo implantation is performed perpendicular to a plane defined by the surface of the substrate 101. In some embodiments, at least a portion of the halo implantation is performed as a tilted implantation at an angle of up to 15° offset from the vertical direction (i.e., a tilt angle that satisfies the expression 0<tilt angle≤15°). In some embodiments, utilizing a tilted implantation technique during the halo implantation enables an increased portion of the implanted dopant material 120 to be placed adjacent to or within an upper peripheral region of the mesa region 106. The actual tilt angle used during the halo implantation will depend to some extent on the aspect ratio of the existing structures on the substrate, with lower tilt angles used for structures with higher aspect ratios and higher tilt angles used for structures with lower aspect ratios. A range of tilt angles up to 15 degrees (i.e., 0<tilt angle≤15°) will be suitable for a large number of embodiments.

[0030] Figure 1D According to some embodiments, Figure 1C A cross-sectional view of a portion of an integrated circuit device 100D after the operations shown and which may be used in intermediate operations for manufacturing an IC device. In some embodiments, a source / drain (S / D) structure 124 is epitaxially grown outwardly from the exposed sidewalls of the Si layer 112 and the dielectric spacer 116 and / or upwardly from the upper surface of the doped halo region 122, providing both the S / D structure 124 and structural support for the stack structure 104. The SiGe layer in the nanosheet stack is then selectively removed, exposing the Si channel. A subsequent atomic layer deposition (ALD) operation introduces a gate oxide stack, potentially with a variety of work functions for device Vt supply. In some embodiments, a subsequent ALD operation provides gate material and completely encapsulates the nanosheet stack. As Figure 1DAs reflected, in some embodiments, placing the doped halo region 122 between the source / drain structure 124 and the mesa region 106 tends to suppress parasitic current leakage 126 along the path between the source / drain structure 124 and the mesa region 106 of the transistor. In some embodiments, the advantage of suppressing or eliminating the parasitic current leakage path 126 is reflected in an improvement in the mesa pass rate (MPR) by up to 20%.

[0031] Figure 1E According to some embodiments, Figure 1C A cross-sectional view of a portion of an integrated circuit device 100E after the operations shown and which may be used in intermediate operations in the manufacture of an IC device. In some embodiments, source / drain (S / D) structures 124 are epitaxially grown outwardly from the exposed sidewalls of the silicon layer 112 and / or upwardly from the upper surface of the doped halo region 122 to provide both the S / D structures 124 and structural support for the stacked structure 104. Figure 1E The device shown also includes an optional additional dielectric layer 127, which is located between the upper surface of the doped halo region 122 and the lower surface of the source / drain structure 124. In some embodiments, this additional dielectric layer 127 provides additional separation and current suppression between the doped halo region 122 and the source / drain structure 124. In some embodiments, the additional dielectric layer 127 can be formed of a silicon nitride (SiN) layer having a layer thickness of about 3 nanometers to 6 nanometers. In some embodiments, the thickness of the additional dielectric layer 127 is selected to avoid forming a layer that does not cover the silicon surface and interferes with subsequent processing.

[0032] Some embodiments differ in the timing of gate electrode construction and can be broadly divided into 1) a gate-first process and 2) a gate-last process (also referred to as a replacement gate process). In both the gate-first process and the gate-last process, the goal is to produce IC devices that consistently exhibit a predetermined work function and threshold voltage for both N-type metal-oxide-semiconductor (NMOS) and P-type metal-oxide-semiconductor (PMOS) transistors. Studies have shown that the threshold voltage of an IC device is highly dependent on both the properties of the deposited materials and the subsequent processing steps to which these materials are exposed.

[0033] Figure 1E and Figure 1F 1 is a cross-sectional view of an alternative intermediate operation for producing different embodiments of integrated circuit devices 100E and 100F including doped halo regions 122. Figure 1E and Figure 1FIn the embodiment of FIG. 1 , the doped halo region 122 provides both physical and electrical separation between the mesa region 106 of the well and the source / drain structure 124 , which tends to suppress or eliminate current leakage. Figure 1E and Figure 1F Additional details are also provided regarding embodiments of the configuration of certain conductive components comprising the stacked structure 104, including, for example, the use of a dielectric layer 130, a high dielectric constant material layer 132, and a main conductive component 134 (e.g., a gate electrode) for improving the performance and robustness of a final integrated circuit device constructed using the doped halo region 122.

[0034] Figure 2 is a cross-sectional view of an intermediate operation reflecting a non-uniform distribution of the halo implanted dopant species 120 within the doped halo region 122 of the integrated circuit device 200. In some embodiments, the combination of dopant species and implantation energy is selected to provide a predetermined distribution throughout the initial undoped epitaxial layer 118 when the initial undoped epitaxial layer 118 is converted into the final doped halo region 122 by the halo implantation operation.

[0035] In some embodiments, the combination of dopant species and implantation energy is selected to provide a more heavily doped upper region 122a and more lightly doped middle and / or lower regions 122b of the doped halo region 122, the upper region 122a having, for example, about 1E 20 The final dopant concentration per cubic centimeter is about 5E in the middle and / or lower region 122b. 19 per cubic centimeter. Higher than 1E 20 A final dopant concentration of greater than about 5E per cubic centimeter requires additional processing time, does not provide any additional benefit, and may result in a higher concentration at the well region 102 / doped halo region 122b region boundary. 19 The lower region dopant concentration per cubic centimeter requires additional processing time, causes additional implant damage, and does not significantly increase the separation of the displaced junction 128b from the mesa region 106. In some embodiments, the final dopant concentration continues to decrease in such regions of the epitaxial layer 118 closer to the well and / or any counter-doping implant species introduced in the surface region of the well 102. In some embodiments, the final epitaxial layer doping profile includes undoped or very lightly doped regions and / or counter-doping implant regions adjacent to the interface between the epitaxial layer 118 and the well 102.

[0036] In some embodiments, the proximity of the more heavily doped halo region 122 within the epitaxial layer 118 tends to shift or offset the parasitic transistor junction formed between the source / drain region 124 and the mesa region 106 beneath the first / lowest / bottom nanosheet 112a. Figure 2As reflected, the addition of the more heavily doped halo region 122 tends to shift the transistor junction toward the doped halo region 122 and away from the original or unadjusted junction location 128a proximate the mesa region 106 by a shift distance 129 to a second or adjusted junction location 128b, thereby tending to suppress leakage current and, in some designs, suppress short channel effects (SCEs) that induce such leakage paths 126, thereby tending to improve the performance and / or lifetime of the resulting integrated circuit devices fabricated according to the methods and structures detailed herein. One of ordinary skill in the art guided by the present disclosure can adjust the relationship between the thickness and profile of the epitaxial layer 118 and the dopant species, implantation energy, implantation dose, and implantation tilt angle to achieve a doped halo region 122 that improves the performance of the resulting integrated circuit device while protecting the crystalline integrity of the well region 102 and the mesa region 106 from implantation damage. By confining the halo implant dopant species 120 to the epitaxial layer 118, process engineers gain the beneficial effects of junction offset without causing a level of damage to underlying components that would otherwise unduly impair the performance and / or lifetime of the resulting device.

[0037] Figure 3 is a chart reflecting various combinations of S / D configurations, implant materials, implant energies, implant ranges, implant doses, implant concentrations, and implant tilt angles used in some embodiments of the present disclosure. Figure 3 As reflected in the diagram provided in FIG. , some embodiments (particularly embodiments of columns 1 to 12) include a dielectric layer (see Figure 1E The dielectric layer 127 in the embodiment of the embodiment of the doped halo region 122 and the S / D structure 124 has a dielectric thickness range of about 1 nanometer to 3 nanometers for the embodiments of the columns 1 to 6, and has a thickness range of about 3 nanometers to 5 nanometers for the embodiments of the columns 7 to 12. Figure 3 As reflected, some embodiments, particularly those of columns 13-24, do not include a dielectric layer between the doped halo region 122 and the S / D structure 124, such that the S / D structure is formed directly on the doped halo region.

[0038] like Figure 3 As reflected in FIG. 1 , the implantation energy is adjusted for both the specific dopant used and the dielectric thickness, wherein the embodiments of columns 7 to 12 use higher implantation energies than the embodiments of columns 1 to 12 to achieve a target implantation range of 10 nm to 20 nm and ensure that the doped halo region 122 exhibits a predetermined dopant concentration value and doping profile. Figure 3 As reflected, the implantation dose is selected from a minimum of 5×10 13The maximum value of phosphorus and boron is 40×10 13 The operator applies a specific combination of implant dose and implant energy to obtain a range of 5×10 18 Each cubic centimeter is equal to 1×10 20 Dopant concentration per cubic centimeter.

[0039] like Figure 3 As reflected, some embodiments that do not include a dielectric layer between the doped halo region 122 and the S / D structure 124 include a recessed upper surface on the epitaxial layer 118, with embodiments of columns 13 to 18 having a recess height (RH) of about 1 nanometer, and embodiments of columns 19 to 24 having a recess height of about 3 nanometers. In some embodiments, the recess height is a factor in setting the aspect ratio of the surface structure and affects the tilt angle used for the halo implant to ensure suppression of short channel effects (SCE) associated with shorter channel lengths. In some embodiments, the dielectric layer thickness can be increased to reduce or suppress leakage, but too thick a dielectric layer can cover the bottom sheet and interfere with subsequent processing. Figure 4 is a flow chart of a process 400 for manufacturing an IC device according to some embodiments. In some embodiments, the manufacturing process 400 is used according to Figures 1A to 1F The operations shown in the figure are used to manufacture the IC device, and the following is incorporated into the combination Figures 1A to 1F References to the structures identified above to aid understanding Figure 4 The flowchart is not intended to limit the application of the manufacturing process 400 to only Figures 1A to 1F by way of embodiment.

[0040] according to Figure 4 Embodiments of the present invention include operation 402, during which a substrate (e.g., semiconductor substrate 101) is prepared and certain front-end-of-line (FEOL) operations (which include, for example, deposition of material layers, implantation, annealing, and patterning and etching of the deposited materials) are completed to produce, for example, well regions, isolation structures (not shown), source / drain structures 124, and stacked structures 104. In some embodiments, one or more layers of material applied to the surface of the substrate during formation of the stacked structure 104 are planarized using an etch-back and / or chemical-mechanical planarizing (CMP) process to prepare the surface for subsequent processing. According to some embodiments, the above combined Figures 1A to 1F The discussion of details regarding the execution of the process utilized when performing operation 402.

[0041] In operation 404, the exposed portions of the well region 102 are etched using the stack structure 104 as an etching mask to form self-aligned recessed regions 108 on opposite sides of the stack structure 104, leaving residual portions of the well region 102 to form elevated mesa regions 106 below the stack structure.

[0042] In operation 406, one or more epitaxial materials are deposited on the semiconductor device to at least partially fill the recessed region 108 that was etched in operation 404 into the well region adjacent to the stacked structure 104. In some embodiments, the final thickness of the epitaxial deposition is selected to produce an undoped epitaxial layer having at least a portion of an upper surface that is recessed (characterized by a recess height (RH)) relative to a plane defined by an upper surface of the mesa region 106 below the stacked structure 104. In other embodiments, the final thickness of the epitaxial deposition is selected to produce an undoped epitaxial layer of sufficient thickness such that all or substantially all of a subsequent halo implant dose remains within the undoped epitaxial layer.

[0043] In some embodiments, a dielectric layer 127 is formed over the epitaxial layer 118 prior to the halo implant to provide additional spacing between the mesa regions 106 and the source / drain structures 124 and to provide additional suppression of short channel effects and associated parasitic leakage using optional operation 407. In some embodiments, dielectric regions are used for reduction or suppression, with the best results being seen in such devices that utilize both the halo implant and one or more dielectric layers.

[0044] In operation 408, the previously undoped epitaxial layer is selectively doped using halo implantation. In some embodiments, a combination of dopant species and implantation energy is selected to ensure that all or substantially all of the subsequent implanted dose of dopant species 120 remains within epitaxial layer 118. In embodiments where dielectric layer 127 is formed prior to halo implantation, the implantation energy and / or implantation dose is increased to compensate for the additional material that the implanted dopant must pass through to reach the epitaxial layer and to ensure that the final dopant concentration and distribution within the doped halo region is within predetermined limits. By limiting the projection range of the halo implant to slightly less than the thickness (T ) of epitaxial layer 118, the dopant species 120 is selectively doped with the dopant species 120. NSE ), process 400 ensures that the well region 102 doping and the concentration of any dopant introduced into the well region prior to the counter-doping implant dopant 110 are not affected by the halo implant dopant species 120. In some embodiments, the combination of dopant species and implant energy is selected to ensure that the transistor junction region is shifted from an initial junction location 128a toward a second junction location 128b that is closer to the doped halo region 122, and therefore further away from the portion of the mesa region 106 that underlies the first nanosheet silicon layer 112 in the stacked structure 104, which portion forms a portion of the parasitic current leakage path 126.

[0045] In some embodiments where optional operation 407 is not performed, a dielectric layer 127 is formed over the doped halo region 122 using optional operation 409 to provide additional spacing between the mesa region 106 and the source / drain structure 124 and to provide additional suppression of short channel effects and associated parasitic leakage. In embodiments where the dielectric layer 127 is formed after the halo implant, there is no need to adjust the implant energy and / or implant dose to compensate for the additional material, and implant calculations can be made considering only the thickness of the epitaxial layer to ensure that the final dopant concentration and distribution within the doped halo region is within predetermined limits. In some embodiments, the implant energy of the halo implant is increased to enable the dopant to penetrate the pre-existing dielectric layer. In these embodiments, the dielectric layer provides some additional protection for the underlying semiconductor material. Alternatively, in some embodiments, the halo implant is performed before the dielectric layer is formed. In these embodiments, the halo implant can be performed at a lower implant energy, which will tend to generate less implant damage and associated defects. In some embodiments, the dielectric layer is a multilayer structure including a diffusion barrier layer to isolate the S / D doping from the halo doping. In other embodiments, the dielectric layer is a single material layer that is also used to isolate the S / D epitaxy.

[0046] In operation 410 , in some embodiments, source / drain regions 124 are formed using ALD or other suitable techniques to form source / drain structures on doped halo regions between adjacent stacked structures 104 and / or isolation structures (not shown) disposed between active regions of the semiconductor substrate 101 .

[0047] Figure 5 is a block diagram of an electronic process control (EPC) system 500 according to some embodiments. According to some embodiments of the EPC system 500, the EPC system 500 can be used, for example, to implement methods for generating cell layouts corresponding to some embodiments of the FET device structures detailed above (particularly with respect to adding and placing electrical contacts, thermal contacts, active metal patterns, dummy metal patterns, and other heat dissipation structures).

[0048] In some embodiments, the EPC system 500 is a general purpose computing device including a hardware processor 502 and a non-transitory computer readable storage medium 504. The computer readable storage medium 504 and other devices are encoded with (i.e., store) computer program code (or instructions) 506, i.e., a set of executable instructions. The execution of the computer program code 506 by the hardware processor 502 represents (at least in part) an EPC tool that implements, for example, part or all of the methods described herein according to one or more of the processes and / or methods mentioned below.

[0049] The hardware processor 502 is electrically coupled to the computer readable storage medium 504 via a bus 518. The hardware processor 502 is also electrically coupled to an input / output (I / O) interface 512 via the bus 518. A network interface 514 is also electrically connected to the hardware processor 502 via the bus 518. The network interface 514 is connected to a network 516 so that the hardware processor 502 and the computer readable storage medium 504 can be connected to external components via the network 516. The hardware processor 502 is configured to execute computer program code 506 encoded in the computer readable storage medium 504 so that the EPC system 500 can be used to implement part or all of the processes and / or methods mentioned. In one or more embodiments, the hardware processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0050] In one or more embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or equipment or device). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 504 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disk (DVD).

[0051] In one or more embodiments, the computer readable storage medium 504 stores computer program code 506 configured to enable the EPC system 500 (where such execution represents (at least in part) an EPC tool) to be used to implement a portion or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 504 also stores information that facilitates the implementation of a portion or all of the processes and / or methods mentioned. In one or more embodiments, the computer readable storage medium 504 stores process control data 508, which in some embodiments includes control algorithms, process variables and constants, target ranges, set points, programmed control data, and code for achieving statistical process control (SPC) and / or model predictive control (MPC) type control of various processes.

[0052] The EPC system 500 includes an I / O interface 512. The I / O interface 512 is coupled to external circuitry. In one or more embodiments, the I / O interface 512 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys that communicate information and commands to the hardware processor 502.

[0053] The EPC system 500 also includes a network interface 514 coupled to the hardware processor 502. The network interface 514 enables the EPC system 500 to communicate with a network 516 to which one or more other computer systems are connected. The network interface 514 includes a wireless network interface such as Bluetooth, Wi-Fi, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, a portion or all of the processes and / or methods described are implemented in two or more EPC systems 500.

[0054] The EPC system 500 is configured to send information to and receive information from a fabrication tool 520, which includes one or more of an ion implantation tool, an etching tool, a deposition tool, a coating tool, a rinse tool, a cleaning tool, a chemical mechanical planarization (CMP) tool, a test tool, an inspection tool, a conveyor system tool, and a thermal processing tool that will perform a predetermined series of fabrication operations to produce a desired integrated circuit device. The information includes one or more of operational data, parameter data, test data, and functional data used to control, monitor, and / or evaluate the execution, progress, and / or completion of a particular fabrication process. The process tool information is stored in and / or retrieved from a computer-readable storage medium 504.

[0055] The EPC system 500 is configured to receive information via the I / O interface 512. The information received via the I / O interface 512 includes one or more of instructions, data, programmed data, design rules that specify, for example, layer thicknesses, spacing distances, structure and layer resistivities and feature sizes, process execution history, target ranges, set points, and / or other parameters processed by the hardware processor 502. The information is communicated to the hardware processor 502 via the bus 518. The EPC system 500 is configured to receive information related to a user interface (UI) via the I / O interface 512. The information is stored in the computer readable medium 504 in the form of a user interface (UI) 510.

[0056] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EPC tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EPC system 500.

[0057] In some embodiments, the process is implemented according to a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of an optical disk (e.g., DVD), a magnetic disk (e.g., a hard disk), a semiconductor memory (e.g., ROM, RAM, a memory card), etc.

[0058] Figure 6The present invention is a block diagram of an integrated circuit (IC) manufacturing system 600 for manufacturing IC devices and an IC manufacturing process associated with the IC manufacturing system 600, the IC manufacturing system 600 and the IC manufacturing process incorporating improved control over solid state disk (SSD) and epitaxial (EPI) configuration files according to some embodiments. In some embodiments, the manufacturing system 600 is used to fabricate at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer based on a layout diagram.

[0059] exist Figure 6 , IC manufacturing system 600 includes entities that interact with each other in the design, development and manufacturing cycles and / or services associated with manufacturing IC devices 660, such as design room 620, mask room 630 and IC manufacturer / fabricator ("fab") 650. Once the manufacturing process has been completed to form multiple IC devices on a wafer, the wafer is sent to the back end or back end of line (BEOL) 680 as needed to be programmed, electrically tested and packaged according to the devices to obtain the final IC device product. The entities in manufacturing system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet.

[0060] The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design studio 620, the mask room 630, and the IC fabrication plant 650 are owned by a single larger company. In some embodiments, two or more of the design studio 620, the mask room 630, and the IC fabrication plant 650 coexist in a shared facility and use shared resources.

[0061] The design office (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 660. The geometric patterns correspond to metal layer patterns, oxide layer patterns, or semiconductor layer patterns that constitute various components of the IC device 660 to be manufactured. Various layers are combined to form various IC features.

[0062] For example, a portion of the IC design layout 622 includes various IC features (e.g., active regions, gate electrodes, source and drain, metal lines or vias for metal-to-metal interconnects, and openings for bonding pads) to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design studio 620 implements an appropriate design program to form the IC design layout 622. The design program includes one or more of a logic design, a physical design, or a place and route. The IC design layout 622 exists in one or more data files having information of a geometric pattern. For example, in some operations, the IC design layout 622 will be represented in a GDSII file format or a DFII file format.

[0063] Given that the pattern of the modified IC design layout drawing is adjusted by appropriate methods to, for example, reduce the parasitic capacitance of the integrated circuit compared to the unmodified IC design layout drawing, the modified IC design layout drawing reflects the following results: the positions of the conductive lines in the layout drawing are changed and in some embodiments, features associated with the capacitive isolation structure are inserted into the IC design layout drawing to further reduce the parasitic capacitance compared to the IC structure having the modified IC design layout drawing but without features for forming the capacitive isolation structure located in the IC structure.

[0064] The mask room 630 includes mask data preparation 632 and mask fabrication 644. The mask room 630 uses the IC design layout drawing 622 to manufacture one or more masks 645 for fabricating various layers of the IC device 660 according to the IC design layout drawing 622. The mask room 630 implements the mask data preparation 632, wherein the IC design layout drawing 622 is converted into a representative data file ("representative data file, RDF"). The mask data preparation 632 provides the RDF to the mask fabrication 644. The mask fabrication 644 includes a mask writer. The mask writer converts the RDF into an image on a substrate (e.g., a mask (shield) 645 or a semiconductor wafer 653). The mask data preparation 632 manipulates the IC design layout drawing 622 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 650. In Figure 6 In FIG. 6 , mask data preparation 632 and mask production 644 are illustrated as separate elements. In some embodiments, mask data preparation 632 and mask production 644 are collectively referred to as mask data preparation.

[0065] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which utilizes lithography enhancement techniques to compensate for image errors, such as those known to be caused by diffraction, crosstalk, other process effects, etc. OPC adjusts IC design layout 622. In some embodiments, mask data preparation 632 further includes resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT), which treats OPC as an inverse imaging problem, is also utilized.

[0066] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that checks the IC design layout 622 that has undergone the OPC process using a set of mask creation rules containing certain geometric and / or connectivity constraints to ensure sufficient margin to account for semiconductor manufacturing process variability, etc. In some embodiments, the MRC modifies the IC design layout 622 to compensate for the limitations during mask fabrication 644, which may cancel a portion of the modifications implemented by OPC to satisfy the mask creation rules.

[0067] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), which simulates the process to be performed by IC fabrication facility 650 to fabricate IC device 660. LPC simulates this process based on IC design layout 622 to create a simulated finished device, such as IC device 660. In some embodiments, the process parameters in the LPC simulation will include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or combinations thereof. In some embodiments, after LPC has created a simulated finished device, if the shape of the simulated device does not meet the design rules closely enough, OPC and / or MRC are repeated to further improve IC design layout 622.

[0068] It should be understood that the above description of mask data preparation 632 has been simplified for the purpose of clarity. In some embodiments, mask data preparation 632 includes additional features, such as modifying the logic operation (LOP) of IC design layout 622 according to manufacturing rules. In addition, the processes applied to IC design layout 622 during mask data preparation 632 can be performed in a variety of different orders.

[0069] After the mask data preparation 632 and during the mask fabrication 644, a mask 645 or a batch of masks 645 are fabricated based on the modified IC design layout 622. In some embodiments, the mask fabrication 644 includes performing one or more photolithography exposures based on the IC design layout 622. In some embodiments, an electron-beam (e-beam) or multiple electron-beam mechanisms are used to form a pattern on the mask (photomask or shield) 645 based on the modified IC design layout 622. The mask 645 is formed using a process selected from a variety of available technologies. In some embodiments, the mask 645 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 645 includes a transparent substrate (eg, fused quartz) and an opaque material (eg, chrome) coated in the opaque regions of the binary mask.

[0070] In another example, the mask 645 is formed using a phase shifting technique. In a phase shift mask (PSM) version of the mask 645, various pattern features formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask will be an attenuated PSM or an alternating PSM. The mask produced by the mask making 644 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 653, in an etching process to form various etched regions in the semiconductor wafer 653, and / or in other suitable processes.

[0071] IC fabrication plant 650 includes wafer fabrication 652. IC fabrication plant 650 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating various IC products. In some embodiments, IC fabrication plant 650 is a semiconductor foundry. For example, there may be a fabrication facility for front-end fabrication (front-end of line (FEOL) fabrication) of multiple IC products, while a second fabrication facility may provide back-end fabrication (back-end of line (BEOL) fabrication) for interconnection and packaging of IC products, and a third fabrication facility may provide other services for the foundry enterprise.

[0072] Wafer fabrication 652 includes forming a patterned layer of mask material formed on a semiconductor substrate, wherein the semiconductor substrate is composed of a photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si 3 N 4 , SiON, SiC, SiOC) or a combination thereof. In some embodiments, the mask 645 includes a single mask material layer. In some embodiments, the mask 645 includes multiple mask material layers.

[0073] In some embodiments, IC fabrication plant 655 includes wafer fabrication 657. IC fabrication plant 655 is an IC fabrication enterprise that includes one or more fabrication facilities for fabricating various IC products. In some embodiments, IC fabrication plant 655 is a fabrication facility that provides back-end fabrication (BEOL fabrication) for interconnection and packaging of IC products to add one or more metallization layers to wafer 659, and a third fabrication facility (not shown) may provide other services such as packaging and labeling for the foundry enterprise.

[0074] In some embodiments, the mask material is patterned by exposure to an irradiation source. In some embodiments, the irradiation source is an electron beam source. In some embodiments, the irradiation source is a lamp that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the irradiation source emits a combination of different lights (UV light, visible light, and / or infrared light).

[0075] In some embodiments, the etching process includes exposing the exposed structure in the functional area to an atmosphere containing oxygen to oxidize the outer portion of the exposed structure, followed by a chemical trimming process (e.g., plasma etching or liquid chemical etching) described above to remove the oxidized material and leave the modified structure. In some embodiments, the oxidation is performed after the chemical trimming to provide greater size selectivity for the exposed material and reduce the possibility of accidentally removing material during the manufacturing process. In some embodiments, the exposed structure may include a fin structure of a fin field effect transistor (FinFET), wherein the fin is embedded in a dielectric support medium covering the sides of the fin. In some embodiments, the exposed portion of the fin of the functional area is the top surface and sides of the fin located above the top surface of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level below the top surface of the fin, but still covers the lower portion of the sides of the fin.

[0076] After the mask patterning operation, the areas not covered by the mask are etched to modify the dimensions of one or more structures in the exposed areas. In some embodiments, according to some embodiments, the etching is performed using plasma etching, reactive ion etching (RIE), or a liquid chemical etching solution. The chemistry of the liquid chemical etching solution includes one or more of the following etchants, such as citric acid (C 6 H 8 O 7 ), hydrogen peroxide (H 2 O 2 ), nitric acid (HNO 3 ), sulfuric acid (H 2 SO 4 ), hydrochloric acid (HCl), acetic acid (CH 3 CO 2 H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H 3 PO 4 ), ammonium fluoride (NH 4 F), potassium hydroxide (KOH), ethylenediaminecatechol (EDP), TMAH (tetramethylammonium hydroxide) or a combination thereof.

[0077] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of the substrate material is performed using a halogen-containing reactive gas that is excited by an electromagnetic field to dissociate into ions. The reactive gas or etchant gas includes, for example, CF 4 , SF 6 NF 3 , Cl 2 , CCl 2 F 2 、SiCl 4 , BCl 2or combinations thereof, but other semiconductor material etchant gases are also contemplated to be within the scope of the present disclosure. According to plasma etching methods known in the art, ions are accelerated by varying electromagnetic fields or by fixed bias to bombard exposed materials.

[0078] In some embodiments, molecular-level processing techniques that share the self-limiting surface reaction characteristics utilized in ALD include, for example, Molecular Layer Deposition (MLD) and Self-Assembled Monolayer (SAM). MLD utilizes a continuous precursor-surface reaction in which a precursor is introduced into a reaction zone above the wafer surface. The precursor is adsorbed to the wafer surface where it is confined by physical adsorption. The precursor is then subjected to a rapid chemical adsorption reaction with a number of active surface sites, resulting in self-limited molecular attachment in a specific assembly or regularly repeating structure. These MLD structures will be successfully formed using lower process temperatures than some conventional deposition techniques.

[0079] SAM is a deposition technique involving the spontaneous adhesion of organized organic structures to a wafer surface. Such adhesion involves the adsorption of organic structures from a gas or liquid phase using relatively weak interactions with the wafer surface. Initially, the structures are adsorbed onto the surface by physical adsorption (e.g., by van der Waals forces or polar interactions). The self-assembled monolayer is then confined to the surface by a chemical adsorption process. In some embodiments, the ability of SAM to grow layers as thin as a single molecule through chemical adsorption-driven interactions with the wafer surface is particularly useful for forming thin films including, for example, "near-zero thickness" active layers or barrier layers. SAM is also particularly useful in area-selective deposition (ASD) (or area-specific deposition), which uses molecules that exhibit preferential reactions with specific sections of the underlying wafer surface to promote or hinder subsequent material growth in the target area. In some embodiments, the SAM is used to form a foundation region or a blueprint region for subsequent area-selective ALD (AS-ALD) or area-selective CVD (AS-CVD).

[0080] ALD, MLD and SAM processes represent viable options for fabricating thin layers (in some embodiments, layers made only a few atoms thick) that exhibit sufficient uniformity, conformality and / or purity for intended IC device applications. By individually and sequentially delivering the components of the material system being fabricated to the processing environment, these processes and precise control of the resulting surface chemistry enable excellent control over the processing parameters and the target composition and performance of the resulting film.

[0081] Figure 7 FIG. 7 is a schematic diagram of various processing zones defined within a fabrication plant / front end of line / foundry 700A for manufacturing IC devices according to some embodiments. Processing zones for both front end of line (FEOL) IC device manufacturing and back end of line (BEOL) IC device manufacturing typically include wafer transport operations 702 for moving wafers between the various processing zones. In some embodiments, the wafer transport operations will be associated with the wafer transport operations according to Figure 5 The electronic process control (EPC) system of the wafer transport operation 702 is integrated together and used to provide process control operations to ensure that the wafers being processed are delivered to the appropriate processing area determined by the process flow in a timely and sequential manner. In some embodiments, the EPC system will also provide control and / or quality assurance and parameter data for the proper operation of the defined processing equipment. Wafer transport operations 702 will interconnect various processing areas that provide, for example, photolithography operations 704, etching operations 706, ion implantation operations 708, cleaning / stripping operations 710, chemical mechanical polishing (CMP) operations 712, epitaxial growth operations 714, deposition operations 716, and thermal treatment 718.

[0082] An integrated circuit includes: a substrate, a well, a stacked structure, a doped epitaxial structure, and a source / drain region. The well is formed on a portion of the substrate. The stacked structure is formed on a first portion of the well. The doped epitaxial structure is formed on a second portion of the well adjacent to the stacked structure and below a plane defined by an upper surface of the first portion of the well. The source / drain region is formed on the doped epitaxial structure.

[0083] In some embodiments, the above-mentioned integrated circuit further includes: a dielectric layer located between the doped epitaxial structure and the source / drain regions. In some embodiments, the well has a first dopant concentration; and the doped epitaxial structure has a second dopant concentration, where the first dopant concentration is less than the second dopant concentration. In some embodiments, the well has a first dopant concentration Cd1; the well has a second dopant concentration Cd2 adjacent to the doped epitaxial structure; and the doped epitaxial structure has a third dopant concentration Cd3, where the first dopant concentration, the second dopant concentration, and the third dopant concentration satisfy expressions (I) and (II): Cd1 < Cd2 (I); and Cd2 < Cd3 (II). In some embodiments, the doped epitaxial structure has a dopant concentration profile in which the dopant concentration in the lower region adjacent to the well does not exceed 1E 18 Dopant concentration profile per cubic centimeter. In some embodiments, the doped epitaxial structure has a maximum dopant concentration not greater than 1E 20 Dopant concentration profile per cubic centimeter. In some embodiments, the doped epitaxial structure has a dopant concentration profile in which the lower region adjacent to the well is undoped. In some embodiments, when measured from the plane defined by the upper surface of the mesa structure, the doped epitaxial structure has a concave upper surface with a recess height (RH) between 1 nanometer and 5 nanometers. In some embodiments, the above-mentioned integrated circuit further includes: a plurality of nanosheets in electrical contact with the source / drain regions.

[0084] An integrated circuit includes: a semiconductor substrate, a well region, a stacked structure, a first groove, an epitaxial layer, and a source / drain (S / D) structure. The well region has a first dopant concentration and is located above the semiconductor substrate. The stacked structure is located above a first portion of the well region. The first groove is located in a second portion of the well region. The epitaxial layer is located in the first groove, where the epitaxial layer contains a first implanted dopant. The source / drain (S / D) structure is located above the epitaxial layer.

[0085] In some embodiments, the epitaxial layer contains a first implanted dopant with a first dopant concentration; a second portion of the well region located below the epitaxial layer contains a first implanted dopant with a second dopant concentration; and the first dopant concentration is greater than the second dopant concentration. In some embodiments, the ratio of the first dopant concentration to the second dopant concentration is at least 99:1. In some embodiments, the ratio of the first dopant concentration to the second dopant concentration is at least 85:15. In some embodiments, the first dopant concentration in the epitaxial layer is not greater than 1E 19 Per cubic centimeter. In some embodiments, a first portion of the first implanted dopant extends below the stacked structure. In some embodiments, the above-mentioned integrated circuit further includes: a dielectric layer located above the epitaxial layer; and a source / drain (S / D) structure located above the dielectric layer.

[0086] A method for manufacturing an integrated circuit device includes: forming a well region having a first dopant concentration on a semiconductor substrate; forming a stacked structure on a first region of the well region; etching a first portion of the well region adjacent to the stacked structure to form a first groove and a mesa region; filling the first groove with an undoped epitaxial layer; implanting a first dopant substance of a first dopant dose into the undoped epitaxial layer with an implantation energy to form a first doped epitaxial region; and forming a source / drain (S / D) structure on the first doped epitaxial region, wherein a second dopant concentration in the first doped epitaxial region is sufficient to cause the device junction to deviate from the stacked structure.

[0087] In some embodiments, the method further comprises: configuring the stacked structure into a gate-all-around (GAA) structure; and inserting at least two nanosheets in the stacked structure. In some embodiments, the method further comprises: selecting an implantation energy that causes the second dopant concentration of the first dopant substance to vary by at least 5 times over the thickness of the first doped epitaxial region. In some embodiments, the method further comprises: implanting the first dopant substance at a first dopant dose at an implantation energy sufficient to generate a dopant concentration gradient over the thickness of the first doped epitaxial region, wherein the dopant concentration gradient is 5E. 19 Each cubic centimeter and 1E 20 Varies per cubic centimeter.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. An integrated circuit, characterized in that: Comprising: a substrate; a well formed on a part of the substrate; a stacked structure formed on a first part of the well; a doped epitaxial structure formed on a second part of the well adjacent to the stacked structure and below a plane defined by an upper surface of the first part of the well; and source / drain regions formed on the doped epitaxial structure.

2. The integrated circuit according to claim 1, characterized in that Further comprising: a dielectric layer located between the doped epitaxial structure and the source / drain regions.

3. The integrated circuit according to claim 1, wherein: the well has a first dopant concentration; and the doped epitaxial structure has a second dopant concentration, wherein the first dopant concentration is less than the second dopant concentration.

4. The integrated circuit according to claim 1, wherein: the well has a first dopant concentration Cd1; the well has a second dopant concentration Cd2 adjacent to the doped epitaxial structure; and the doped epitaxial structure has a third dopant concentration Cd3, wherein the first dopant concentration, the second dopant concentration and the third dopant concentration satisfy expressions (I) and (II): Cd1 < Cd2 (I); and Cd2 < Cd3 (II).

5. The integrated circuit according to claim 1, wherein: the doped epitaxial structure has a dopant concentration profile in which a lower region adjacent to the well is undoped.

6. The integrated circuit according to claim 1, wherein: when measured from a plane defined by an upper surface of a mesa structure, the doped epitaxial structure has a concave upper surface with a recess height (RH) between 1 nanometer and 5 nanometers.

7. The integrated circuit according to claim 1, characterized in that Further comprising: a plurality of nanosheets in electrical contact with the source / drain regions.

8. An integrated circuit, characterized in that: Comprising: a semiconductor substrate; a well region having a first dopant concentration, located on the semiconductor substrate; a stacked structure located on a first part of the well region; a first groove located in a second part of the well region; an epitaxial layer located in the first groove, wherein the epitaxial layer contains a first implanted dopant; and a source / drain (S / D) structure located on the epitaxial layer.

9. The integrated circuit according to claim 8, wherein: the epitaxial layer contains the first implanted dopant having a first dopant concentration; a second part of the well region below the epitaxial layer contains the first implanted dopant having a second dopant concentration; and the first dopant concentration is greater than the second dopant concentration.

10. The integrated circuit according to claim 9, wherein: a ratio of the first dopant concentration to the second dopant concentration is at least 85:15.

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