Optical device

Abstract

An optical device and a method of manufacturing the same are disclosed in which a step of bonding the optical device to another device, such as a laser die, is earlier than a step of bonding the optical device and the laser die to another device. The optical device is separated from the laser grain by a distance not greater than about 10 microns.

Description

Technical Field

[0001] The present invention relates to an optical device, and more particularly to a structure for reducing the distance between an optical chip and a laser die. Background Art

[0002] Electrical signal processing is a technology for transmitting and processing signals. In recent years, optical signal processing has been used in more and more applications, especially signal transmission using optical fiber related applications.

[0003] Optical signals and processing are often combined with electrical signals and processing to provide mature applications. For example, optical fibers can be used to transmit, process, and control long-distance signals, while electrical signals can be used to transmit, process, and control short-distance signals. In summary, devices that integrate long-distance optical components and short-distance electrical components can be used to convert between optical signals and electrical signals, as well as process optical signals and electrical signals. Therefore, a package may include an optical (photonic) die containing an optical device, and an electronic die containing an electronic device, and there is a need for improved packaging. Utility Model Content

[0004] In one embodiment, an optical device includes: a first optical chiplet; and a laser die adjacent to the first optical chiplet, wherein a first distance between the laser die and the first optical chiplet is less than about 10 microns.

[0005] In one embodiment, the optical device further includes a first adhesive extending from the first optical chiplet and the laser die.

[0006] In one embodiment, the optical device further includes a second optical chiplet, wherein a second distance between the first optical chiplet and the second optical chiplet is less than about 10 microns.

[0007] In one embodiment, the optical device further includes a second adhesive located between the first optical chip and the second optical chip.

[0008] In one embodiment, the optical device further includes a second laser die, wherein a third distance between the first optical chiplet and the second laser die is less than about 10 microns.

[0009] In one embodiment, the optical device further includes a second adhesive located between the first optical chiplet and the second laser die.

[0010] In one embodiment, the optical device further includes a local silicon interconnect connecting the first optical chiplet to an electronic integrated circuit.

[0011] In one embodiment, the optical device further includes a metallization layer located on the local silicon interconnect, and the metallization layer and the first optical chiplet are located on opposite sides of the local silicon interconnect.

[0012] In one embodiment, the first optical wafer includes an edge coupler aligned to an output end of the laser die.

[0013] In one embodiment, the first optical chiplet and the laser die are bonded to an integrated fan-out substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1 to 2B is a diagram of forming a first optical chip in some embodiments.

[0015] Figure 3 FIG. 1 is a diagram of placing a first optical wafer adjacent to a laser die in some embodiments.

[0016] Figure 4 FIG. 5 is a diagram of bonding a first optical chiplet and a laser die to an interposer substrate in some embodiments.

[0017] Figure 5A and Figure 5B FIG. 1 is a diagram of bonding a first optical wafer to a second optical wafer in some embodiments.

[0018] Fig. 6A and Figure 6B FIG. 1 is a diagram of bonding a first optical chiplet and a second optical chiplet to an integrated fan-out package in some embodiments.

[0019] Figure 7 FIG. 5 is a diagram of bonding a first optical chiplet and a second optical chiplet to an integrated fan-out package with a single-sided metallization layer in some embodiments.

[0020] The reference numerals are described as follows:

[0021] B-B': Section line

[0022] D1: First distance

[0023] 100: The first optical wafer

[0024] 101: First substrate

[0025] 103: First insulation layer

[0026] 105: First active layer

[0027] 107: First optical component

[0028] 109: Semiconductor Materials

[0029] 111: Second insulation layer

[0030] 113: First metallization layer

[0031] 115: Second optical component

[0032] 117: First passivation layer

[0033] 119: Edge Coupler

[0034] 201: Second active layer

[0035] 203: Third optical component

[0036] 205: First through hole

[0037] 207: First external connection

[0038] 209: Combined Active Layer

[0039] 215: First wafer seat

[0040] 300: Laser grains

[0041] 301: First contact

[0042] 303: Second wafer seat

[0043] 305: Second external connection

[0044] 307: First Adhesive

[0045] 401: Interposer substrate

[0046] 403: Semiconductor substrate

[0047] 405, 611: The third metallization layer

[0048] 407: Second through hole

[0049] 409: Second external link

[0050] 500: Second optical wafer

[0051] 503: First semiconductor device

[0052] 505: Second semiconductor device

[0053] 507, 613: Fourth external connection

[0054] 509: Second edge coupler

[0055] 600: Integrated fan-out substrate

[0056] 601: Integrated fan-out through-hole

[0057] 603: Third semiconductor device

[0058] 605: Fourth semiconductor device

[0059] 607: Sealant

[0060] 609: Second metallization layer

[0061] 615: Fifth semiconductor device

[0062] 617: Sixth semiconductor device

[0063] 619: Seventh semiconductor device

[0064] 621: Eighth semiconductor device DETAILED DESCRIPTION

[0065] The following detailed description may be accompanied by drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for clarity of description.

[0066] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. These specific examples are not intended to limit the embodiments of the present invention. For example, if the embodiment of the present invention describes that a first structure is formed on a second structure, it means that the first structure may be in direct contact with the second structure, or an additional structure may be formed between the first structure and the second structure so that the first structure is not in direct contact with the second structure. In addition, multiple examples of the present invention may be repeatedly labeled to simplify the description or make the description clear, which does not mean that structures with the same labels in multiple embodiments and / or settings have the same relative relationship.

[0067] In addition, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or the like are used to describe the relationship of some elements or structures to another element or structure in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientation depicted in the drawings. When the device is rotated in a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted based on the orientation.

[0068] The photonic integrated circuit and the laser die of the following embodiments are connected together before being attached to the substrate. However, the embodiments described here are only for illustration and are not intended to limit the embodiments to the content of the description. On the contrary, the embodiments described can be combined into a variety of implementations, and all of these implementations are fully within the scope of the embodiments of the utility model.

[0069] Figure 1 is the first optical wafer 100 of some embodiments. Figure 1 In the illustrated embodiment, the first optical chiplet 100 is a photonic integrated circuit and at this stage includes a first substrate 101, a first insulating layer 103, and a material layer for a first active layer 105 of a first optical element 107. In one embodiment, the first substrate 101, the first insulating layer 103, and the material layer for a first active layer 105 of a first optical element 107 at the beginning of the manufacturing process of the first optical chiplet 100 can be together as part of a silicon-on-insulator substrate. Consider first the first substrate 101, which can be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material to serve as a structural support for the upper device.

[0070] The first insulating layer 103 may be a dielectric layer that separates the first substrate 101 from the first active layer 105 thereon. In one embodiment, the first insulating layer 103 may be a portion of a cladding material surrounding a first optical component 107 that is subsequently fabricated (as described below). In one embodiment, the first insulating layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination thereof, or the like, and may be formed by implantation (e.g., forming a buried oxide layer) or by deposition methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination thereof, or the like to deposit on the first substrate 101. However, any suitable material and manufacturing method may be used.

[0071] The material used for the first active layer 105 is initially a compliant material layer (before patterning), which can be used to start making the first active layer 105 of the first optical component 107. In one embodiment, the material used for the first active layer 105 can be a semi-transparent material, which can be used as the core material of the desired first optical component 107, such as a semiconductor material such as silicon, germanium, silicon germanium, a combination of the above, or the like. In other embodiments, the material used for the first active layer 105 can be a dielectric material such as silicon nitride or the like. In other embodiments, the material used for the first active layer 105 can be a III-V material, a lithium niobate material, or a polymer. In embodiments where the material of the first active layer 105 is deposited, the deposition method of the material used for the first active layer 105 can be epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the above, or the like. In other embodiments where the method for forming the first insulating layer 103 adopts an implantation method, the material of the first active layer 105 can initially be a portion of the first substrate 101 before the implantation process for forming the first insulating layer 103. However, any suitable material and manufacturing method may be used to form the material of the first active layer 105 .

[0072] Figure 1It is additionally shown that once the materials for the first active layer 105 are prepared, the first optical component 107 for the first active layer 105 can be manufactured using the materials of the first active layer 105. In an embodiment, the first optical component 107 of the first active layer 105 may include components such as optical waveguides (such as ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, or the like), couplers (such as grating couplers, edge couplers such as narrowed waveguides with a width between about 1 nm and about 200 nm, or the like), directional couplers, optical modulators (such as Mach-Zehnder silicon photonic switches, micro-electromechanical switches, micro-ring oscillators, or the like), amplifiers, multiplexers, demultiplexers, photoelectric converters (such as PN junctions), electro-optical converters, lasers, combinations of the above, or the like. However, any suitable first optical component 107 may be used.

[0073] In order to form the first active layer 105 of the first optical element 107 from the initial material, the material used for the first active layer 105 can be patterned into the desired shape of the first active layer 105 of the first optical element 107. In one embodiment, the method of patterning the material used for the first active layer 105 can use one or more photolithography masking and etching processes. However, any suitable method can be used to pattern the material used for the first active layer 105. For some first optical elements 107 such as waveguides or edge couplers, the patterning process can be all or at least the main manufacturing method used to form these first optical elements 107.

[0074] For components using other manufacturing processes, such as Mach-Zehnder silicon photonic switches using resistive heating elements, additional processes may be performed before or after patterning the material of the first active layer 105. For example, an implantation process, additional deposition and patterning processes for different materials (such as resistive heating elements, III-V materials used in converters), a combination of all of these processes, or similar processes may be used to facilitate further manufacturing of a variety of desired first optical components 107. Figure 1 In some of the embodiments shown, a semiconductor material 109 such as germanium (for electrical or optical signal modulation and conversion) may be epitaxially deposited on the patterned portion of the material of the first active layer 105. In these embodiments, the semiconductor material 109 may be epitaxially grown to facilitate the manufacture of photodiodes for photoelectric converters. All of these manufacturing processes, all suitable first optical components 107 that may be manufactured, and all of these combinations are fully within the scope of the embodiments of the present invention.

[0075] Once the independent first optical elements 107 of the first active layer 105 are formed, the second insulating layer 111 may be deposited to cover the first optical elements 107 and provide additional cladding material. In one embodiment, the second insulating layer 111 may be a dielectric layer that can separate the independent elements of the first active layer 105 from each other and from the upper structure, and may additionally serve as another portion of the cladding material to surround the first optical element 107. In one embodiment, the second insulating layer 111 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, a combination of the above, or the like, and may be formed by a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the above, or the like. Once the material of the second insulating layer 111 is deposited, the material may be planarized using a chemical mechanical polishing process to planarize the upper surface of the second insulating layer 111 (in an embodiment where the second insulating layer 111 is intended to completely cover the first optical element 107), or to planarize the second insulating layer 111 to be flush with the upper surface of the first optical element 107. However, any suitable material and manufacturing method may be used.

[0076] Once the first optical element 107 of the first active layer 105 is manufactured and the second insulating layer 111 is formed, the first metallization layer 113 can be formed to electrically connect the first active layer 105 of the first optical element 107 to the control circuit, to electrically connect them to each other, and to electrically connect them to the subsequent bonding device (not shown). Figure 1 , but with Figure 4 In one embodiment, the first metallization layer 113 is formed on the alternating dielectric layer and the conductive material layer, and the formation method thereof can be any suitable process such as deposition, inlay, dual inlay, or the like. In a specific embodiment, multiple metallization layers can be used to interconnect various first optical components 107, but the exact number of first metallization layers 113 depends on the design of the first optical chiplet 100.

[0077] In addition, when manufacturing the first metallization layer 113, one or more second optical components 115 may be formed as part of the first metallization layer 113. In some embodiments, the second optical components 115 of the first metallization layer 113 may include components such as couplers (e.g., edge couplers, grating couplers, or the like) to connect to external signals, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, or the like), optical modulators (e.g., Mach-Zehnder silicon photonic switches, micro-electromechanical switches, micro-ring oscillators, or the like), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optic converters, lasers, combinations thereof, or the like. However, any suitable optical components may be used as the one or more second optical components 115.

[0078] In one embodiment, the method of forming the one or more second optical components 115 may initially deposit the material used for the one or more second optical components 115. In one embodiment, the material used for the one or more second optical components 115 may be a dielectric material such as silicon nitride, silicon oxide, a combination thereof, or the like, or a semiconductor material such as silicon, and the deposition method thereof may be chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination thereof, or the like. However, any suitable material and any suitable deposition method may be used.

[0079] Once the material for the one or more second optical elements 115 is deposited or otherwise formed, the material may be patterned into the desired shape of the one or more second optical elements 115. In one embodiment, the method for patterning the material for the one or more second optical elements 115 may employ one or more photolithography masking and etching processes. However, any suitable method may be employed to pattern the material for the one or more second optical elements 115.

[0080] For some of the one or more second optical components 115, such as waveguides or edge couplers, it may be possible to completely or at least largely utilize a patterning process to form these components. In addition, for components that utilize other manufacturing processes, such as a Mach-Zehnder silicon photonic switch with a resistive heating element, additional processes may be performed before or after patterning the material used for the one or more second optical components 115. For example, an implantation process, additional deposition and patterning processes for different materials, a combination of all of these processes, or the like may be used to facilitate the subsequent placement of a variety of desired one or more second optical components 115. All of these manufacturing processes, all suitable one or more second optical components 115 that can be manufactured, and all of these combinations are within the scope of the embodiments of the present invention.

[0081] In a specific embodiment, the second optical component 115 may specifically include an edge coupler 119 to be adjacent to the edge of the first optical wafer 100. In an embodiment, the edge coupler 119 includes a plurality of waveguides located at different layers of the first metallization layer 113, wherein the plurality of waveguides work together to receive optical signals from the outside of the first optical wafer 100, such as from the subsequently bonded laser die 300 (not shown). Figure 1 , but with Figure 3 However, any suitable combination of optical components may be used.

[0082] Once the one or more second optical elements 115 of the first metallization layer 113 are fabricated, the first passivation layer 117 may be formed on the first metallization layer 113. The first passivation layer 117 may be deposited by any suitable method, such as chemical vapor deposition, high density plasma chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. However, any suitable material and deposition process may be used.

[0083] Figure 2A The steps of removing the first substrate 101 and the first insulating layer 103 as appropriate are shown, thereby exposing the first active layer 105 of the first optical element 107. In one embodiment, the first substrate 101 and the first insulating layer 103 can be removed by a planarization process such as a chemical mechanical polishing process, a grinding process, one or more etching processes, a combination of the above, or the like. However, any suitable method can be used to remove the first substrate 101 and / or the first insulating layer 103.

[0084] Once the first substrate 101 and the first insulating layer 103 are removed, the second active layer 201 of the third optical element 203 (which can form a combined active layer 209 together with the first active layer 105) can be formed on the back side of the first active layer 105. In one embodiment, the materials and processes used to form the second active layer 201 of the third optical element 203 can be the same as the materials and processes used to form the second optical element 115 of the first metallization layer 113 (with the same process). Figure 1 For example, the second active layer 201 of the third optical element 203 may be formed as alternating cladding material layers such as silicon oxide and core material layers such as silicon nitride, which may be formed by a deposition and patterning process to form optical elements such as waveguides and the like.

[0085] Figure 2A The steps of forming the first through-device via 205 and the first external connector 207 are additionally shown. In one embodiment, the first through-device via 205 extends through the second active layer 201 and the first active layer 105 to provide a quick passage for power lines, data lines, and ground lines to pass through the first optical chiplet 100. In one embodiment, the method of forming the first through-device via 205 may initially form a through-device via opening into the first optical chiplet 100. The through-device via opening may be formed by applying and developing a suitable photoresist (not shown), and removing the exposed portions of the second active layer 201 and the first optical chiplet 100.

[0086] Once the through-device via opening is formed in the first optical wafer 100, the through-device via opening can be lined with a liner. The liner can be an oxide or silicon nitride formed from tetraethoxysilane, but any suitable dielectric material can be used instead. The liner can be formed using a plasma-assisted chemical vapor deposition process, but other suitable processes such as physical vapor deposition or thermal processes can also be used instead.

[0087] Once the liner is formed along the sidewalls and bottom of the through-device via opening, a barrier layer (not shown) may be formed and the remainder of the through-device via opening may be filled with a first conductive material. The first conductive material may include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations of the foregoing, or the like may also be used. The first conductive material may be formed by electroplating copper onto a seed layer (not shown) to fill and overfill the through-device via opening. Once the through-device via opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside of the through-device via opening may be removed by a planarization process such as chemical mechanical polishing, although any suitable removal process may be used.

[0088] In some embodiments, once the first through-device via 205 is formed, a second metallization layer (not shown) may be formed as appropriate. Figure 2A ) to be electrically connected to the first through-device via 205. In one embodiment, the second metallization layer may be formed by the method of forming the first metallization layer 113, such as using a damascene process, a dual damascene process, or a similar process to form alternating dielectric material and conductive material layers.

[0089] In other embodiments, the second metallization layer may be formed by an electroplating process to form and shape the conductive material, and then the conductive material is covered with a dielectric material. However, any suitable structure and manufacturing method may be used.

[0090] A first external connector 207 may be formed to provide a conductive area for a connection between the first through-device via 205 or the second metallization layer and other external devices. The first external connector 207 may be a conductive bump (such as a controlled collapse chip connection bump, a ball grid array, a microbump, or the like) or a conductive column, and the materials used may be solder and copper. In one embodiment, the first external connector 207 is a contact bump, and the material included may be tin or other suitable materials such as silver, lead-free tin, or copper. In one embodiment, the first external connector 207 is a tin solder bump, and the method of forming the first external connector 207 may be through common methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like to form a tin layer. Once the tin layer is formed on the structure, reflow may be performed to form the material into the desired bump shape.

[0091] Figure 2BA three-dimensional diagram showing a simplified form of the first optical wafer 100. In this embodiment, the first active layer 105 and the second active layer 201 are shown as a bonded active layer 209, and the first metallization layer 113 above is shown on the bonded active layer 209. In addition, the second optical components 115, each located in the first metallization layer 113, are removed except for the portion used for the edge coupler 119.

[0092] As shown, a first optical chiplet 100 bonded to the laser die 300 may be prepared. Specifically, the first optical chiplet 100 may be separated from any other optical chiplets formed using the first substrate 101. For example, a saw may be used to cut through adjacent optical chiplets to separate the first optical chiplet 100. However, any suitable method such as one or more etching processes may be used.

[0093] Once the first optical chiplet 100 is cut, the first optical chiplet 100 can be bonded to the first wafer bed 215. The first wafer bed 215 is used to control the movement and placement of the first optical chiplet 100. In one embodiment, the first wafer bed 215 can be a vacuum wafer bed, which uses negative pressure to fix and control the first optical chiplet 100. However, any suitable type of wafer bed such as an electrostatic wafer bed can also be used.

[0094] like Figure 3 As shown, the connection of the first optical chiplet 100 to the laser die 300 in the optical integrated circuit to the laser die integration can form an optical chiplet integration. In some embodiments, the laser die 300 can be used to generate light to power other optical components (such as the first optical component 107, the second optical component 115, the third optical component 203, or the like), and can include a structure that generates light such as one or more laser diodes (not shown). In a specific embodiment, the laser diode can be a Fabry-Perot diode, and can be a III-V-based material, a II-VI-based material, or any other suitable material group.

[0095] In a specific embodiment, the laser chip 300 may include a first contact 301, a first buffer layer, a first active diode layer including a plurality of quantum wells, and a second contact ( Figure 3 Only some components are shown for clarity of the drawing) to generate the desired light. In addition, the generated light can be output from the laser die 300 via the first contact 301. However, any suitable structure can be used to form the laser die 300 and generate the desired light.

[0096] In addition, the laser die 300 may also include a second external connector 305. In one embodiment, the second external connector 305 may be similar to the first external connector 207, such as solder balls. However, any suitable material and shape of connector may be used.

[0097] Once the laser die 300 is formed or received, the laser die 300 can be placed adjacent to the first optical wafer 100. In one embodiment, the method of placing the laser die 300 can initially attach the laser die 300 to the second wafer bed 303. In one embodiment, the second wafer bed 303 can be similar to the first wafer bed 215, such as a vacuum wafer bed. However, any suitable type of wafer bed can be used.

[0098] Once the laser die 300 is attached to the second wafer bed 303, the first wafer bed 215 and the second wafer bed 303 may be used to align the first optical chiplet 100 and the laser die 300. In one embodiment, the edge coupler 119 in the first optical chiplet 100 may serve as an alignment mark during the alignment process, which helps the first wafer bed 215 and the second wafer bed 303 ensure that the first optical chiplet 100 and the laser die 300 are located at the desired location and have the desired size. However, any suitable alignment process and / or structure may be used.

[0099] Furthermore, in a specific embodiment, the first contact 301 is used to output the light generated by the laser die 300, and the first wafer bed 215 and the second wafer bed 303 are used to align the output end (such as the first contact 301) of the laser die 300 to the edge coupler 119, so that the edge coupler 119 can receive the light output from the laser die 300. However, any suitable components can be aligned with each other.

[0100] In a specific embodiment, the first wafer bed 215 and the second wafer bed 303 are used to align the first optical chiplet 100 and the laser die 300 so that the first optical chiplet 100 and the laser die 300 are separated by a first distance D1. In some embodiments, the first distance D1 is between about 0.5 microns and about 10 microns. If the first distance D1 is greater than this range, the loss of the generated light when passing through the first distance D1 may be too large. In addition, if the first distance D1 is less than this range, the space between the laser die 300 and the first optical chiplet 100 may not be sufficient to apply subsequent structures such as the first adhesive 307 (if required).

[0101] Once the first wafer bed 215 and the second wafer bed 303 are positioned adjacent to each other, the first adhesive 307 may be applied to adhere the first optical chiplet 100 to the laser die 300 at a first distance D1. In some embodiments, the first adhesive 307 includes a polymer material such as epoxy-acrylate oligomer, whose refractive index may be between about 1 and about 3, and the application method thereof may be an injection method to inject the first adhesive 307 between the laser die 300 and the first optical chiplet 100. However, the first adhesive 307 may be made of any suitable material and any suitable application method.

[0102] Once the first adhesive 307 is applied, the first adhesive 307 may be cured to harden and set the first distance D1. In one embodiment, a thermal curing process may be used to cure the first adhesive, such as heating the first adhesive 307 to cure it. However, any other suitable curing process such as ultraviolet curing may be used.

[0103] By injecting and curing the first adhesive 307 between the first optical chip 100 and the laser die 300, all the areas between the first optical chip 100 and the laser die 300 can be filled with the first adhesive 307. In this way, since the thickness of the first adhesive 307 is equal to the thickness of the area between the first optical chip 100 and the laser die 300, the first width of the first adhesive 307 in this area is equal to the first distance D1.

[0104] In addition, the first adhesive 307 of some embodiments may extend above the upper surface of the first optical chiplet 100 and the laser die 300. In this way, the first adhesive 307 is not limited to the sidewalls of the first optical chiplet 100 and the laser die 300, but may extend horizontally to cover at least a portion of the upper surface of the first optical chiplet 100 and the laser die 300. In this way, at a position above the first optical chiplet 100 and the laser die 300, the second width of the first adhesive 307 is greater than the first width, such as the first distance D1.

[0105] In addition, since the first adhesive 307 is applied to the area between the first optical chip 100 and the laser die 300, the first adhesive 307 can also extend from the bottom side of the first optical chip 100 and the laser die 300. In this way, the first adhesive 307 is not limited to the sidewalls of the first optical chip 100 and the laser die 300, but can be horizontally extended to cover at least a portion of the lower surface of the first optical chip 100 and the laser die 300. In some embodiments, the first adhesive 307 is laterally extended to a sufficient extent to physically contact any one or both of the first external connector 207 and the second external connector 305. However, the first adhesive 307 does not physically contact all of the first external connector 207 and the second external connector 305.

[0106] Although the first adhesive 307 is used in the description of the specific embodiment, the first adhesive 307 is of course only one embodiment, and its description is not intended to limit the scope of the embodiments of the present invention. For example, other embodiments may align and place the first optical chiplet 100 and the laser die 300 to make them physically contact, and perform a welding process such as a laser welding process to connect the first optical chiplet 100 and the laser die 300. However, any suitable method may be used to adhere the first optical chiplet 100 and the laser die 300, and all such methods are fully within the scope of the embodiments of the present invention.

[0107] Figure 4 The step of bonding the first optical chiplet 100 and the laser die 300 to the interposer substrate 401 is shown, which can be used to couple the first optical chiplet 100 and the laser die 300 to other devices to form a chip-on-wafer-on-substrate In one embodiment, the interposer substrate 401 includes a semiconductor substrate 403, a third metallization layer 405, a second through-device via 407, and a second external connection 409. The semiconductor substrate 403 may include a doped or undoped base silicon, or an active layer of a semiconductor-on-insulator substrate. Generally, the semiconductor-on-insulator substrate includes a semiconductor material layer such as silicon, germanium, or silicon germanium, such as silicon-on-insulator, silicon-germanium-on-insulator, or a combination thereof. Other substrates that may be used include multi-layer substrates, composition gradient substrates, or hybrid orientation substrates.

[0108] Active devices (not shown) may be added to the semiconductor substrate 403 as appropriate. Active devices include a wide variety of active devices and passive devices such as capacitors, resistors, inductors, or the like, which can be used to produce the desired structure and function of the design of the semiconductor substrate 403. The active devices may be formed in or on the semiconductor substrate 403 using any suitable method.

[0109] The third metallization layer 405 is formed on the semiconductor substrate 403 and the active device, and is designed to connect various active devices to form functional circuits. In one embodiment, the third metallization layer 405 is formed as alternating dielectric layers (such as low-k dielectric material layers, very low-k dielectric material layers, ultra-low-k dielectric material layers, combinations thereof, or the like) and conductive material layers, and the formation method thereof may be any suitable method such as deposition, damascene, dual damascene, or the like. However, any suitable material and process may be used.

[0110] In addition, at any desired time during the manufacturing process, a second through device via 407 may be formed in the semiconductor substrate 403. If desired, one or more third metallization layers 405 may be formed to provide an electrical connection from the front side of the semiconductor substrate 403 to the back side of the semiconductor substrate 403. In one embodiment, the method of forming the second through device via 407 may initially form a through device via opening into the semiconductor substrate 403 and, if desired, may form any overlying third metallization layer 405 (e.g., after forming the desired third metallization layer, but before forming a subsequent overlying third metallization layer). The through device via opening may be formed by applying and developing a suitable photoresist and removing the portion of the underlying material exposed therefrom to a desired depth. The depth to which the through device via opening extends into the semiconductor substrate 403 may be greater than the final desired height of the semiconductor substrate 403.

[0111] Once the through device via opening is formed in the semiconductor substrate 403 and / or any third metallization layer 405, a liner may be formed to line the through device via opening. The liner may be an oxide or nitride formed from tetraethoxysilane, but any suitable dielectric material may be used. The liner may be formed using a plasma assisted chemical vapor deposition process, but other suitable processes such as physical vapor deposition or thermal processes may also be used.

[0112] Once the liner is formed along the sidewalls and bottom of the through-device via opening, the barrier layer may be formed and the first conductive material may be filled into the remainder of the through-device via opening. The first conductive material may include copper, although other suitable materials such as aluminum alloys, doped polysilicon, combinations of the foregoing, or the like may also be used. The first conductive material may be formed by electroplating copper onto a seed layer to fill and overfill the through-device via opening. Once the through-device via opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside of the through-device via opening may be removed by a planarization process such as chemical mechanical polishing, although any suitable removal process may be used.

[0113] Once the through-device via opening is filled, the semiconductor substrate 403 may be thinned until the second through-device via 407 is exposed. In one embodiment, the method of thinning the semiconductor substrate 403 may be a chemical mechanical polishing process, a grinding process, or the like. Additionally, once the second through-device via 407 is exposed, one or more etching processes such as a wet etching process may be used to recess the semiconductor substrate 403 so that the second through-device via 407 extends out of the semiconductor substrate 403.

[0114] In one embodiment, the second external connector 409 may be placed on the semiconductor substrate 403 to electrically connect to the second through-device via 407 and may be a ball grid array containing a eutectic material such as solder, but any suitable material may be used. An under-bump metallization layer or an additional metallization layer (not shown) may be used as appropriate. Figure 4 ) between the semiconductor substrate 403 and the second external connector 409. In one embodiment, the second external connector 409 is a solder bump, which can be formed by a ball drop method such as a direct ball drop method. In another embodiment, the method of forming the solder bump can initially form a tin layer by any suitable method such as evaporation, electroplating, printing, or solder transfer, and then reflow the material to form the desired bump shape. Once the second external connector 409 is formed, testing can be performed to ensure that the structure is suitable for subsequent processes.

[0115] Once the interposer substrate 401 is formed, the first optical chiplet 100 and the laser die 300 can be bonded to the interposer substrate 401 together. In one embodiment, the method of attaching the first optical chiplet 100 and the laser die 300 to the interposer substrate 401 can be to align the first external connector 207 and the second external connector 305 to the conductive portion of the interposer substrate 401. Once aligned and in physical contact, the first external connector 207 and the second external connector 305 can be heated to exceed the eutectic temperature of the two to reflow, thereby causing the materials of the two to change phase to a liquid phase. Once reflowed, the temperature can be lowered to cause the materials of the first external connector 207 and the second external connector 305 to change phase back to a solid phase, thereby bonding the first optical chiplet 100 and the laser die 300 to the interposer substrate 401.

[0116] By applying the first adhesive 307 between the first optical chiplet 100 and the laser die 300 before bonding the first optical chiplet 100 and the laser die 300 to the interposer substrate 401, the first adhesive 307 may or may not physically contact the interposer substrate 401. For example, the first adhesive 307 of some embodiments may be separated from the interposer substrate 401 by a first gap. In other embodiments, the first adhesive 307 may extend and physically contact the upper surface of the interposer substrate 401.

[0117] Furthermore, by bonding the first optical chiplet 100 and the laser die 300 before bonding either of the first optical chiplet 100 and the laser die 300 to the interposer substrate 401, the distance between the first optical chiplet 100 and the laser die 300 can be reduced to less than about 10 microns (rather than greater than about 30 microns required for first bonding the first optical chiplet 100 and the laser die 300 to the interposer substrate 401). By reducing the distance between the two devices, the coupling loss between the first optical chiplet 100 and the laser die 300 can be reduced when transmitting light between the first optical chiplet 100 and the laser die 300. In this way, direct coupling can be achieved without the need for additional structures.

[0118] The interposer substrate 401 may be viewed as shown (not shown in the figure) Figure 4 ) is additionally bonded to the second substrate via a second external connector 409. In one embodiment, the second substrate may be a packaging substrate, which may be a printed circuit board or the like. The second substrate may include one or more dielectric layers and conductive structures such as conductive lines and through holes. In some embodiments, the second substrate may include through holes, active devices, passive devices, and the like. The second substrate may further include conductive pads formed on the upper surface and the lower surface of the second substrate.

[0119] Figure 5A and Figure 5BA top view and cross-sectional view showing the first optical wafer 100 being adhered to the second optical wafer 500 (in photonic integrated circuit to photonic integrated circuit integration) and a plurality of laser dies 300, and then the units are bonded together to an interposer substrate 401, and Figure 5B show Figure 5A The sectional view of the section line B-B'. Figure 5A and Figure 5B In the embodiment shown, the first optical chiplet 100 is attached to four independent laser dies 300 and receives light generated by the laser dies 300. In a specific embodiment, the first optical chiplet 100 is attached to each laser die 300, such as with Figure 3 For example, the first optical chiplet 100 may be placed before the step of applying the first adhesive 307 before bonding the first optical chiplet 100 to the interposer substrate 401 . However, any suitable connection between the independent laser dies 300 may be used.

[0120] Figure 5A and Figure 5B The step of bonding the second optical chip 500 to the first optical chip 100 is additionally shown. In one embodiment, the manufacturing method and structure of the second optical chip 500 can be matched with Figures 1 to 2A The processes and structures described above are similar and can be designed to work with the first optical wafer 100. For example, a second optical wafer 500 can be fabricated with a second edge coupler 509 formed as part of the second optical member 115 in the first metallization layer 113.

[0121] In one embodiment, the second optical chip 500 may be bonded to the first optical chip 100 before bonding the second optical chip 500 to the interposer substrate 401. In one embodiment, the method and process of bonding the second optical chip 500 to the first optical chip 100 may be combined with Figure 3 The methods and processes described above are similar. For example, the second optical wafer 500 and the first optical wafer 100 are placed adjacent to each other, so that the second edge coupler 509 is aligned with the edge coupler 119 to transmit a signal between the first optical wafer 100 and the second optical wafer 500. In addition, the second optical wafer 500 and the first optical wafer 100 can be placed so that they are separated by a first distance D1 or less, and the first adhesive 307 is applied and cured between the first optical wafer 100 and the second optical wafer 500. However, any suitable method of placing and connecting the first optical wafer 100 and the second optical wafer 500 is fully within the scope of the embodiments of the present invention.

[0122] In addition to bonding the second optical chip 500 to the first optical chip 100, the second optical chip 500 may also be bonded to one or more laser chips 300. In one embodiment, the method of bonding the second optical chip 500 to one or more laser chips 300 may be performed by using a combination of Figure 3 Similar methods and processes as described above. For example, the second optical chiplet 500 and the independent laser die 300 may be placed adjacent to each other within the first distance D1, and the first adhesive 307 may be applied and cured between the laser die 300 and the second optical chiplet 500. However, any suitable method may be used to place and connect the laser die 300, which is entirely within the scope of the embodiments of the present invention.

[0123] Once the second optical chiplet 500 is attached to the first optical chiplet 100 and the laser die 300, the second optical chiplet 500 and other structures can be bonded to the interposer substrate 401 at the same time. Figure 4 However, any suitable bonding process may be used.

[0124] Figure 5A and Figure 5B The method of placing and bonding the first semiconductor device 503 and the second semiconductor device 505 on the interposer substrate 401 is additionally shown. In some embodiments, the first semiconductor device 503 and the second semiconductor device 505 are electronic integrated circuits (e.g., devices without optical devices), and can each have a semiconductor substrate, an active device layer, an upper interconnect structure, and a fourth external connection 507. In one embodiment, the semiconductor substrate can be similar to the first substrate 101 (e.g., a semiconductor material such as silicon or silicon germanium), the active device can be a transistor, a capacitor, a resistor, and the like formed on the semiconductor substrate, the interconnect structure can be similar to the first metallization layer 113 (without optical components), and the fourth external connection 507 can be similar to the first external connection 207. However, any suitable device can be used.

[0125] In one embodiment, the first semiconductor device 503 and the second semiconductor device 505 can be configured to work with the first optical wafer 100, the second optical wafer 500, and each other for a desired function. In some embodiments, the first semiconductor device 503 and the second semiconductor device 505 can be high bandwidth memory modules, processors of any function, logic dies, 3D integrated circuit dies, CPUs, GPUs, system-on-wafer dies, MEMS dies, combinations of the above, or the like. Any suitable device having any suitable function can be used, and all such devices are fully within the scope of the embodiments of the present invention.

[0126] The fourth external interconnect 507 is used to bond the first semiconductor device 503 and the second semiconductor device 505 to the interposer substrate 401. In one embodiment, the first semiconductor device 503 and the second semiconductor device 505 may be placed on the interposer substrate 401, and then a reflow process may be performed to increase the temperature of the fourth external interconnect 507 until the fourth external interconnect 507 is liquefied. Once liquefied, the temperature may be lowered until the fourth external interconnect 507 is solidified, and the first semiconductor device 503 and the second semiconductor device 505 are bonded to the interposer substrate 401.

[0127] By bonding the first optical wafer 100 and the second optical wafer 500 before bonding either of the first optical wafer 100 and the second optical wafer 500 to the interposer substrate 401, the distance between the first optical wafer 100 and the second optical wafer 500 can be reduced to less than about 10 microns. By reducing the distance between the two devices, the coupling loss between the first optical wafer 100 and the second optical wafer 500 can be reduced when light is transmitted between the first optical wafer 100 and the second optical wafer 500. In this way, direct coupling can be achieved without the need for additional structures.

[0128] like Fig. 6A and Figure 6B In another embodiment shown, the first optical chiplet 100 and the second optical chiplet 500 are bonded to an integrated fan-out substrate 600. In this embodiment, an integrated fan-out through-device via 601 is initially formed on a substrate (not shown) to be adjacent to the third semiconductor device 603 and the fourth semiconductor device 605, and the formation method may adopt a photolithography mask and electroplating process. In one embodiment, the third semiconductor device 603 and the fourth semiconductor device 605 may be local silicon interconnects, or may be semiconductor devices similar to the first semiconductor device 503 and / or the second semiconductor device 505.

[0129] Once placed, the integrated fan-out through-device via 601, the third semiconductor device 603, and the fourth semiconductor device 605 can be sealed by a sealant 607, and a second metallization layer 609 can be formed (similar to the first metallization layer 113). The substrate can then be removed, and a third metallization layer 611 can be formed on the opposite side of the integrated fan-out through-device via 601, and a fourth external connector 613 (similar to the first external connector 207) can be placed.

[0130] Once the integrated fan-out substrate 600 is formed, the first optical chiplet 100, the second optical chiplet 500, the laser die 300, the first semiconductor device 503, and the second semiconductor device 505 may be bonded to the integrated fan-out substrate 600. For example, the first optical chiplet 100, the second optical chiplet 500, the laser die 300, the first semiconductor device 503, and the second semiconductor device 505 are placed on the integrated fan-out substrate 600, and the first external connector 207, the second external connector 305, and the fourth external connector 507 are reflowed. However, any suitable process and structure may be used.

[0131] Fig. 6A and Figure 6B The fifth semiconductor device 615, the sixth semiconductor device 617, the seventh semiconductor device 619, and the eighth semiconductor device 621 are additionally shown bonded to the integrated fan-out substrate 600. In one embodiment, the fifth semiconductor device 615, the sixth semiconductor device 617, the seventh semiconductor device 719, and the eighth semiconductor device 621 may be similar to the first semiconductor device 503 and / or the second semiconductor device 505, such as a high bandwidth memory stack or any computing processor (XPU) with external connections such as solder bonding. However, any suitable function and any suitable bonding method may be used.

[0132] Figure 7 In another embodiment shown, an integrated fan-out substrate 600 (eg Figure 7 The simplified form shown in FIG. 1 only includes the third metallization layer 611 (rather than the second metallization layer 609 and the third metallization layer 611) in the chip-on-wafer configuration on the substrate. As a result, since the second metallization layer 609 is not present, the upper device can be directly bonded to the third semiconductor device 603, the fourth semiconductor device 605, and other semiconductor devices such as local silicon interconnects.

[0133] By bonding the optical devices together before bonding any of the optical devices (e.g., the first optical wafer 100, the second optical wafer 500, the laser die 300, and the like) to the interposer substrate 401, the distance between the optical devices can be reduced. By reducing the distance between the individual devices, the coupling loss between adjacent devices can be reduced, and light can be transmitted from one device to an adjacent device. In this way, direct coupling between multiple devices can be achieved without the need for additional structures.

[0134] In one embodiment, a method for manufacturing an optical device includes placing a first optical chiplet; and placing a laser die to form an optical chiplet integration, and the laser die is no more than about 10 microns apart from the first optical chiplet; and placing the optical chip integration to a substrate. In one embodiment, the method further includes applying a first adhesive between the first optical chiplet and the laser die. In one embodiment, the method further includes placing a second optical chiplet, and the second optical chiplet is no more than about 10 microns apart from the first optical chiplet. In one embodiment, the method further includes applying a second adhesive between the second optical chiplet and the first optical chiplet. In one embodiment, the method further includes simultaneously bonding the first optical chiplet, the second optical chiplet, and the laser die to the substrate. In one embodiment, the method further includes simultaneously bonding the first optical chiplet and the laser die to the substrate. In one embodiment, the substrate includes local silicon interconnects.

[0135] In another embodiment, a method for manufacturing an optical device includes: bonding a first optical chiplet to a first wafer bed; bonding a laser die to a second wafer bed; moving at least one of the first wafer bed and the second wafer bed to align an edge coupler of the first optical chiplet with an output end of the laser die; and applying a first adhesive between the first optical chiplet and the laser die, wherein a first thickness of the first adhesive after applying the first adhesive is less than about 10 microns. In one embodiment, the method further includes applying a second adhesive between the first optical chiplet and the second optical chiplet, wherein a second thickness of the second adhesive after applying the second adhesive is less than about 10 microns. In one embodiment, the method further includes applying a second adhesive between the first optical chiplet and the second laser die, wherein a second thickness of the second adhesive after applying the second adhesive is less than about 10 microns. In one embodiment, the method further includes simultaneously bonding the first optical chiplet and the laser die to a substrate. In one embodiment, the substrate is an integrated fan-out substrate. In one embodiment, the integrated fan-out substrate includes local silicon interconnects. In one embodiment, the method further includes using an edge coupler in the first optical wafer as an alignment mark when moving at least one of the first wafer bed and the second wafer bed.

[0136] In yet another embodiment, the optical device comprises: a first optical chiplet; and a laser die adjacent to the first optical chiplet, wherein a first distance between the laser die and the first optical chiplet is less than about 10 microns. In one embodiment, the optical device further comprises a first adhesive extending from the first optical chiplet and the laser die. In one embodiment, the optical device further comprises a second optical chiplet, wherein a second distance between the first optical chiplet and the second optical chiplet is less than about 10 microns. In one embodiment, the optical device further comprises a second adhesive located between the first optical chiplet and the second optical chiplet. In one embodiment, the optical device further comprises a second laser die, wherein a third distance between the first optical chiplet and the second laser die is less than about 10 microns. In one embodiment, the optical device further comprises a second adhesive located between the first optical chiplet and the second laser die. In one embodiment, the optical device further comprises a local silicon interconnect to connect the first optical chiplet to an electronic integrated circuit. In one embodiment, the optical device further comprises a metallization layer located on the local silicon interconnect, and the metallization layer is located on opposite sides of the local silicon interconnect as the first optical chiplet. In one embodiment, the first optical chiplet includes an edge coupler aligned to an output end of the laser die. In one embodiment, the first optical chiplet and the laser die are bonded to an integrated fan-out substrate.

[0137] The features of the above embodiments are helpful for those with ordinary knowledge in the technical field to understand the present invention. Those with ordinary knowledge in the technical field should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those with ordinary knowledge in the technical field should also understand that these equivalent substitutions do not deviate from the spirit and scope of the present invention, and can be changed, replaced, or modified without departing from the spirit and scope of the present invention.

Claims

1. An optical device, characterized in that: include: a first optical wafer; and A laser die is adjacent to the first optical chip, wherein a first distance between the laser die and the first optical chip is less than about 10 microns.

2. The optical device according to claim 1, characterized in that A first adhesive is further included extending from the first optical chiplet and the laser die.

3. The optical device according to claim 1 or 2, characterized in that: A second optical chip is further included, wherein a second distance between the first optical chip and the second optical chip is less than about 10 microns.

4. The optical device according to claim 3, characterized in that A second adhesive is further included between the first optical chip and the second optical chip.

5. The optical device according to claim 3, characterized in that A second laser die is further included, wherein a third distance between the first optical chiplet and the second laser die is less than about 10 microns.

6. The optical device according to claim 5, characterized in that A second adhesive is further included between the first optical chip and the second laser die.

7. The optical device according to claim 1 or 2, characterized in that: A local silicon interconnect is further included to connect the first optical chiplet to an electronic integrated circuit.

8. The optical device according to claim 7, characterized in that It further includes a metallization layer located on the local silicon interconnect, and the metallization layer and the first optical chip are located on opposite sides of the local silicon interconnect.

9. The optical device according to claim 1 or 2, characterized in that: The first optical wafer includes an edge coupler aligned to an output end of the laser die.

10. The optical device according to claim 1 or 2, characterized in that: The first optical chiplet and the laser die are bonded to an integrated fan-out substrate.

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