Fan-out type packaging device

Abstract

The embodiment of the utility model provides a fan-out type packaging device. The fan-out type packaging device comprises a packaging substrate, a chip, an RDL, a UBM layer and an ABF layer, the packaging substrate is provided with a groove, the chip is fixed in the groove, the process face of the chip is back to the bottom of the groove, the RDL is located on the process face of the chip and electrically connected with the chip, the UBM layer is located on the side, away from the chip, of the RDL and electrically makes contact with part of the surface of the RDL, and the ABF layer is electrically connected with the chip. The ABF layer is attached to the side, away from the chip, of the RDL and wraps the side wall of the UBM layer, the ABF layer is provided with a plurality of first through holes to expose the surface of the UBM layer, a thick UBM layer can be arranged, the fan-out type packaging device can bear large stress, and therefore the stability of the fan-out type packaging device can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a fan-out packaging device. Background Art

[0002] In existing fan-out packaging devices, the side walls of the under bump metallization (UBM) layer are exposed to the outside. After the subsequent board is installed, it needs to be filled with bottom filler (Underfile) for protection. Underfile has a certain degree of corrosiveness, or it is easily oxidized by air after being exposed to air for a long time, which further affects the circuit layer inside the chip and causes electrical failure of the chip.

[0003] Usually, the UBM layer is made as thin as possible so that the ball can completely cover the UBM layer after reflow to avoid the problem of chip electrical failure caused by underfile. However, if the UBM layer is thin, the stress it can withstand will be greatly reduced, that is, the stress that the packaged device can withstand is lower, resulting in poor stability of the packaged device. Utility Model Content

[0004] The embodiments of the present disclosure provide a fan-out packaging device that can withstand greater stress, thereby improving the stability of the fan-out packaging device.

[0005] The present disclosure provides a fan-out packaging device, comprising:

[0006] A packaging substrate is provided with a groove;

[0007] A chip is fixed in the groove with the process surface of the chip facing away from the bottom of the groove;

[0008] A redistribution layer, located on a process surface of the chip and electrically connected to the chip;

[0009] An under bump metallization layer is located at a side of the redistribution layer away from the chip and is in electrical contact with a portion of the surface of the redistribution layer;

[0010] The Ajinomoto deposition film layer is attached to the side of the redistribution layer away from the chip and covers the side wall of the under-bump metal layer. The Ajinomoto deposition film layer is provided with a plurality of first through holes to expose the surface of the under-bump metal layer.

[0011] In some embodiments of the present disclosure, the fan-out packaging device further includes: an adhesive layer located between the chip and the bottom of the groove.

[0012] In some embodiments of the present disclosure, the adhesive layer is a crystal bonding film layer.

[0013] In some embodiments of the present disclosure, the fan-out packaging device further includes: a first protection layer located between the chip and the redistribution layer.

[0014] In some embodiments of the present disclosure, the first protective layer is a polyimide layer.

[0015] In some embodiments of the present disclosure, the first protection layer extends into the interior of the groove to fill the area between the sidewall of the chip and the sidewall of the groove.

[0016] In some embodiments of the present disclosure, the fan-out packaging device also includes: a second protective layer, located between the Ajinomoto stacking film layer and the redistribution layer, the second protective layer being provided with a plurality of second through holes to expose a portion of the surface of the redistribution layer away from the chip.

[0017] In some embodiments of the present disclosure, the second protective layer is a polyimide layer.

[0018] In some embodiments of the present disclosure, the chip includes a pad, the first protective layer is provided with a plurality of third through holes to expose a surface of the pad on one side away from the package substrate, and the redistribution layer is in electrical contact with the pad.

[0019] In some embodiments of the present disclosure, the fan-out packaging device further includes: a bump, which is located on a side surface of the under-bump metal layer away from the chip and is in electrical contact with the under-bump metal layer.

[0020] In the technical solution of the embodiment of the present disclosure, the fan-out packaging device includes a packaging substrate, a chip, an RDL, a UBM layer and an ABF layer. The packaging substrate is provided with a groove, the chip is fixed in the groove and the process surface of the chip is facing away from the bottom of the groove, the RDL is located on the process surface of the chip and is electrically connected to the chip, the UBM layer is located on the side of the RDL away from the chip and is electrically contacted with a part of the surface of the RDL, the ABF layer is attached to the side of the RDL away from the chip and covers the side wall of the UBM layer, a plurality of first through holes are provided on the ABF layer to expose the surface of the UBM layer, and a thicker UBM layer can be provided to protect the chip, so that the fan-out packaging device can withstand greater stress, thereby improving the stability of the fan-out packaging device.

[0021] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the cross-sectional structure of a fan-out packaging device provided in an embodiment of the present disclosure.

[0024] FIG. 2A to FIG. 2E A schematic diagram of the packaging process of a fan-out packaging device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "electrically connected" together shall mean that the parts are directly joined together or joined through one or more intermediate components.

[0027] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0028] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0029] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0030] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0031] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0032] The traditional chip packaging method is to cut first and then package and test, and the volume of the original chip increases by at least 20% after packaging. The fan-out packaged device provided by the present disclosure is a device based on the wafer-level chip packaging (Wafer Level Chip Scale Packaging, WLCSP) method. This packaging method first packages and tests on the entire wafer, and then cuts it into individual integrated circuit (IC) particles. Therefore, the volume after packaging is equivalent to the original size of the IC bare crystal. The WLCSP packaging method reduces the size of the memory module, meets the high-density requirements of mobile devices for body space, and also improves data transmission.

[0033] The technical solution of the present disclosure is described in detail below with reference to several specific embodiments.

[0034] Figure 1 A schematic cross-sectional structure diagram of a fan-out packaging device provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the fan-out package device 100 includes: a package substrate 110 , a chip 120 , a redistribution layer (RDL) 130 , a UBM layer 140 and an Ajinomoto Build-up Film (ABF) layer 150 .

[0035] The package substrate 110 is provided with a groove 111, the chip 120 is fixed in the groove 111 and the process surface of the chip 120 faces away from the bottom of the groove 111. The RDL 130 is located on the process surface of the chip 120 and is electrically connected to the chip 120, the UBM layer 140 is located on the side of the RDL 130 away from the chip 120 and is in electrical contact with a part of the surface of the RDL 130, the ABF layer 150 is attached to the side of the RDL 130 away from the chip 120 and covers the sidewall of the UBM layer 140, and a plurality of first through holes 151 are provided on the ABF layer 150 to expose the surface of the UBM layer 140.

[0036] For example, FIG. 2A to FIG. 2E A schematic diagram of a packaging process of a fan-out packaging device provided in an embodiment of the present disclosure. Figure 2A As shown, a packaging substrate 110 is provided, and a groove 111 is arranged on the surface of the packaging substrate 110 .

[0037] The back side of the chip 120 is thinned to a suitable thickness, an adhesive is applied to the back side of the chip 120 and / or the bottom of the groove 111, and the back side of the chip 120 is placed on the bottom of the groove 111 and pressed to form an adhesive layer 160 between the back side of the chip 120 and the bottom of the groove 111. Figure 2B As shown. For example, the adhesive layer 160 may be a die attach film (DAF) layer. Thus, the fan-out package device 100 further includes an adhesive layer 160 located between the back side of the chip 120 and the bottom of the groove 111, which may fix the back side of the chip 120 to the groove 111. At this time, the depth of the groove 111 is approximately equal to the thickness of the chip 120.

[0038] like Figure 2B and Figure 2C As shown, the chip 120 includes a pad 121, and the surface of the pad 121 away from the package substrate 110 is exposed to the air. For example, the pad 121 is an aluminum pad. An RDL 130 is arranged on the surface of the pad 121 exposed to the air, and the RDL 130 is in electrical contact with the pad 121 of the chip 120, so that the RDL 130 is electrically connected to the chip 120. Figure 2C shown.

[0039] like Figure 2D As shown, only a portion of the surface of the side of the RDL 130 away from the chip 120 is exposed to the air, and the surface area of ​​the RDL 130 exposed to the air is subjected to an electroplating process to form a UBM layer 140. In this way, the UBM layer 140 does not exist in the area corresponding to the RDL 130 that is not exposed to the air, that is, the UBM layer 140 includes a plurality of metal layers scattered in a horizontal plane.

[0040] like Figure 2EAs shown, based on the lamination technology, the ABF layer 150 is attached to the side of the RDL 130 away from the chip 120, and the ABF layer 150 covers the area corresponding to the RDL 130 not exposed to the air, the surface of the side of the UBM layer 140 away from the chip 120, and the sidewall of the UBM layer 140. Through the grinding technology, the ABF layer 150 on the surface of the UBM layer 140 is removed to form a plurality of first through holes 151, and the UBM layer 140 is thinned, so as to ensure that the first through holes 151 fully expose the entire surface of the UBM layer 140. Among them, the number of the first through holes 151 and the number of the metal layers scattered on the horizontal plane of the UBM layer 140 are equal.

[0041] In this way, the ABF layer 150 can cover the sidewall of the UBM layer 140 to protect the UBM layer 140. Since there is no need to reduce the thickness of the UBM layer 140, the UBM layer can be subjected to greater stress, so that the fan-out package device 100 can withstand greater stress, thereby improving the stability of the fan-out package device 100.

[0042] like Figure 1 As shown, a bump 170 is formed on the surface of the UBM layer 140, and after reflow, a bump 170 is formed on the surface of the UBM layer 140 away from the chip 120, and the bump 170 is in electrical contact with the UBM layer 140. In this way, the bump 170 is in electrical contact with the pad 121 of the chip 120 through the UBM layer 140 and the RDL 130 in sequence, so that other devices can be electrically connected to the fan-out package device 100 through the bump 170.

[0043] In the disclosed embodiment, a fan-out packaging device includes a packaging substrate, a chip, an RDL, a UBM layer and an ABF layer. The packaging substrate is provided with a groove, the chip is fixed in the groove and the process surface of the chip is facing away from the bottom of the groove, the RDL is located on the process surface of the chip and is electrically connected to the chip, the UBM layer is located on the side of the RDL away from the chip and is electrically contacted with a portion of the surface of the RDL, the ABF layer is attached to the side of the RDL away from the chip and covers the side wall of the UBM layer, a plurality of first through holes are provided on the ABF layer to expose the surface of the UBM layer, and a thicker UBM layer can be provided to protect the chip, so that the fan-out packaging device can withstand greater stress, thereby improving the stability of the fan-out packaging device.

[0044] In some embodiments, see Figure 1 and Figure 2C The fan-out package device 100 further includes a first protection layer 180 , and the first protection layer 180 is located between the chip 120 and the RDL 130 .

[0045] Exemplarily, after the back side of the chip 120 is fixed to the groove 111, polyimide (PI) glue is injected into the process surface of the chip 120 to form a first protective layer 180 covering the entire process surface of the chip 120. At the position corresponding to the first protective layer 180 and the pad 121, a third through hole 181 is formed by coating photoresist, exposing and etching to expose the side surface of the pad 121 away from the package substrate 110, such as Figure 2C shown.

[0046] A layer of RDL 130 is formed on a surface of the first protection layer 180 away from the package substrate 110 by a deposition process, and the RDL 130 is in electrical contact with the pad 121 through the third through hole 181. Figure 2C In other embodiments, a multi-layer RDL 130 is formed on a surface of the first protection layer 180 away from the package substrate 110 by processes such as coating photoresist, exposure, deposition and etching, and a PI layer is disposed between any adjacent RDLs 130 .

[0047] In the embodiment of the present disclosure, when the fan-out packaging device 100 is impacted by external force, the first protective layer 180 formed on the process surface of the chip 120 can buffer the external stress, prevent the chip 120 from being damaged, and improve the stability of the fan-out packaging device 100.

[0048] In some embodiments, see Figure 1 and Figure 2C The first protection layer 180 extends into the groove 111 to fill the area between the sidewall of the chip 120 and the sidewall of the groove 111 .

[0049] For example, when PI glue is applied to the process surface of the chip 120, due to the fluidity of the PI glue, the PI glue flows into the groove 111 along the gap between the sidewall of the chip 120 and the sidewall of the groove 111. When the gap between the sidewall of the chip 120 and the sidewall of the groove 111 is filled with the PI glue, the PI glue will cover the process surface of the chip 120.

[0050] In this way, after the back side of the chip 120 is fixed to the groove 111, as the PI glue is injected, the first protective layer 180 is first formed in the area between the side wall of the chip 120 and the side wall of the groove 111. As the PI glue is continuously injected, the area between the side wall of the chip 120 and the side wall of the groove 111 is completely filled, and the first protective layer 180 is formed on the process surface of the chip 120.

[0051] In some embodiments, see Figure 1 and Figure 2DThe fan-out package device 100 further includes a second protection layer 190 . The second protection layer 190 is located between the ABF layer 150 and the RDL 130 . The second protection layer 190 is provided with a plurality of second through holes 191 to expose a portion of the surface of the RDL 130 away from the chip 120 .

[0052] Exemplarily, after forming the RDL 130, PI glue is injected into the surface of the RDL 130 to form a second protective layer 190 covering the surface of the side of the RDL 130 away from the chip 120. At the position corresponding to the plurality of metal layers scattered on the horizontal plane of the second protective layer 190 and the UBM layer 140, a second through hole 191 is formed by coating photoresist, exposing and etching, etc., to expose a part of the surface of the side of the RDL 130 away from the chip 120, such as Figure 2D shown.

[0053] The exposed area of ​​the surface of the RDL 130 away from the chip 120 is formed into a UBM layer 140 by deposition or other processes. The UBM layer 140 is in electrical contact with the RDL 130 through the second through hole 191. Figure 2D At this time, the surface of the UBM layer 140 away from the chip 120 is higher than the surface of the second protection layer 190 on the chip 120 .

[0054] The ABF layer 150 is attached to the surface of the second protective layer 190 away from the chip 120. The ABF layer 150 covers the surface of the second protective layer 190 away from the chip 120, the surface of the UBM layer 140 away from the chip 120, and the sidewall of the UBM layer 140. The ABF layer 150 on the surface of the UBM layer 140 is removed and the UBM layer 140 is thinned. Figure 2E shown.

[0055] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0056] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0057] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A fan-out packaging device, characterized in that: include: A packaging substrate is provided with a groove; A chip is fixed in the groove with the process surface of the chip facing away from the bottom of the groove; A redistribution layer, located on a process surface of the chip and electrically connected to the chip; An under bump metallization layer is located at a side of the redistribution layer away from the chip and is in electrical contact with a portion of the surface of the redistribution layer; The Ajinomoto deposition film layer is attached to the side of the redistribution layer away from the chip and covers the side wall of the under-bump metal layer. The Ajinomoto deposition film layer is provided with a plurality of first through holes to expose the surface of the under-bump metal layer.

2. The fan-out package device according to claim 1, characterized in that: The fan-out packaging device further comprises: The adhesive layer is located between the chip and the bottom of the groove.

3. The fan-out package device according to claim 2, characterized in that: The adhesive layer is a crystal-bonding film layer.

4. The fan-out package device according to claim 1, characterized in that: The fan-out packaging device further comprises: The first protection layer is located between the chip and the redistribution layer.

5. The fan-out package device according to claim 4, characterized in that: The first protective layer is a polyimide layer.

6. The fan-out package device according to claim 4, characterized in that: The first protection layer extends into the groove to fill the area between the sidewall of the chip and the sidewall of the groove.

7. The fan-out package device according to claim 1, characterized in that: The fan-out packaging device further comprises: The second protective layer is located between the Ajinomoto deposition film layer and the redistribution layer. The second protective layer is provided with a plurality of second through holes to expose a portion of the surface of the redistribution layer away from the chip.

8. The fan-out package device according to claim 7, characterized in that: The second protective layer is a polyimide layer.

9. The fan-out package device according to claim 4, characterized in that: The chip includes a pad; The first protection layer is provided with a plurality of third through holes to expose a surface of the pad on one side away from the package substrate, and the redistribution layer is in electrical contact with the pad.

10. The fan-out package device according to claim 1, characterized in that: The fan-out packaging device further comprises: The bump is located on a side surface of the under bump metal layer away from the chip and is in electrical contact with the under bump metal layer.

Images