SRIO transmission circuit based on high-capacity FPGA

Abstract

The utility model discloses an SRIO transmission circuit based on a large-capacity FPGA, which comprises an FPGA chip D51 and a VPX connector XP1, the FPGA chip D51 is electrically connected with the VPX connector XP1, an N45 pin of the FPGA chip D51 is electrically connected with a P1A13 pin of the VPX connector XP1 through a capacitor C965, and an N46 pin of the FPGA chip D51 is electrically connected with a P1B13 pin of the VPX connector XP1 through a capacitor C966. And the N40 pin of the FPGA chip D51 is electrically connected with the P1D13 pin of the VPX connector XP1. According to the SRIO transmission circuit based on the large-capacity FPGA disclosed by the utility model, the PGA chip D51 realizes high transmission rate and capability through an SRIO transmission protocol between the PGA chip D51 and the VPX connector XP1, and the SRIO transmission circuit has the advantages of fast transmission, high practicability, wide application range and the like.

Description

Technical Field

[0001] The utility model belongs to the technical field of FPGA protocol transmission, and in particular relates to a SRIO transmission circuit based on a large-capacity FPGA. Background Art

[0002] Based on the continuous changes in market requirements and design concepts, the capacity requirements for FPGA boards are becoming larger and larger. As a result, the design requirements for various parts of FPGA boards are constantly increasing. Some existing PFGAs use transmission protocols with low transmission rates and poor transmission capabilities, which cannot meet the transmission requirements of high transmission rates and capabilities.

[0003] Therefore, further improvements are made to the above problems. Utility Model Content

[0004] The main purpose of the utility model is to provide a SRIO transmission circuit based on a large-capacity FPGA. The FPGA chip D51 achieves high transmission rate and capacity through the SRIO transmission protocol between the VPX connector XP1. It has the advantages of fast transmission, high practicality and wide range of use.

[0005] To achieve the above purpose, the utility model provides a SRIO transmission circuit based on a large-capacity FPGA, including an FPGA chip D51 and a VPX connector XP1, wherein the FPGA chip D51 and the VPX connector XP1 are electrically connected, wherein:

[0006] The N45 pin of the FPGA chip D51 is electrically connected to the P1_A13 pin of the VPX connector XP1 through the capacitor C965, and the N46 pin of the FPGA chip D51 is electrically connected to the P1_B13 pin of the VPX connector XP1 through the capacitor C966; the N40 pin of the FPGA chip D51 is electrically connected to the P1_D13 pin of the VPX connector XP1, and the N41 pin of the FPGA chip D51 is electrically connected to the P1_E13 pin of the VPX connector XP1 (VPX GTH R8 P and VPX GTHR8 N are used to receive data, and VPX GTH T8 P and VPX GTH T8 N are used to transmit data, the same below);

[0007] The M43 pin of the FPGA chip D51 is electrically connected to the P1_B14 pin of the VPX connector XP1 through a capacitor C967, and the M44 pin of the FPGA chip D51 is electrically connected to the P1_C14 pin of the VPX connector XP1 through a capacitor C968; the M38 pin of the FPGA chip D51 is electrically connected to the P1_E14 pin of the VPX connector XP1, and the M39 pin of the FPGA chip D51 is electrically connected to the P1_F14 pin of the VPX connector XP1;

[0008] The L45 pin of the FPGA chip D51 is electrically connected to the P1_A15 pin of the VPX connector XP1 through a capacitor C969, and the L46 pin of the FPGA chip D51 is electrically connected to the P1_B15 pin of the VPX connector XP1 through a capacitor C970; the L40 pin of the FPGA chip D51 is electrically connected to the P1_D15 pin of the VPX connector XP1, and the L41 pin of the FPGA chip D51 is electrically connected to the P1_E15 pin of the VPX connector XP1;

[0009] The K43 pin of the FPGA chip D51 is electrically connected to the P1_B16 pin of the VPX connector XP1 through the capacitor C971, and the K44 pin of the FPGA chip D51 is electrically connected to the P1_C16 pin of the VPX connector XP1 through the capacitor C972; the J40 pin of the FPGA chip D51 is electrically connected to the P1_E16 pin of the VPX connector XP1, and the J41 pin of the FPGA chip D51 is electrically connected to the P1_F16 pin of the VPX connector XP1;

[0010] The J45 pin of the FPGA chip D51 is electrically connected to the P2_A1 pin of the VPX connector XP1 through a capacitor C973, and the J46 pin of the FPGA chip D51 is electrically connected to the P2_B1 pin of the VPX connector XP1 through a capacitor C974; the G40 pin of the FPGA chip D51 is electrically connected to the P2_D1 pin of the VPX connector XP1, and the G41 pin of the FPGA chip D51 is electrically connected to the P1_E1 pin of the VPX connector XP1

[0011] The H43 pin of the FPGA chip D51 is electrically connected to the P2_B2 pin of the VPX connector XP1 through a capacitor C975, and the H44 pin of the FPGA chip D51 is electrically connected to the P2_C2 pin of the VPX connector XP1 through a capacitor C976; the E42 pin of the FPGA chip D51 is electrically connected to the P2_E2 pin of the VPX connector XP1, and the E43 pin of the FPGA chip D51 is electrically connected to the P2_F2 pin of the VPX connector XP1;

[0012] The F45 pin of the FPGA chip D51 is electrically connected to the P2_A3 pin of the VPX connector XP1 through a capacitor C977, and the F46 pin of the FPGA chip D51 is electrically connected to the P2_B3 pin of the VPX connector XP1 through a capacitor C978; the C42 pin of the FPGA chip D51 is electrically connected to the P2_D3 pin of the VPX connector XP1, and the C43 pin of the FPGA chip D51 is electrically connected to the P2_E3 pin of the VPX connector XP1;

[0013] The D45 pin of the FPGA chip D51 is electrically connected to the P2_B4 pin of the VPX connector XP1 through capacitor C979, and the D46 pin of the FPGA chip D51 is electrically connected to the P2_C4 pin of the VPX connector XP1 through capacitor C980; the A42 pin of the FPGA chip D51 is electrically connected to the P2_E4 pin of the VPX connector XP1, and the A43 pin of the FPGA chip D51 is electrically connected to the P2_F4 pin of the VPX connector XP1.

[0014] As a further preferred technical solution of the above technical solution, the AG36 pin and the AG37 pin of the FPGA chip D51 are used to provide a clock for the VPX connector XP1, and the clock is 125 MHz.

[0015] As a further preferred technical solution of the above technical solution, the B42 pin of the FPGA chip D51 is connected to the first power supply terminal (VCC1.2) and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal through a resistor R585 (used for voltage correction of the GTH transceiver of the FPGA chip (connected to the VPX connector XP1)).

[0016] As a further preferred technical solution of the above technical solution, the power supply end of the VPX connector XP1 is connected to the second power supply end.

[0017] As a further preferred technical solution of the above technical solution, the VPX connector XP1 is also electrically connected to another FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the first part of a VPX connector XP1 of a SRIO transmission circuit based on a large-capacity FPGA of the utility model.

[0019] Figure 2 It is a schematic diagram of the second part of the VPX connector XP1 of the SRIO transmission circuit based on a large-capacity FPGA of the utility model.

[0020] Figure 3 It is a schematic diagram of the third part of the VPX connector XP1 of the SRIO transmission circuit based on a large-capacity FPGA of the utility model.

[0021] Figure 4 It is a schematic diagram of an FPGA chip D5 of a SRIO transmission circuit based on a large-capacity FPGA of the utility model. DETAILED DESCRIPTION

[0022] The following description is used to disclose the utility model so that those skilled in the art can implement the utility model. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the utility model defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the utility model.

[0023] The utility model discloses a SRIO transmission circuit based on a large-capacity FPGA. The specific embodiments of the utility model are further described below in conjunction with preferred embodiments.

[0024] In the embodiments of the present invention, those skilled in the art will note that the resistors and the like involved in the present invention may be regarded as prior art.

[0025] Preferred embodiments.

[0026] The utility model discloses a SRIO transmission circuit based on a large-capacity FPGA, comprising an FPGA chip D51 and a VPX connector XP1, wherein the FPGA chip D51 and the VPX connector XP1 are electrically connected, wherein:

[0027] The N45 pin of the FPGA chip D51 is electrically connected to the P1_A13 pin of the VPX connector XP1 through the capacitor C965, and the N46 pin of the FPGA chip D51 is electrically connected to the P1_B13 pin of the VPX connector XP1 through the capacitor C966; the N40 pin of the FPGA chip D51 is electrically connected to the P1_D13 pin of the VPX connector XP1, and the N41 pin of the FPGA chip D51 is electrically connected to the P1_E13 pin of the VPX connector XP1 (VPX GTH R8 P and VPX GTHR8 N are used to receive data, and VPX GTH T8 P and VPX GTH T8 N are used to transmit data, the same below);

[0028] The M43 pin of the FPGA chip D51 is electrically connected to the P1_B14 pin of the VPX connector XP1 through a capacitor C967, and the M44 pin of the FPGA chip D51 is electrically connected to the P1_C14 pin of the VPX connector XP1 through a capacitor C968; the M38 pin of the FPGA chip D51 is electrically connected to the P1_E14 pin of the VPX connector XP1, and the M39 pin of the FPGA chip D51 is electrically connected to the P1_F14 pin of the VPX connector XP1;

[0029] The L45 pin of the FPGA chip D51 is electrically connected to the P1_A15 pin of the VPX connector XP1 through a capacitor C969, and the L46 pin of the FPGA chip D51 is electrically connected to the P1_B15 pin of the VPX connector XP1 through a capacitor C970; the L40 pin of the FPGA chip D51 is electrically connected to the P1_D15 pin of the VPX connector XP1, and the L41 pin of the FPGA chip D51 is electrically connected to the P1_E15 pin of the VPX connector XP1;

[0030] The K43 pin of the FPGA chip D51 is electrically connected to the P1_B16 pin of the VPX connector XP1 through the capacitor C971, and the K44 pin of the FPGA chip D51 is electrically connected to the P1_C16 pin of the VPX connector XP1 through the capacitor C972; the J40 pin of the FPGA chip D51 is electrically connected to the P1_E16 pin of the VPX connector XP1, and the J41 pin of the FPGA chip D51 is electrically connected to the P1_F16 pin of the VPX connector XP1;

[0031] The J45 pin of the FPGA chip D51 is electrically connected to the P2_A1 pin of the VPX connector XP1 through a capacitor C973, and the J46 pin of the FPGA chip D51 is electrically connected to the P2_B1 pin of the VPX connector XP1 through a capacitor C974; the G40 pin of the FPGA chip D51 is electrically connected to the P2_D1 pin of the VPX connector XP1, and the G41 pin of the FPGA chip D51 is electrically connected to the P1_E1 pin of the VPX connector XP1

[0032] The H43 pin of the FPGA chip D51 is electrically connected to the P2_B2 pin of the VPX connector XP1 through a capacitor C975, and the H44 pin of the FPGA chip D51 is electrically connected to the P2_C2 pin of the VPX connector XP1 through a capacitor C976; the E42 pin of the FPGA chip D51 is electrically connected to the P2_E2 pin of the VPX connector XP1, and the E43 pin of the FPGA chip D51 is electrically connected to the P2_F2 pin of the VPX connector XP1;

[0033] The F45 pin of the FPGA chip D51 is electrically connected to the P2_A3 pin of the VPX connector XP1 through a capacitor C977, and the F46 pin of the FPGA chip D51 is electrically connected to the P2_B3 pin of the VPX connector XP1 through a capacitor C978; the C42 pin of the FPGA chip D51 is electrically connected to the P2_D3 pin of the VPX connector XP1, and the C43 pin of the FPGA chip D51 is electrically connected to the P2_E3 pin of the VPX connector XP1;

[0034] The D45 pin of the FPGA chip D51 is electrically connected to the P2_B4 pin of the VPX connector XP1 through capacitor C979, and the D46 pin of the FPGA chip D51 is electrically connected to the P2_C4 pin of the VPX connector XP1 through capacitor C980; the A42 pin of the FPGA chip D51 is electrically connected to the P2_E4 pin of the VPX connector XP1, and the A43 pin of the FPGA chip D51 is electrically connected to the P2_F4 pin of the VPX connector XP1.

[0035] Specifically, the AG36 pin and the AG37 pin of the FPGA chip D51 are used to provide a clock of the VPX connector XP1, and the clock is 125 MHz.

[0036] More specifically, the B42 pin of the FPGA chip D51 is connected to the first power supply terminal (VCC1.2) and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal through resistor R585 (for voltage correction of the GTH transceiver of the FPGA chip (connected to VPX connector XP1)).

[0037] Furthermore, the power supply end of the VPX connector XP1 is connected to the second power supply end (VCC12).

[0038] Furthermore, the VPX connector XP1 is also electrically connected to another FPGA chip (the pins of VPX GTH R0-7P and VPXGTH R0-7 N are used to implement SRIO protocol transmission with another FPGA chip).

[0039] The 8XGTH high-speed interface of the AE45 pin to the AC37 pin of the FPGA chip D51 is a high-speed communication between internal FPGA chips, and also performs high-speed transmission through the SRIO protocol.

[0040] It is worth mentioning that the technical features such as resistors involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field and should not be regarded as the invention point of this utility model patent. This utility model patent will not be further elaborated.

[0041] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A SRIO transmission circuit based on a large-capacity FPGA, characterized in that: It includes an FPGA chip D51 and a VPX connector XP1, wherein the FPGA chip D51 and the VPX connector XP1 are electrically connected, wherein: The N45 pin of the FPGA chip D51 is electrically connected to the P1_A13 pin of the VPX connector XP1 through a capacitor C965, and the N46 pin of the FPGA chip D51 is electrically connected to the P1_B13 pin of the VPX connector XP1 through a capacitor C966; the N40 pin of the FPGA chip D51 is electrically connected to the P1_D13 pin of the VPX connector XP1, and the N41 pin of the FPGA chip D51 is electrically connected to the P1_E13 pin of the VPX connector XP1; The M43 pin of the FPGA chip D51 is electrically connected to the P1_B14 pin of the VPX connector XP1 through a capacitor C967, and the M44 pin of the FPGA chip D51 is electrically connected to the P1_C14 pin of the VPX connector XP1 through a capacitor C968; the M38 pin of the FPGA chip D51 is electrically connected to the P1_E14 pin of the VPX connector XP1, and the M39 pin of the FPGA chip D51 is electrically connected to the P1_F14 pin of the VPX connector XP1; The L45 pin of the FPGA chip D51 is electrically connected to the P1_A15 pin of the VPX connector XP1 through a capacitor C969, and the L46 pin of the FPGA chip D51 is electrically connected to the P1_B15 pin of the VPX connector XP1 through a capacitor C970; the L40 pin of the FPGA chip D51 is electrically connected to the P1_D15 pin of the VPX connector XP1, and the L41 pin of the FPGA chip D51 is electrically connected to the P1_E15 pin of the VPX connector XP1; The K43 pin of the FPGA chip D51 is electrically connected to the P1_B16 pin of the VPX connector XP1 through the capacitor C971, and the K44 pin of the FPGA chip D51 is electrically connected to the P1_C16 pin of the VPX connector XP1 through the capacitor C972; the J40 pin of the FPGA chip D51 is electrically connected to the P1_E16 pin of the VPX connector XP1, and the J41 pin of the FPGA chip D51 is electrically connected to the P1_F16 pin of the VPX connector XP1; The J45 pin of the FPGA chip D51 is electrically connected to the P2_A1 pin of the VPX connector XP1 through a capacitor C973, and the J46 pin of the FPGA chip D51 is electrically connected to the P2_B1 pin of the VPX connector XP1 through a capacitor C974; the G40 pin of the FPGA chip D51 is electrically connected to the P2_D1 pin of the VPX connector XP1, and the G41 pin of the FPGA chip D51 is electrically connected to the P1_E1 pin of the VPX connector XP1 The H43 pin of the FPGA chip D51 is electrically connected to the P2_B2 pin of the VPX connector XP1 through a capacitor C975, and the H44 pin of the FPGA chip D51 is electrically connected to the P2_C2 pin of the VPX connector XP1 through a capacitor C976; the E42 pin of the FPGA chip D51 is electrically connected to the P2_E2 pin of the VPX connector XP1, and the E43 pin of the FPGA chip D51 is electrically connected to the P2_F2 pin of the VPX connector XP1; The F45 pin of the FPGA chip D51 is electrically connected to the P2_A3 pin of the VPX connector XP1 through a capacitor C977, and the F46 pin of the FPGA chip D51 is electrically connected to the P2_B3 pin of the VPX connector XP1 through a capacitor C978; the C42 pin of the FPGA chip D51 is electrically connected to the P2_D3 pin of the VPX connector XP1, and the C43 pin of the FPGA chip D51 is electrically connected to the P2_E3 pin of the VPX connector XP1; The D45 pin of the FPGA chip D51 is electrically connected to the P2_B4 pin of the VPX connector XP1 through capacitor C979, and the D46 pin of the FPGA chip D51 is electrically connected to the P2_C4 pin of the VPX connector XP1 through capacitor C980; the A42 pin of the FPGA chip D51 is electrically connected to the P2_E4 pin of the VPX connector XP1, and the A43 pin of the FPGA chip D51 is electrically connected to the P2_F4 pin of the VPX connector XP1.

2. The SRIO transmission circuit based on a large-capacity FPGA according to claim 1, characterized in that: The AG36 pin and the AG37 pin of the FPGA chip D51 are used to provide a clock for the VPX connector XP1, and the clock is 125 MHz.

3. The SRIO transmission circuit based on a large-capacity FPGA according to claim 2, characterized in that: The B42 pin of the FPGA chip D51 is connected to the first power supply terminal and the B43 pin of the FPGA chip D51 is connected to the first power supply terminal through a resistor R585.

4. The SRIO transmission circuit based on a large-capacity FPGA according to claim 3, characterized in that: The power supply end of the VPX connector XP1 is connected to the second power supply end.

5. The SRIO transmission circuit based on a large-capacity FPGA according to claim 4, characterized in that: The VPX connector XP1 is also electrically connected to another FPGA chip.

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