Integrated circuit and radio frequency circuit

Abstract

An integrated circuit includes a first substrate having a first substrate material, and the first substrate includes a first circuit. A second substrate has a second substrate material different from the first substrate material, and the second substrate includes a second circuit. A conductive interconnect electrically connects the first circuit and the second circuit. The utility model also relates to a radio frequency circuit.

Description

Technical Field

[0001] The invention relates to an integrated circuit, and more particularly to a radio frequency (RF) integrated circuit with a variety of substrate configurations. Background Art

[0002] An integrated circuit, such as a radio frequency (RF) integrated circuit, may include, for example, an RF amplifier gain stage, an oscillator including a cross-coupled transistor pair, and a mixer (e.g., a Gilbert mixer implemented by a common source transistor or a cascade structure). Furthermore, the RF integrated circuit may also include input, output, and matching circuits between stages implemented using a plurality of passive inductive and capacitive elements. Typically, the RF integrated circuit is implemented on a single substrate (e.g., a silicon substrate). Utility Model Content

[0003] An integrated circuit has a first substrate, the first substrate includes a first substrate material, and the first substrate includes a first circuit. A second substrate includes a second substrate material different from the first substrate material, and the second substrate includes a second circuit. A conductive interconnection electrically connects the first circuit and the second circuit.

[0004] In some embodiments, the first circuit is a radio frequency (RF) circuit, and the first substrate material is a high impedance substrate.

[0005] In some embodiments, the first circuit includes a plurality of passive components.

[0006] In some embodiments, the first circuit includes a matching circuit.

[0007] In some embodiments, the second circuit includes an amplifier circuit.

[0008] In some embodiments, the first circuit includes a common gate circuit, and wherein the second circuit includes a common source circuit, and wherein the conductive interconnect electrically connects the common gate circuit to the common source circuit.

[0009] In some embodiments, the integrated circuit further includes: a third substrate, the third substrate includes a third substrate material, the third substrate includes a third circuit; and wherein the conductive internal connection electrically connects the third circuit to at least one of the first circuit and / or the second circuit.

[0010] A radio frequency (RF) circuit includes an RF amplifier stage, the RF amplifier stage includes an amplifier circuit formed on a silicon substrate, a first matching circuit formed on a high impedance substrate, and a first conductive inner connection electrically connecting the amplifier circuit and the first matching circuit. An RF oscillator circuit includes an RF oscillator circuit formed on the silicon substrate and a second matching circuit formed on the high impedance substrate. A second conductive inner connection electrically connects the RF oscillator circuit and the second matching circuit.

[0011] In some embodiments, the amplifier circuit includes a common source circuit.

[0012] In some embodiments, the first conductive interconnect and the second conductive interconnect include at least one of a via, a solder bump and / or a bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is fully disclosed in accordance with the following detailed description and in conjunction with the accompanying drawings. It should be noted that, in accordance with common practices in the industry, the drawings are not necessarily drawn to scale. In fact, the size of the components may be arbitrarily enlarged or reduced to provide a clear description. In addition, the accompanying drawings are intended as illustrative examples of embodiments of the present invention and are not intended to limit the embodiments of the present invention.

[0014] Figure 1 is a block diagram illustrating an example of a radio frequency (RF) integrated circuit according to some embodiments.

[0015] Figure 2 is a schematic diagram illustrating an example of a common-gate circuit according to some embodiments.

[0016] Figure 3 is a schematic diagram showing an example of a common source circuit according to some embodiments.

[0017] Figure 4 is a schematic diagram showing an example of a series circuit according to some embodiments.

[0018] Figure 5 is a schematic diagram illustrating an example of a mixer circuit according to some embodiments.

[0019] Figure 6 is a schematic diagram showing an example of a matching circuit according to some embodiments.

[0020] Figure 7 is a diagram showing a method according to some embodiments Figure 1 A block diagram of more aspects of an example of an RF integrated circuit (IC) in FIG.

[0021] Figure 8 is a block diagram illustrating another example of an RFIC according to some embodiments.

[0022] Fig. 9 is a block diagram illustrating an example of an amplifier circuit according to some embodiments.

[0023] Fig.10 is a diagram showing a method according to some embodiments Fig. 9 Schematic diagram of an example amplifier circuit in .

[0024] Fig.11 is a block diagram illustrating another example of an RFIC according to some embodiments.

[0025] Fig.12 is a block diagram illustrating further aspects of an example of an RFIC according to some embodiments.

[0026] Fig.13 is a block diagram illustrating further aspects of another example of an RFIC according to some embodiments.

[0027] Fig.14 is a flow chart illustrating an example of a method of circuit operation according to some embodiments.

[0028] The reference numerals are described as follows:

[0029] 100: RF integrated circuits

[0030] 110: RF input circuit

[0031] 112: Input switch circuit

[0032] 114, 115: Input matching circuit

[0033] 122, 123: Interstage matching circuit

[0034] 124, 125: Output matching circuit

[0035] 120: Amplifier circuit / power amplifier

[0036] 120-1: First stage / first amplifier stage / first power amplifier stage

[0037] 120-n: Nth stage / Nth amplifier stage / final stage

[0038] 130: Common source

[0039] 132: Transistor series circuit

[0040] 140: RF output circuit

[0041] 142: Oscillator Circuit

[0042] 144: LC circuit / output matching circuit

[0043] 146, 220: Mixer circuit

[0044] VDD: voltage terminal

[0045] 210: Common source circuit

[0046] 212: Common-gate circuit

[0047] 214: Series Circuit

[0048] RD, RL: load resistance

[0049] Vout: output node

[0050] M1, M2: CMOS transistors

[0051] Vin: input signal

[0052] VB: Bias signal

[0053] Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8: transistors

[0054] RB1, RB2: resistor

[0055] LS, L1: Inductor

[0056] VLO, VLObar, VRF, VRFbar: Differential input signal

[0057] VIF, VIFbar: differential output signal

[0058] C1, C2: capacitors

[0059] 230: LC matching circuit

[0060] 102: First circuit part

[0061] 104: Second Circuit Part

[0062] 150: First substrate

[0063] 152: Second substrate

[0064] 154: The third substrate

[0065] 121: Low Noise Amplifier

[0066] 121-1: First Low Noise Amplifier (LNA) Stage

[0067] 121-n: Final amplifier stage / final low noise (LNA) amplifier stage

[0068] 156: The fourth substrate

[0069] 158: Fifth substrate

[0070] 160: Conductive internal connection

[0071] 162: Bonding pad

[0072] 164: Substrate through-hole

[0073] 166: Conductive path

[0074] 170: Intermediary layer

[0075] 300: Methods

[0076] 310, 312, 314, 316, 318, 320: Steps DETAILED DESCRIPTION

[0077] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the following disclosure may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0078] In addition, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate description of the relationship between one element or feature and another element or features in the diagram. In addition to the orientation shown in the drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same manner.

[0079] A radio frequency integrated circuit (RFIC) may include, for example, an RF amplifier gain stage, an oscillator, and a mixer. In addition, the RFIC may also include input, output, and matching circuits between stages implemented using multiple passive inductive and capacitive elements. However, one substrate or one type of substrate is not necessarily suitable or the best choice for all RF circuit designs. For example, a lossy substrate may result in intolerable signal loss, thereby limiting the performance of the RF circuit. Although using substrates with more advanced materials can improve performance, this can also result in undesirable increases in device cost.

[0080] Some disclosed embodiments provide substrate configurations for multiple RFICs to optimize RF performance using a substrate suitable for a particular RF circuit while ensuring that substrate costs are kept within a certain range. Substrate configuration (partitioning) is applied to RF circuit design based on system level, sub-block, active / passive components, etc. to enhance the performance of the RF circuit and manage substrate costs. More specifically, the passive components of the matching circuit of the circuit can be configured, for example, on a high impedance substrate to reduce losses, while the core active devices of the above-mentioned RF circuit can be configured on silicon on insulator (SOI) or other advanced-node substrates (substate) to enhance performance. Furthermore, the construction of deep N-well (DNW) devices is often used to avoid substrate effects and improve the reliability of RF circuits. The substrate configuration technology disclosed herein avoids the use of DNW while achieving the above goals. The technical optimization of RFIC is further disclosed herein, wherein the above-mentioned substrate configuration is based on low noise requirements, high voltage circuit requirements, low flicker requirements and similar requirements of other RF circuits, and the above-mentioned RF circuits may be RF low noise amplifiers (LNA), RF power amplifiers (PA) and RF oscillator circuits.

[0081] Therefore, various embodiments of the present disclosure provide various substrate configurations for RFIC, for example, substrate configurations based on system level, sub-blocks, active / passive components, etc. to enhance RF circuit performance, such as improving gain, reducing noise, and increasing reliability while reducing power consumption. By configuring substrates based on device aspects (e.g., functional blocks, circuit types, device operations, etc.), the advantages of different substrate materials can be achieved and optimization of RF system block integration can be allowed.

[0082] For example, some disclosed examples provide an integrated circuit, the integrated circuit comprising a first substrate formed by a first substrate material, the first substrate comprising a first circuit. For example, the first circuit comprises an RF circuit or other high-frequency circuit (e.g., RF LNA). The high-frequency circuit may include a plurality of passive components (e.g., passive components included in a plurality of matching circuits). In some embodiments, for example, the first substrate material comprises a high-impedance substrate, SOI, etc.

[0083] A second substrate is formed by a second substrate material different from the first substrate material. For example, the second substrate material includes silicon. The second substrate also includes a second circuit, for example, an amplifier circuit. A conductive interconnect (e.g., a via, a solder bump, a bonding pad, etc.) electrically connects the first circuit and the second circuit. In some examples, the first circuit includes a common gate circuit, the second circuit includes a common source circuit, and the conductive interconnect electrically connects the common gate circuit to the common source circuit.

[0084] Some specific examples may include an RF circuit, such as an RF LNA having an RF amplifier stage, wherein the RF amplifier stage has an amplifier circuit formed by a silicon substrate and a first matching circuit formed by a high impedance substrate (e.g., an SOI or glass substrate). A first conductive interconnect electrically connects the amplifier circuit and the first matching circuit. The RF circuit further includes an RF oscillator circuit formed on the silicon substrate. The high impedance substrate also forms a second matching circuit. A second conductive interconnect electrically connects the RF oscillator circuit and the second matching circuit. For example, the first and second conductive interconnects include a plurality of vias, a plurality of solder bumps, a plurality of bonding pads, and the like.

[0085] Some embodiments further include a third substrate formed of a third substrate material, the third substrate having a third circuit. The conductive interconnection electrically connects the third circuit to at least one of the first circuit and / or the second circuit.

[0086] Other embodiments are expressed by a method, which includes providing a first substrate formed of a first substrate material (e.g., glass or SOI). Providing a second substrate formed of a second substrate material (e.g., silicon) different from the first substrate material. Receiving an input signal by an input circuit formed on the second substrate. The input signal from the input circuit is further received by a matching circuit formed on the first substrate. An output signal is provided by the matching circuit to an output matching circuit formed on the first substrate. An RF signal is generated by an oscillator circuit formed on the second substrate, and an output of the output matching circuit and an output of the oscillator circuit are received by a mixer circuit formed on the second substrate.

[0087] Providing such a variety of substrate configurations for an RFIC (e.g., substrate configurations based on system level, sub-blocks, active / passive components, etc.) can enhance RF circuit performance. Such enhancements may include increased gain, reduced noise, increased reliability, etc. As described above, substrate configurations are based on functional blocks, circuit types, device operations, etc. to achieve the advantages of using different substrate materials and promote improved RF system block integration.

[0088] Figure 1 An example of an RF integrated circuit 100 configured to provide RF communication or operation is shown. The RF integrated circuit (IC) 100 shown in the figure may include, for example, an RF input circuit 110 and an RF output circuit 140. The RF input circuit 110 includes an amplifier circuit 120 and an input switch circuit 112 for receiving and routing multiple RF input signals. In the example shown, the amplifier circuit 120 is a multi-stage amplifier including a first stage 120-1 to an Nth stage 120-n. An input matching circuit 114 is connected between an output of the input switch circuit 112 and the first stage 120-1 of the amplifier circuit 120.

[0089] A multi-stage inter-stage matching circuit 122 is connected between the multiple stages of the amplifier circuit 120. Figure 1 As shown in the example of FIG. 1 , an inter-stage matching network 122 is connected between multiple stages of the amplifier 120 (eg, Figure 1 An output matching circuit 124 is connected to an output of the final or Nth amplifier stage 120-n.

[0090] The RF output circuit 140 includes an oscillator circuit 142 configured to generate a carrier frequency signal. A mixer circuit 146 (e.g., a Gilbert mixer circuit) combines the output of the RF signal from the output matching circuit 124 with the carrier signal from the oscillator circuit 142. An LC tank / output matching circuit 144 is connected between the oscillator circuit 142 and the mixer circuit 146.

[0091] Some portions of the RF integrated circuit 100, such as the input switch circuit 112, the amplifier circuit 120, the oscillator circuit 142, and the mixer circuit 146, include multiple active devices, such as multiple transistors. In some embodiments, the transistors include complementary metal oxide semiconductor (CMOS) transistors. For example, the first amplifier stage 120-1 to the Nth amplifier stage 120-n, the oscillator circuit 142, and / or the mixer circuit 146 may include coupled transistor pair circuits implemented using a common source 130 and / or a plurality of transistor series arrangement circuits 132.

[0092] Figure 2 An example of a common source circuit 210 is shown, and the common source circuit 210 can be used for the amplifier circuit 120, the oscillator circuit 142 and / or the mixer circuit 146. The common source circuit includes a CMOS transistor M1, which receives an input signal Vin at a gate terminal and uses a drain terminal as an output node Vout. A load resistor RD is connected between the drain terminal of the CMOS transistor M1 and a voltage terminal VDD. The CMOS transistor M1 converts the gate-source voltage change into a small signal drain current, which passes through the load resistor RD and generates an amplified cross-voltage on the load resistor RD.

[0093] Figure 3 An example of a common gate circuit 212 is shown, which can be used in the amplifier circuit 120, the oscillator circuit 142 and / or the mixer circuit 146. The common gate circuit 212 includes a CMOS transistor M2, which receives a bias signal VB at a gate terminal using an input signal Vin detected at a source terminal. The CMOS transistor M2 provides an output node Vout at a drain terminal. A load resistor RD is connected between the drain terminal of the CMOS transistor M2 and a voltage terminal VDD.

[0094] Figure 4An example of a series circuit 214 is shown, which can be used for the amplifier circuit 120, the oscillator circuit 142 and / or the mixer circuit 146. The series circuit 214 is a second-stage amplifier including a common source circuit 210 feeding into a common gate circuit 212. More specifically, the output of the common source circuit 210 is connected to the input of the common gate circuit 212. Therefore, the input signal Vin is first amplified by the common source circuit 210, and the amplified output signal is further amplified by the common gate circuit 212.

[0095] Figure 5 An example of a mixer circuit 146 is shown. Figure 5 The example shown in FIG. 1 is a Gilbert mixer circuit 220, which is used in a series circuit. Figure 4 As shown. The mixer circuit 220 generates a plurality of output signals proportional to the product of the two input signals. The two differential amplifier stages are composed of cross-coupled transistor pairs Q1 / Q2 and Q4 / Q5. One source / drain terminal of these transistors is connected to a load resistor RL and provides differential output signals VIF and VIFbar. The gate terminals of these transistors receive differential input signals VLO and VLObar. The other drain / source terminals of these transistors are connected to a differential transistor pair Q3 / Q6, and the differential transistor pair Q3 / Q6 receives differential input signals VRF and VRFbar using the gate terminals. The source terminals of transistors Q3 / Q6 are further connected to a plurality of inductors LS and a resistor RB1 via a transistor Q7. In the example shown, transistor Q7 is connected to a current mirror configured by transistor Q8 and resistor RB2.

[0096] In some embodiments, the input matching circuit 114 , the inter-stage matching circuit 122 , and the output matching circuits 124 and 144 include a plurality of passive inductive and capacitive elements. Figure 6 An example of an LC matching circuit 230 is shown, which may be used for one or more of the input matching circuit 114, the inter-stage matching circuit 122, and the output matching circuits 124 and 144. The LC matching circuit 230 includes a plurality of passive components, such as an inductor L1 connected between capacitors C1 and C2.

[0097] In some embodiments, the RF integrated circuit 100 is implemented by a single substrate, such as a silicon substrate or a monolithic system on chip (monolithic SoC). However, a single substrate is not necessarily suitable or sufficient for all RF circuits (including Figure 1100). Using a single substrate may result in poor performance and / or increased substrate cost. For example, implementing the entire RFIC 100 on a lossy substrate may result in signal loss and poor performance. On the other hand, implementing the RFIC 100 on a lossless or low-loss substrate (e.g., one utilizing advanced substrate materials) may provide better RF performance, but may also significantly increase cost, especially when the performance of certain components or independent circuits of the RFIC 100 is not affected by the degree of substrate loss.

[0098] According to some embodiments of the present disclosure, a substrate configuration is provided for RFIC 100 to optimize RF performance by utilizing optimized substrate materials (the above-mentioned substrate materials are determined based on a system / circuit / device design perspective), and to manage substrate costs by using low-cost substrate materials for circuits or portions of circuits whose performance is not affected.

[0099] For example, in some examples, multiple passive components (such as multiple passive components in a matching circuit) are configured on a high resistance (high-R) substrate to reduce losses, while active devices used in the core of RF circuits (such as the input switch circuit 112, the first amplifier stage 120-1 to the Nth amplifier stage 120-n, the oscillator circuit 142, the mixer circuit 146, etc.) are configured on advanced node substrate materials (such as silicon on insulator (SOI)) to improve performance.

[0100] Furthermore, for the active portion of the RF integrated circuit 100 (e.g., multiple cascaded amplifier circuits), a deep N-well (DNW) device is often used to avoid substrate effects and improve circuit reliability. However, DNW devices may also increase loss effects, as well as increase the complexity and cost of manufacturing the circuit. In some disclosed examples, a substrate configuration is used to avoid the use of DNWs while also avoiding substrate effects and reliability issues. The substrate configuration disclosed herein may also provide techniques for optimizing RF systems. For example, problems associated with low noise devices, high voltage devices, and low flicker devices in low noise amplifiers (LNA), power amplifiers (PA), and voltage controlled oscillators (VCO) can be solved by the substrate configuration disclosed herein.

[0101] Figure 7 An example of an RFIC 100 configured using a substrate according to an embodiment of the present disclosure is shown. Figure 7The illustrated RFIC 100 includes a first substrate 150 formed from a first substrate material and a second substrate 152 formed from a second substrate material, the first substrate material being different from the second substrate material. Figure 1 In the example shown in FIG. 1 , the RFIC 100 includes an RF input circuit 110 and an RF output circuit 140. The first substrate 150 has a plurality of first circuit portions 102 of the RF input circuit 110 and the RF output circuit 140, and the second substrate 152 has a plurality of second circuit portions 104 of the RF input circuit 110 and the RF output circuit 140. A plurality of conductive interconnects 160 electrically connect the first circuit portions and the second circuit portions.

[0102] exist Figure 7 In the example of FIG. 1 , the first substrate 150 has a first substrate material that forms a high impedance substrate, and the first substrate material has an impedance value, and the impedance value ranges from 750 ohm-cm to 10,000 ohm-cm. The first substrate 150 includes the first circuit portion 102 of the RF input circuit 110 and the RF output circuit 140 (i.e., the input matching circuit 114, the interstage matching circuit 122, and the output matching circuits 124 and 144). The second substrate 152 has a second substrate material (e.g., silicon in the illustrated embodiment), and the second substrate 152 includes the second circuit portion 104 of the RF input circuit 110 and the RF output circuit 140 (i.e., the input switch circuit 112, the amplifier circuit 120, the oscillator circuit 142, and the mixer circuit 146).

[0103] In order to reduce the loss effect caused by a lossy silicon substrate, the first circuit portion 102 (i.e., the input matching circuit 114, the inter-stage matching circuit 122, and the output matching circuits 124 and 144) is implemented on a lossless or low-loss high-impedance substrate, which may include, for example, an SOI or glass substrate. This can improve the performance of the input matching circuit 114, the inter-stage matching circuit 122, and the output matching circuits 124 and 144 at RF frequencies.

[0104] Figure 7 In the example shown, the second substrate 152 is a silicon substrate. The second substrate 152 may be a bulk substrate of single crystal silicon or other semiconductors. In some embodiments, the substrate may alternatively or additionally include one or more semiconductors of other elemental species (e.g., germanium). The substrate may also include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide.

[0105] As described above, in some examples, the first substrate 150 is a SOI substrate. An SOI substrate is a semiconductor wafer technology that can produce higher performance, lower power (dynamic) devices compared to traditional bulk silicon technology. SOI works by adding a thin layer of insulator (e.g., silicon oxide) between a thin layer of silicon and a silicon substrate. Therefore, the SOI substrate is a silicon-insulator-silicon stacked substrate, which can reduce parasitic capacitance within the device and thus improve performance. The difference between SOI-based devices and traditional silicon-based devices is that the silicon interface of SOI-based devices is on an electrical insulator, which is usually silicon dioxide or sapphire (such devices are also called silicon on sapphire (SOS)).

[0106] In other examples, the first substrate 150 is a glass substrate, which includes a glass layer, which can be formed by silicon dioxide (SiO2), lithium peroxide (LiO2), cerium dioxide (CeO2), aluminum oxide (Al2O3), boron trioxide (B2O3) and other similar materials. An oxide layer (such as silicon oxide (SiO)) can be formed on the surface of the glass layer. In some embodiments, a thickness of the glass substrate is less than about 800 μm, or less than about 200 μm in other embodiments.

[0107] As discussed below, the substrate configuration in various embodiments is achieved by different packaging technologies, such as fan out arrangement, interposer, ball grid array, multi-chip package, etc. The interconnection can be bonding, bump, copper via, etc. For example, the conductive interconnect 160 can be implemented by conductive vias, wire bonding pads, conductive bumps, etc.

[0108] Figure 8 Another embodiment is shown, the above embodiment provides a third substrate 154 having a third substrate material. Using an SOI substrate for the entire RF device (such as RFIC 100) can provide better performance than using a silicon substrate. However, using an SOI substrate will result in increased costs. Figure 8The example shown includes a third substrate 154 formed by a third substrate material that is different from the first substrate material and the second substrate material. The third substrate 154 may include an SOI substrate, which is a stacked substrate of silicon-insulator-silicon. The SOI substrate can reduce parasitic capacitance within the device, thereby improving performance. The silicon interface is located on an electrical insulator, usually silicon dioxide or sapphire, and the silicon interface is also called silicon on sapphire (SOS). The second substrate 152 and the third substrate 154 are configured for active circuits between the second circuit portion 104 or the RF input circuit 110 and the RF output circuit 140.

[0109] More specifically, the input switch circuit 112 and the first to Nth amplifier stages 120 - 1 to 120 - n of the amplifier circuit 120 are disposed on a third substrate 154 , which is an advanced node substrate, for example, Figure 8 In order to reduce the loss effect caused by a lossy silicon substrate, the input matching circuit 114, the inter-stage matching circuit 122 and the output matching circuits 124 and 144 are implemented on the first substrate 150, which can be a lossless or low-loss high-impedance substrate. Figure 8 In the example of, the high impedance substrate may have an impedance value, and the impedance value ranges from 750 ohm-cm to 10,000 ohm-cm. A glass substrate may include a glass layer, and the glass layer may be formed by silicon dioxide (SiO2), lithium peroxide (LiO2), cerium dioxide (CeO2), aluminum oxide (Al2O3), boron trioxide (B2O3) and other similar materials. An oxide layer (such as silicon oxide (SiO)) may be formed on the surface of the glass layer, and the oxide layer may have a thickness of less than about 800μm, or less than about 200μm in other embodiments. The above content can provide the above circuit with better performance at RF frequencies. The oscillator circuit 142 and the mixer circuit 146 are implemented on the second substrate 152, and the second substrate 152 is a silicon substrate. The above content improves the RF operation of the RFIC 100 while controlling the cost. Fig. 9 An example of the RF input circuit 110 of the RFIC 100 is shown, wherein the amplifier circuit 120 is configured on two different substrates 150 and 152. As described above, the first amplifier stage 120-1 to the Nth amplifier stage 120-n of the amplifier circuit 120 include a plurality of common gate circuits connected in series, for example, Figure 4Serial circuit 214 is shown. Often, the above-mentioned serial common-gate circuit is implemented by a deep N-well (DNW) device to avoid substrate effect and reliability issues. More specifically, in some embodiments, the common-gate circuit 210 of the serial circuit 214 is implemented by a DNW device to avoid substrate effect and reliability issues. However, the DNW device may cause increased signal loss effects and require more masks in the manufacturing operation.

[0110] Fig. 9 In the illustrated embodiment, the common gate circuit 210 of the series circuit 214 is implemented in or on the first substrate 150, and in some examples, the first substrate 150 can be a high impedance substrate (e.g., a glass substrate). The common source circuit 212 is formed in or on the second substrate 152, for example, the second substrate 152 can be a silicon substrate. Fig.10 It is for a display Figure 4 A schematic diagram of the series circuit 214 is shown, Fig.10 The common source circuit 212 implemented in the second substrate 152 and the common gate circuit 210 implemented in the first substrate 150 are further conceptually illustrated. The conductive interconnect 160 connects the common source circuit 212 to the common gate circuit 210 to form a series circuit 214.

[0111] More specifically, the common source circuit 210 includes a CMOS transistor M1 that receives an input signal Vin at a gate terminal and provides an output signal at a drain terminal. The CMOS transistor M1 converts a gate-source voltage difference into a small signal drain current to output to the common gate circuit 212. The common source circuit 210 is formed in or on the first substrate 150, and for example, the first substrate 150 can be a high impedance substrate. The common gate circuit 212 includes a CMOS transistor M2 that receives a bias signal VB at a gate terminal. The source terminal of the CMOS transistor M2 detects the output signal of the common source circuit 210. The CMOS transistor M2 provides an output node Vout at the drain terminal. The load resistor RD is connected between the drain terminal of the CMOS transistor M2 and the voltage terminal VDD. The common gate circuit 212 is formed in or in the second substrate 152, and in some examples, the second substrate 152 can be a silicon substrate.

[0112] The common source circuit 210 and the common gate circuit 212 together form a series circuit 214 of a second-stage amplifier, wherein the input signal Vin is first amplified by the common source circuit 210 , and the output signal generated by the amplification is further amplified by the common gate circuit 212 .

[0113] use Fig. 9 , Fig.10The substrate configuration shown in FIG. 1 is used to realize that one or more series circuits 214 of the amplifier circuit 120 are not limited by DNW and can also avoid the problem of substrate effect.

[0114] Fig.11 Another example of further configuring the substrate is shown. As mentioned above, a single substrate technology may not be suitable for all parts of the RFIC 100. In the embodiment shown, the input switch circuit 112 is implemented by the first substrate 150, which is a SOI substrate.

[0115] exist Fig.11 In the example shown, the amplifier circuit 120 is an RF power amplifier. The input matching circuit 114 and the first power amplifier stage 120-1 are implemented by a second substrate 152, and the second substrate 152 can be a silicon substrate, for example. The final stage 120-n and the output matching circuit 124 of the power amplifier 120 use a third substrate 154 (e.g., a high voltage (high-V) substrate). The high-voltage substrate can include a ceramic material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (SiN), barium oxide (BeO), and other similar materials.

[0116] Fig.11 The illustrated embodiment further includes a low noise amplifier 121, wherein a first low noise amplifier (LNA) stage 121-1 is implemented by a fourth substrate 156, which may be a low noise SOI substrate. An input matching circuit 115 is also implemented by the fourth substrate 156. Other low noise amplifier stages (e.g., final amplifier stage 121-n) may be formed by a second substrate 152 or other similar substrates. A multi-stage inter-stage matching circuit 123 and an output matching circuit 125 may be implemented by the same substrate as the final low noise amplifier (LNA) stage 121-n.

[0117] In some examples, the oscillator circuit 142 is implemented by a fifth substrate 158 , which may be a low-flicker substrate (eg, a glass substrate). The oscillator output matching circuit 144 and the mixer circuit 146 may also be implemented by the fifth substrate 158 .

[0118] The above substrate configuration can optimize multiple circuit blocks in terms of legacy circuit design, performance, cost / area, etc. to improve system block integration.

[0119] As described above, a variety of packaging technologies may be used for the various substrates and their respective RF circuits. Fig.12An example is shown in which the first substrate 150 and the second substrate 152 are in a stacked configuration to form a 3D IC structure. The conductive interconnect 160 can be in the form of a through substrate conductive via 164 extending from a plurality of bonding pads 162 on the front or back side of the first substrate 150 to a corresponding plurality of bonding pads on the second substrate 152.

[0120] Fig.13 An example is shown in which the first substrate 150 and the second substrate 152 are arranged side by side on an interposer 170. The first substrate 150 and the second substrate 152 can be connected to the interposer by a plurality of micro-bumps. Fig.13 In the embodiment, the conductive interconnect 160 may include a plurality of bonding pads 162 interconnected by a plurality of conductive tracks 166 of the interposer 170 .

[0121] Fig.14 Demonstrates the operation of an RF circuit (such as: Figure 7 An example of a method 300 for manufacturing an RFIC 100 is shown in FIG. 300 includes providing a first substrate and a plurality of second substrates in step 310. Figure 7In the illustrated embodiment, the first substrate 150 includes a first substrate material, and in some examples, the first substrate material can be a high impedance substrate (e.g., glass or SOI). The second substrate 152 includes a second substrate material (e.g., silicon) different from the first substrate material. In step 312, an RF input circuit 110 (e.g., input switch circuit 112 and amplifier circuit 120 formed on the second substrate 152) receives an input signal. The amplifier circuit is an RF LNA, and in some embodiments, the RF LNA includes a common gate circuit and a common source circuit. In step 314, a matching circuit (e.g., input matching circuit 114, interstage matching circuit 122, and output matching circuit 124 formed on the first substrate 150) receives the input signal from the input circuit. In some examples, the matching circuit includes a plurality of passive components. In step 316, the output matching circuit 124 provides an output signal to an output matching circuit 144 formed on the first substrate 150. In step 318, an oscillator circuit 142 formed on the second substrate 152 generates an RF signal, and in step 320, a mixer circuit 146 formed on the second substrate 152 receives an output of the output matching circuit 144 and an output of the oscillator circuit 142. The input matching circuit 114, the inter-stage matching circuit 122, and the output matching circuit 124 can be electrically connected to one or more stages of the amplifier circuit 120 via conductive internal connections (e.g., multiple vias, multiple solder bumps, multiple bonding pads, etc.). In some embodiments, a third substrate formed by a third substrate material is further provided. The third substrate includes a third circuit, for example, the third circuit includes one or more amplifier stages of the RF LNA. The conductive internal connections electrically connect the third circuit to the first circuit and / or the second circuit mentioned above.

[0122] Therefore, the embodiments of the present disclosure provide multiple substrate configurations of RFIC 100 (e.g., based on system level, sub-blocks, active / passive components, etc.) to enhance RF circuit performance, such as gain enhancement, noise reduction, and increased reliability at less power consumption. By configuring the substrate based on device aspects (e.g., functional blocks, circuit types, device operations, etc.), the advantages of different substrate materials can be achieved and the integration of RF system blocks can be improved.

[0123] According to an embodiment of the present disclosure, an integrated circuit has a first substrate, the first substrate includes a first substrate material, and the first substrate includes a first circuit. A second substrate includes a second substrate material different from the first substrate material, and the second substrate includes a second circuit. A conductive interconnection electrically connects the first circuit and the second circuit. The first circuit is a radio frequency (RF) circuit, and the first substrate material is a high impedance substrate. The first substrate material includes glass and silicon on insulator (SOI). The first circuit includes a plurality of passive components and a matching circuit, and the second circuit includes an amplifier circuit, the amplifier circuit includes a common source circuit, and the second substrate material includes silicon. The first circuit includes a common gate circuit, the second circuit includes a common source circuit, and the conductive interconnection electrically connects the common gate circuit to the common source circuit. A third substrate includes a third substrate material, and the third substrate includes a third circuit. The conductive interconnection electrically connects the third circuit to at least one of the first circuit and / or the second circuit, and the conductive interconnection includes at least one of a via, a solder bump, and / or a bonding pad.

[0124] According to other embodiments, an RF circuit includes an RF amplifier stage, the RF amplifier stage includes an amplifier circuit formed by a silicon substrate, a first matching circuit formed by a high impedance substrate, and a first conductive inner connection electrically connecting the amplifier circuit and the matching circuit. An RF oscillator circuit includes an RF oscillator circuit formed by the silicon substrate and a second matching circuit formed by the high impedance substrate. A second conductive inner connection electrically connects the RF oscillator circuit and the second matching circuit. The amplifier circuit includes a common source circuit, the high impedance substrate is a silicon on insulator (SOI) substrate or a glass substrate. The first conductive inner connection and the second conductive inner connection include at least one of a via, a solder bump and / or a bonding pad.

[0125] According to other embodiments of the present disclosure, a circuit operation method includes providing a first substrate, the first substrate including a first substrate material, and the method also includes providing a second substrate, the second substrate including a second substrate material different from the first substrate material. An input signal is received by an input circuit formed on the second substrate. The input signal from the input circuit is received by a matching circuit formed on the first substrate. An output signal is provided by the matching circuit to an output matching circuit formed on the first substrate. An oscillator circuit formed on the second substrate generates an RF signal, and an output of the output matching circuit and an output of the oscillator circuit are received by a mixer circuit formed on the second substrate. The first substrate material includes glass or silicon on an insulating layer, and the second substrate material includes silicon.

[0126] The present disclosure summarizes multiple embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other operations and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit, characterized in that: include: A first substrate, comprising a first substrate material, wherein the first substrate comprises a first circuit; a second substrate, comprising a second substrate material different from the first substrate material, wherein the second substrate comprises a second circuit; and A conductive inner connection electrically connects the first circuit and the second circuit.

2. The integrated circuit according to claim 1, wherein: The first circuit is a radio frequency (RF) circuit, and the first substrate material is a high impedance substrate.

3. The integrated circuit according to claim 2, characterized in that The first circuit includes a plurality of passive components.

4. The integrated circuit according to claim 2, wherein: The first circuit includes a matching circuit.

5. The integrated circuit according to claim 2, wherein: The second circuit includes an amplifier circuit.

6. The integrated circuit according to claim 5, characterized in that The first circuit includes a common gate circuit, and the second circuit includes a common source circuit, and the conductive interconnection electrically connects the common gate circuit to the common source circuit.

7. The integrated circuit according to claim 1, wherein: Also includes: a third substrate, the third substrate comprising a third substrate material, the third substrate comprising a third circuit; and The conductive inner connection line electrically connects the third circuit to the first circuit and / or the second circuit.

8. A radio frequency circuit, characterized in that: include: A radio frequency (RF) amplifier stage, comprising: A silicon substrate having an amplifier circuit formed thereon; A high impedance substrate having a first matching circuit formed thereon; and a first conductive inner connection electrically connecting the amplifier circuit and the first matching circuit; and A radio frequency oscillator circuit comprising: The silicon substrate is formed with a radio frequency oscillator circuit; The high impedance substrate is formed with a second matching circuit; and A second conductive inner connection electrically connects the RF oscillator circuit and the second matching circuit.

9. The radio frequency circuit according to claim 8, characterized in that: The amplifier circuit includes a common source circuit.

10. The radio frequency circuit according to claim 8, characterized in that: The first conductive inner connection and the second conductive inner connection include a via, a solder bump and / or a bonding pad.

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