Display device

Abstract

There is provided a display device including: a first pixel electrode disposed on a substrate in a first emission area; the insulating layer covers the edge of the first pixel electrode; a first light emitting layer disposed on the first pixel electrode and the insulating layer; a first common electrode disposed on the first light emitting layer; a first bank disposed on the insulating layer, the first bank surrounding the first emission region; a second bank disposed on the first bank around the first emission area, the second bank including a tip protruding from a side of the first bank; and an etching control layer disposed on a top surface of the first common electrode, on a side surface of the first bank, and on a bottom surface of a tip of the second bank. The display device has a plurality of uniformly formed light emitting elements, and has improved reliability.

Description

Technical Field

[0001] The disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] With the development of the information society, the demand for display devices for displaying images has diversified. In an embodiment, the display device is being applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart TVs. Here, the display device can be a flat panel display device such as a liquid crystal display ("LCD") device, a field emission display ("FED") device, or an organic light emitting diode ("OLED") display device. Specifically, the flat panel light emitting display device includes a light emitting element that enables pixels to emit light, so that images can be displayed without the need for a backlight unit for providing light to the display panel. Utility Model Content

[0003] An object of the disclosure is to provide a display device capable of protecting a tip of a second bank during etching of an inorganic layer and a method of manufacturing the display device.

[0004] However, the features of the disclosure are not limited to those set forth herein. The above and other features of the disclosure will become more apparent to those skilled in the art to which the disclosure pertains by referring to the detailed description of the disclosure given below.

[0005] In a disclosed embodiment, a display device includes: a substrate; a light-emitting element layer including a first pixel electrode, a first light-emitting layer and a first common electrode stacked sequentially in a first emission region; a first embankment surrounding the first emission region; a second embankment disposed on the first embankment, the second embankment including a tip protruding from a side of the first embankment; and an etching control layer disposed on a top surface of the first common electrode, on a side of the first embankment and on a bottom surface of the tip of the second embankment.

[0006] In an embodiment, the display device may further include: a first electrode pattern disposed on the second bank and surrounding the first emission region, the first electrode pattern including the same material as that of the first common electrode.

[0007] In embodiments, an etch control layer may be disposed on a top surface and a side surface of the first electrode pattern.

[0008] In an embodiment, the display device may further include: a cover layer disposed on the etch control layer in the first emission region; and a first cover pattern disposed on a portion of the etch control layer covering the first electrode pattern, the first cover pattern including the same material as that of the cover layer.

[0009] In an embodiment, the display device may further include a first inorganic layer disposed in the first emission region, on a top surface of the capping layer, on a side of the etching control layer, and on a top surface and a side of the first capping pattern.

[0010] In an embodiment, the light emitting element layer may further include a second pixel electrode, a second light emitting layer, and a second common electrode sequentially stacked in the second emission region.

[0011] In an embodiment, a first embankment may surround a second emission region, a second embankment may be disposed on the first embankment, and an etching control layer may be disposed on a top surface of a second common electrode, on a side of a portion of the first embankment surrounding the second emission region, and on a bottom surface of a tip of the second embankment around the second emission region.

[0012] In an embodiment, the display device may further include: a second electrode pattern disposed on the second bank and surrounding the second emission region, the second electrode pattern including the same material as that of the second common electrode.

[0013] In embodiments, an etch control layer may be disposed on a top surface and a side surface of the second electrode pattern.

[0014] In an embodiment, the display device may further include: a covering layer disposed on the etching control layer in the second emission region; and a second covering pattern disposed on a portion of the etching control layer covering the second electrode pattern, the second covering pattern comprising the same material as that of the covering layer.

[0015] In a disclosed embodiment, the display device includes: a substrate; a first pixel electrode, which is arranged on the substrate in a first emission region; an insulating layer, covering an edge of the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode and the insulating layer; a first common electrode, which is arranged on the first light-emitting layer; a first dam, which is arranged on the insulating layer and surrounds the first emission region; a second dam, which is arranged on the first dam and around the first emission region, the second dam including a tip protruding from a side of the first dam; and an etching control layer, which is arranged on a top surface of the first common electrode, on a side of the first dam, and on a bottom surface of the tip of the second dam.

[0016] In an embodiment, the display device may further include: a first organic pattern disposed on the second embankment, the first organic pattern surrounding the first emission region and including a material that is the same as a material of the first light-emitting layer; and a first electrode pattern disposed on the first organic pattern, the first electrode pattern including a material that is the same as a material of the first common electrode.

[0017] In embodiments, an etch control layer may be disposed on a top surface and a side surface of the first electrode pattern.

[0018] In an embodiment, the display device may further include: a cover layer disposed on the etch control layer in the first emission region; and a first cover pattern disposed on a portion of the etch control layer covering the first electrode pattern, the first cover pattern including the same material as that of the cover layer.

[0019] In an embodiment, the display device may further include a first inorganic layer disposed in the first emission region, on a top surface of the capping layer, on a side of the etching control layer, and on a top surface and a side of the first capping pattern.

[0020] In an embodiment, an evaporation temperature of the etch control layer with respect to a fluorine (F)-based etching gas may be higher than an evaporation temperature of the first inorganic layer with respect to the F-based etching gas.

[0021] In an embodiment, the etch control layer may include at least one of indium gallium zinc oxide ("IGZO"), indium zinc oxide ("IZO"), and gallium zinc oxide ("GZO").

[0022] In an embodiment, the display device may further include: a second pixel electrode disposed on the substrate in the second emission region; a second light emitting layer disposed on the second pixel electrode; and a second common electrode disposed on the second light emitting layer.

[0023] In an embodiment, a first dam may surround a second emission region, a second dam may be disposed on the first dam and around the second emission region, and an etching control layer may be disposed on a top surface of a second common electrode, on a side of a portion of the first dam surrounding the second emission region, and on a bottom surface of a tip of the second dam around the second emission region.

[0024] In an embodiment, the display device may further include: a second organic pattern surrounding the second emission area on the second embankment, the second organic pattern including the same material as the second light-emitting layer; and a second electrode pattern arranged on the second organic pattern, the second electrode pattern including the same material as the second common electrode.

[0025] In embodiments, an etch control layer may be disposed on a top surface and a side surface of the second electrode pattern.

[0026] In an embodiment, the display device may further include: a cover layer disposed on the etch control layer in the second emission region; and a second cover pattern disposed on a portion of the etch control layer covering the second electrode pattern, the second cover pattern including the same material as that of the cover layer.

[0027] In an embodiment, the display device may further include a second inorganic layer disposed in the second emission region, on a top surface of the capping layer, on a side of the etching control layer, and on a top surface and a side of the second capping pattern.

[0028] In a disclosed embodiment, the display device includes: a first pixel electrode, which is arranged on a substrate in a first emission region; an insulating layer, covering an edge of the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode and the insulating layer; a first common electrode, which is arranged on the first light-emitting layer; a first dam, which is arranged on the insulating layer and surrounds the first emission region; a second dam, which is arranged on the first dam and around the first emission region, and the second dam includes a tip protruding from a side of the first dam; an etching control layer, which is arranged on a top surface of the first common electrode, on a side of the first dam, and on a bottom surface of the tip of the second dam; and a covering layer, which is arranged on the etching control layer in the first emission region.

[0029] In an embodiment, the display device may further include: a first organic pattern disposed on the second bank, the first organic pattern surrounding the first emission region and including the same material as the first light emitting layer; and a first electrode pattern disposed on the first organic pattern, the first electrode pattern including the same material as the first common electrode. The etching control layer may be disposed on the top surface and side surfaces of the first electrode pattern.

[0030] In a disclosed embodiment, a method for manufacturing a display device includes the following steps: forming a first pixel electrode and a second pixel electrode on a substrate; sequentially stacking a sacrificial layer, an insulating layer, a first dam and a second dam on the first pixel electrode and the second pixel electrode; forming a tip of the second dam by etching the second dam and the first dam, the tip protruding from a side of the first dam; exposing the first pixel electrode and the second pixel electrode by etching the insulating layer and the sacrificial layer; forming a first light-emitting layer on the first pixel electrode and a first organic pattern on the second dam; forming a first common electrode on the first light-emitting layer and a first electrode pattern on the first organic pattern; and forming an etching control layer, the etching control layer being disposed on a top surface of the first common electrode, on a side of the first dam, on a bottom surface of the tip of the second dam, and on a top surface and a side of the first electrode pattern.

[0031] In an embodiment, the method may further include: forming a covering layer on a portion of the etching control layer covering the first common electrode, and forming a first covering pattern on a portion of the etching control layer covering the first electrode pattern; and forming a first inorganic layer, the first inorganic layer being arranged on the top surface of the covering layer, on the side of the etching control layer, and on the top surface and side of the first covering pattern.

[0032] In an embodiment, the method may further include: forming a photoresist disposed on the first inorganic layer in the first emission region; and etching the first inorganic layer, the first capping pattern, and the capping layer using the photoresist as a mask.

[0033] In an embodiment, etching the first inorganic layer, the first capping pattern, and the capping layer may include preventing a tip of the second bank from being etched by etching the control layer.

[0034] In an embodiment, etching the first inorganic layer, the first capping pattern, and the capping layer may include performing a dry etching process using a fluorine (F)-based etching gas.

[0035] In the display device and the method for manufacturing the display device in the embodiment, since an etching control layer covering the bottom surface of the tip formed on the bank is provided, the tip can be prevented from being damaged or bent during etching of the inorganic layer. As a result, a plurality of light emitting elements can be uniformly formed, and the reliability of the display device can be improved.

[0036] It should be noted that the disclosed effects are not limited to the above-described effects, and other effects of the disclosure will become apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments of the disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is a perspective view of an embodiment of a display device according to the disclosure;

[0039] Figure 2 yes Figure 1 A cross-sectional view of a display device;

[0040] Figure 3 It is shown Figure 1 A plan view of a display unit of a display device;

[0041] Figure 4 It is shown Figure 1 a cross-sectional view of a portion of a display device;

[0042] Figure 5 yes Figure 4 an enlarged cross-sectional view of a region A1 of FIG.

[0043] Figures 6 to 15 is a cross-sectional view showing an embodiment of a method of manufacturing a display device according to the disclosure. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments and implementations disclosed. "Embodiment" and "implementation" as used herein are interchangeable words as non-limiting examples of devices or methods that adopt one or more of the disclosures disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in the form of block diagrams to avoid making various embodiments unnecessarily obscure. In addition, various embodiments may be different, but do not have to be exclusive and do not limit disclosure. For example, without departing from the disclosure, the specific shapes, configurations, and characteristics of the embodiments may be used or implemented in other embodiments.

[0045] Unless otherwise specified, the illustrated embodiments will be understood to provide features of varying details that can implement some of the disclosed methods in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, exchanged and / or rearranged without departing from the disclosure.

[0046] The use of cross-hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. As such, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0047] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments may be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the order described. In addition, the same reference numerals represent the same elements.

[0048] When an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, it may be directly on, directly connected to, or directly bound to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bound to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0049] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore, the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0050] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as for example XYZ, XYY, YZ, ZZ, etc. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the disclosed teachings, the first element discussed below may be referred to as the second element.

[0052] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein and thereby describe the relationship of one element to another element as shown in the accompanying drawings. Spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "under" or "beneath" other elements or features would then be oriented as "above" the other elements or features. Thus, the term "under" may include both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein are interpreted accordingly.

[0053] The terms used here are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "said / the" as used here are intended to also include plural forms. In addition, the terms "comprise", "include" and / or its variations when used in this specification, illustrate the existence of the stated features, wholes, steps, operations, elements, components and / or its groups, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or its groups. It is also noted that, as used here, the terms "substantially", "about (approximately)" and other similar terms are used as approximate terms rather than as degree terms, and are used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art. For example, "about (approximately)" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.

[0054] Here, various embodiments are described with reference to cross-sectional views and / or exploded views as schematic illustrations of embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations, such as those caused by manufacturing techniques and / or tolerances, will be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specifically illustrated regions, but will include deviations in shape caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus need not be intended to be limiting.

[0055] As is customary in the art, some embodiments are described and shown in the accompanying drawings according to functional blocks, units, parts (components) and / or modules. It will be appreciated by those skilled in the art that these blocks, units, parts (components) and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, parts (components) and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, part (component) and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions. In addition, without departing from the scope of disclosure, each block, unit, part (component) and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units, parts (components) and / or modules. In addition, without departing from the scope of disclosure, the blocks, units, parts and / or modules of some embodiments can be physically combined into more complex blocks, units, parts and / or modules.

[0056] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the disclosure, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0057] Hereinafter, detailed embodiments of the disclosure are described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view of a display device according to the disclosure.

[0059] Reference Figure 1The display device 10 is applicable to portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), mobile communication terminals, electronic notepads, electronic book ("e-book") readers, portable multimedia players ("PMPs"), navigation devices, or ultra-mobile PCs ("UMPCs"). In an embodiment, for example, the display device 10 may be applied as a display unit of a television ("TV"), a notebook computer, a monitor, a billboard, or an Internet of Things ("IoT") device. In another embodiment, the display device 10 may be applied to a wearable device such as a smart watch, a watch phone, a glasses display, or a head-mounted display ("HMD").

[0060] The display device 10 may have an approximately rectangular shape in a plan view. In an embodiment, for example, the display device 10 may have an approximately rectangular shape in a plan view, the approximately rectangular shape having a short side in the X-axis direction and a long side in the Y-axis direction. The corner where the short side and the long side of the display device 10 meet may be rounded (rounded) or right angled. However, the planar shape of the display device 10 is not particularly limited, and the display device 10 may be formed in various other shapes (such as other polygonal shapes, circular shapes, or elliptical shapes).

[0061] The display device 10 may include a display panel 100 , a display driving unit 200 , a circuit board 300 , and a touch driving unit 400 .

[0062] The display panel 100 may include a main area MA and a sub area SBA.

[0063] The main area MA may include a display area DA and a non-display area NDA, the display area DA includes pixels for displaying an image, and the non-display area NDA is arranged around the display area DA. The display area DA may emit light through a plurality of emission areas or openings. In an embodiment, for example, the display panel 100 may include a pixel circuit, a pixel defining film defining an emission area or an opening, and a self-luminous element, and the pixel circuit includes a switching element.

[0064] In an embodiment, the self-luminous element may include, for example, an organic light emitting diode ("OLED"), a quantum dot light emitting diode ("LED") including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and / or a micro LED, but the disclosure is not limited thereto.

[0065] The non-display area NDA may be outside the display area DA. The non-display area NDA may be defined as an edge portion of the main area MA. The non-display area NDA may include a gate driving unit (not shown) that provides a gate signal to a gate line and a fan-out line (not shown) that connects the display driving unit 200 and the display area DA.

[0066] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that is bendable, foldable, or rollable. In an embodiment, for example, when the sub-area SBA is bendable, the sub-area SBA may be bent to overlap with the main area MA in the thickness direction (or Z-axis direction). The sub-area SBA may include a display drive unit 200 and a pad (or referred to as a "pad") unit connected to the circuit board 300. In some embodiments, the sub-area SBA may not be provided, and the display drive unit 200 and the pad unit may be provided in the non-display area NDA.

[0067] The display driving unit 200 may output a signal and a voltage for driving the display panel 100. The display driving unit 200 may provide a data voltage to a data line. The display driving unit 200 may provide a power supply voltage to a power line, and may provide a gate control signal to a gate driving unit. The display driving unit 200 may be formed as an integrated circuit ("IC"), and may be disposed (e.g., mounted) on the display panel 100 in a chip on glass ("COG") or chip on plastic ("COP") manner or via ultrasonic bonding. In an embodiment, for example, the display driving unit 200 may be disposed in a sub-area SBA, and may overlap with the main area MA in a thickness direction (or Z-axis direction) when the sub-area SBA is bent. In another embodiment, the display driving unit 200 may be disposed (e.g., mounted) on a circuit board 300.

[0068] The circuit board 300 may be attached to the pad unit of the display panel 100 via an anisotropic conductive film ("ACF"). The conductive lines of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a printed circuit board ("PCB"), a flexible PCB ("FPCB"), or a flexible film such as a chip on film ("COF").

[0069] The touch drive unit 400 may be disposed (e.g., mounted) on the circuit board 300. The touch drive unit 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch drive unit 400 may provide a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense a capacitance change between the touch electrodes. In an embodiment, for example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch drive unit 400 may determine the presence of an input based on the capacitance change between the touch electrodes, and may calculate the coordinates of the input. The touch drive unit 400 may be formed as an IC.

[0070] Figure 2 yes Figure 1 A cross-sectional view of a display device.

[0071] Reference Figure 2The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor ("TFT") layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0072] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable, or rollable. In an embodiment, the substrate SUB may include a polymer resin such as polyimide ("PI"), but the disclosure is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0073] The TFT layer TFTL may be disposed on the substrate SUB. The TFT layer TFTL may include a plurality of TFTs forming a pixel circuit of a pixel. The TFT layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driving unit 200 and the data line, and a wire connecting the display driving unit 200 and the pad unit. The TFT may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, in the case where the gate driving unit is formed on one side of the non-display area NDA of the display panel 100, the gate driving unit may include a TFT.

[0074] The TFT layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The TFTs, gate lines, data lines, and power lines of the TFT layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the TFT layer TFTL may be disposed in the non-display area NDA. The conductive lines of the TFT layer TFTL may be disposed in the sub-area SBA.

[0075] The light emitting element layer EML may be disposed on the TFT layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements in which pixel electrodes, light emitting layers, and common electrodes are sequentially stacked to emit light, and a pixel defining film defining pixels. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0076] In an embodiment, for example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the TFT of the TFT layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, electrons may move to the organic light-emitting layer through the electron transport layer, and holes and electrons may be combined in the organic light-emitting layer to emit light. In an embodiment, for example, the pixel electrode and the common electrode may be an anode and a cathode, respectively, but the disclosure is not limited thereto.

[0077] In another embodiment, the light emitting element may be a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, or a micro LED.

[0078] The encapsulation layer TFEL may cover the top surface and the side of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0079] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for detecting a touch input from a user in a capacitive manner and a touch line for connecting the touch electrodes and the touch driving unit 400. In an embodiment, the touch sensing unit TSU may sense a touch input from a user in a mutual capacitance manner or in a self-capacitance manner.

[0080] In another embodiment, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this example, the separate substrate may be a packaging substrate for the display unit DU.

[0081] The touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor region overlapping the display area DA. The touch lines of the touch sensing unit TSU may be disposed in a touch peripheral region overlapping the non-display area NDA.

[0082] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a color filter ( Figure 4 CF1, CF2 and CF3), color filter ( Figure 4 CF1, CF2 and CF3 in the figure correspond to their corresponding emission areas. Figure 4 CF1, CF2, and CF3 in the color filter can selectively transmit light of a specific wavelength through it (them), and can block or absorb light of other wavelengths. Figure 4 CF1, CF2 and CF3 in the filter can reduce the reflected light of the external light by absorbing some of the external light. Figure 4 CF1, CF2, and CF3) in the circuit can prevent color distortion that may be caused by external light.

[0083] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be reduced.

[0084] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that is bendable, foldable, or rollable. In an embodiment, for example, when the sub-region SBA is bent downward, the sub-region SBA may overlap the main region MA in the thickness direction (or Z-axis direction). The sub-region SBA may include a display driving unit 200 and a pad unit electrically connected to the circuit board 300.

[0085] Figure 3 It is shown Figure 1 A plan view of a display unit of a display device.

[0086] Reference Figure 3 , the display unit DU may include a display area DA and a non-display area NDA.

[0087] The display area DA as an area displaying an image may be defined as a central area of ​​the display panel 100. The display area DA may include a plurality of pixels SP, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL. The pixel SP may be defined as a minimum unit for emitting light.

[0088] The gate lines GL may provide the pixels SP with gate signals received from the gate driving unit 210. The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction.

[0089] The data lines DL may provide the pixels SP with data voltages received from the display driving unit 200. The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0090] The power lines VL may provide the pixels SP with a power voltage received from the display driving unit 200. Here, the power voltage includes at least one of a driving voltage, an initialization voltage, a reference voltage, a bias voltage, and a relatively low potential voltage. The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction.

[0091] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driving unit 210, a fan-out line FOL, and a gate control line GCL. The gate driving unit 210 may generate a plurality of gate signals based on a gate control signal and may sequentially provide the gate signals to the gate lines GL in a predetermined order.

[0092] The fan-out line FOL may extend from the display driving unit 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driving unit 200 to the data line DL.

[0093] The gate control line GCL may extend from the display driving unit 200 to the gate driving unit 210. The gate control line GCL may provide the gate driving unit 210 with a gate control signal received from the display driving unit 200.

[0094] The sub-area SBA may include the display driving unit 200 , the display pad area DPA, and first and second touch pad areas TPA1 and TPA2 .

[0095] The display driving unit 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driving unit 200 may provide a data voltage to the data line DL through the fan-out line FOL. The data voltage may be provided to the pixel SP and may determine the brightness of the pixel SP. The display driving unit 200 may provide a gate control signal to the gate driving unit 210 through the gate control line GCL.

[0096] The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The display pad area DPA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 via a relatively low resistance, relatively high reliability material such as anisotropic conductive film ("ACF") or self-assembly anisotropic conductive paste ("SAP").

[0097] The display pad area DPA may include a plurality of display pads DP. The display pad DP may be electrically connected to a graphic system via the circuit board 300. The display pad DP may be connected to the circuit board 300 and thus may receive digital video data and provide the digital video data to the display driving unit 200.

[0098] The first touch pad area TPA1 may be disposed at one side of the display pad area DPA and may include a plurality of first touch pads TP1. The first touch pads TP1 may be electrically connected to the touch driving unit 400 disposed on the circuit board 300. The first touch pads TP1 may provide a touch driving signal to a plurality of driving electrodes via a plurality of driving lines.

[0099] The second touch pad area TPA2 may be disposed at the other side of the display pad area DPA, and may include a plurality of second touch pads TP2. The second touch pads TP2 may be electrically connected to a touch drive unit 400 disposed on the circuit board 300. The touch drive unit 400 may receive a touch sensing signal via a plurality of sensing lines connected to the second touch pads TP2, and may sense a change in mutual capacitance between the driving electrode and the sensing electrode.

[0100] Figure 4 It is shown Figure 1 A cross-sectional view of a portion of a display device, Figure 5yes Figure 4 An enlarged cross-sectional view of area A1.

[0101] Reference Figure 4 and Figure 5 The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a TFT layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0102] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that is bendable, foldable or rollable. In an embodiment, the substrate SUB may include a polymer resin such as PI, but the disclosure is not limited thereto. In another embodiment, the substrate SUB may include a glass or metal material.

[0103] The TFT layer TFTL may include a first buffer layer BF1, a light blocking layer BML, a second buffer layer BF2, a TFT TR, a gate insulating layer GI, a first intermediate insulating layer ILD1, a capacitor electrode CPE, a second intermediate insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0104] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture from penetrating. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0105] The light blocking layer BML may be disposed on the first buffer layer BF1. In an embodiment, for example, the light blocking layer BML may be formed as a single layer or multiple layers including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or any alloy thereof, but the disclosure is not limited thereto. In another embodiment, the light blocking layer BML may be an organic film including a black pigment.

[0106] The second buffer layer BF2 may be disposed on the first buffer layer BF1 and the light blocking layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing air or moisture from penetrating. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0107] The TFT TR may be disposed on the second buffer layer BF2 and may form a pixel circuit of a plurality of pixels. In an embodiment, for example, the TFT TR may be a driving transistor or a switching transistor. The TFT TR may include a semiconductor region ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE. In an embodiment, the source electrode SE and the drain electrode DE may be switched with each other based on the type of the TFT TR.

[0108] The semiconductor region ACT, the source electrode SE, and the drain electrode DE may be disposed on the second buffer layer BF2. The semiconductor region ACT, the source electrode SE, and the drain electrode DE may overlap the light blocking layer BML in the thickness direction. The semiconductor region ACT may overlap the gate electrode GE in the thickness direction and may be insulated from the gate electrode GE by the gate insulating layer GI. The source electrode SE and the drain electrode DE may be obtained by converting the material of the semiconductor region ACT into a conductor.

[0109] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor region ACT with the gate insulating layer GI interposed therebetween.

[0110] The gate insulating layer GI may be disposed on the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the second buffer layer BF2. The gate insulating layer GI may insulate the semiconductor region ACT from the gate electrode GE.

[0111] A first intermediate insulating layer ILD1 may be disposed on the gate electrode GE and the gate insulating layer GI. The first intermediate insulating layer ILD1 may insulate the gate electrode GE from the capacitor electrode CPE.

[0112] The capacitor electrode CPE may be disposed on the first intermediate insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0113] The second intermediate insulating layer ILD2 may be disposed on the capacitor electrode CPE and the first intermediate insulating layer ILD1. The second intermediate insulating layer ILD2 may insulate the capacitor electrode CPE from the first connection electrode CNE1.

[0114] The first connection electrode CNE1 may be disposed on the second intermediate insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the TFT TR and the second connection electrode CNE2. The first connection electrode CNE1 may be inserted in a contact hole of each of the second intermediate insulating layer ILD2, the first intermediate insulating layer ILD1, and the gate insulating layer GI, and thus may contact the drain electrode DE of the TFT TR.

[0115] The first passivation layer PAS1 may be disposed on the first connection electrode CNE1 and the second intermediate insulating layer ILD2. The first passivation layer PAS1 may protect the TFT TR. The first passivation layer PAS1 may insulate the first connection electrode CNE1 from the second connection electrode CNE2.

[0116] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the first pixel electrode AE1 of the first light emitting element ED1. The second connection electrode CNE2 may be inserted into the contact hole of the first passivation layer PAS1 and thus may contact the first connection electrode CNE1.

[0117] The second passivation layer PAS2 may be disposed on the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may insulate the second connection electrode CNE2 from the first pixel electrode AE1.

[0118] In an embodiment, for example, the substrate SUB and the TFT layer TFTL may be incorporated into a silicon (Si) wafer, but the disclosure is not limited thereto. In this example, the light emitting element layer EML may be formed on the Si wafer, and since the display device 10 includes the Si wafer, an image with ultra-high resolution may be realized.

[0119] The light emitting element layer EML may be disposed on the TFT layer TFTL. The light emitting element layer EML may include first, second, and third light emitting elements ED1, ED2, and ED3, a residual pattern RP, a first insulating layer IL1, an etching control layer ECL, a capping layer CAP, a bank BNK, first, second, and third organic patterns ELP1, ELP2, and ELP3, first, second, and third electrode patterns CEP1, CEP2, and CEP3, first, second, and third capping patterns CLP1, CLP2, and CLP3, and first, second, and third inorganic layers TL1, TL2, and TL3.

[0120] The display device 10 may include a plurality of pixels arranged in a plurality of rows and a plurality of columns. Each of the pixels may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 defined by a bank BNK or a pixel defining film, and light having a predetermined peak wavelength may be emitted through the first emission area EA1, the second emission area EA2, and the third emission area EA3. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be an area where light generated by the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 is output to the outside of the display device 10.

[0121] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit light having a predetermined peak wavelength to the outside of the display device 10. The first emission area EA1 may emit a first color light, the second emission area EA2 may emit a second color light, and the third emission area EA3 may emit a third color light. In an embodiment, for example, the first color light may be red light having a peak wavelength of about 610 nanometers (nm) to about 650nm, the second color light may be green light having a peak wavelength of about 510nm to about 550nm, and the third color light may be blue light having a peak wavelength of about 440nm to about 480nm. However, the disclosure is not limited to this example.

[0122] In an embodiment, for example, the third emission area EA3 may be larger in size than the first emission area EA1, and the first emission area EA1 may be larger in size than the second emission area EA2. However, the disclosure is not limited to this example. In another embodiment, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have substantially the same size as each other.

[0123] The first light emitting element ED1 may be disposed on the TFT layer TFTL in the first emission area EA1. The first light emitting element ED1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a first common electrode CE1. The second light emitting element ED2 may be disposed in the second emission area EA2 on the TFT layer TFTL. The second light emitting element ED2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a second common electrode CE2. The third light emitting element ED3 may be disposed in the third emission area EA3 on the TFT layer TFTL. The third light emitting element ED3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a third common electrode CE3.

[0124] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the second passivation layer PAS2. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be connected to the drain electrode DE of the TFT TR through the first connection electrode CNE1 and the second connection electrode CNE2. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other by the first insulating layer IL1. In an embodiment, for example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include at least one of Ag, Cu, Al, Ni, and lanthanum (La). In another embodiment, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a material such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), or indium tin zinc oxide ("ITZO"). In yet another example, the first pixel electrode AE1 , the second pixel electrode AE2 , and the third pixel electrode AE3 may have a stack structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0125] The first insulating layer IL1 may be disposed on the second passivation layer PAS2 and the residual pattern RP. The first insulating layer IL1 may cover the edge of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the residual pattern RP, and may expose a portion of the top surface of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. In an embodiment, for example, the first insulating layer IL1 may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0126] The residual pattern RP may be disposed on an edge of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The residual pattern RP may be disposed between the first insulating layer IL1 and the top surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. Due to the presence of the residual pattern RP, the first insulating layer IL1 may not be in direct contact with the top surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The residual pattern RP may be formed by removing a sacrificial layer ( Figure 6 The "SFL" is formed.

[0127] The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be organic light-emitting layers including or consisting of an organic material, and may be formed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, respectively, via a deposition process. In an embodiment, for example, during deposition of the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3, the organic material may be deposited in an oblique direction relative to the top surface of the substrate SUB.

[0128] The first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. A portion of the first light emitting layer EL1 may fill the space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another portion of the first light emitting layer EL1 may cover a portion of the top surface of the first insulating layer IL1 and some side surfaces of the first insulating layer IL1. The second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. A portion of the second light emitting layer EL2 may fill the space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another portion of the second light emitting layer EL2 may cover a portion of the top surface of the first insulating layer IL1 and some side surfaces of the first insulating layer IL1. The third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light emitting layer EL3 may fill the space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a portion of the top surface of the first insulating layer IL1 and some side surfaces of the first insulating layer IL1.

[0129] The first common electrode CE1 may be disposed on the first light emitting layer EL1, the second common electrode CE2 may be disposed on the second light emitting layer EL2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may include a transparent conductive material and may allow light generated by the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 to transmit therethrough. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may contact a side of the first bank BNK1 and may be electrically connected through the first bank BNK1. In an embodiment, for example, the first common electrode CE1 may receive a common voltage, a cathode voltage, or a relatively low potential voltage.

[0130] The first pixel electrode AE1 may receive a voltage corresponding to the data voltage from one of the TFTs TR, and the first common electrode CE1 may receive a common voltage, a cathode voltage, or a relatively low potential voltage. In this case, when a potential difference is generated between the first pixel electrode AE1 and the first common electrode CE1, holes and electrons may move to the first light emitting layer EL1 through the hole transport layer and the electron transport layer, respectively, and as a result, the first light emitting layer EL1 may emit light.

[0131] The etching control layer ECL may be disposed on the top surface of each of the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3, the side of the first bank BNK1, the bottom surface of the tip of the second bank BNK2, and the top surface and side of each of the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3. The etching control layer ECL may be formed by an atomic layer deposition ("ALD") process, but the disclosure is not limited thereto. The etching control layer ECL may be uniformly deposited on the side of the first bank BNK1 and the bottom surface of the tip of the second bank BNK2 via ALD. In an embodiment, the etching control layer ECL may include at least one of indium gallium zinc oxide ("IGZO"), indium zinc oxide ("IZO"), and gallium zinc oxide ("GZO"). The etching control layer ECL may be used as an etching stopper. The evaporation temperature of the etching control layer ECL for F-based etching gas may be higher than the evaporation temperature of the first inorganic layer TL1 for F-based etching gas. The etching control layer ECL may not be etched during the dry etching process using the F-based etching gas due to its relatively high evaporation temperature, and thus the tip of the second bank BNK2 may be prevented from being etched. Therefore, the etching control layer ECL may protect the tip of the second bank BNK2 during the etching of the first inorganic layer TL1 and the second inorganic layer TL2. Since the display device 10 includes the etching control layer ECL, the tip of the second bank BNK2 may be prevented from being damaged or bent, and the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be uniformly formed. In addition, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 may be uniformly formed, so that the reliability of the display device 10 may be ensured.

[0132] The capping layer CAP may be disposed on the etching control layer ECL in the first emission region EA1, the second emission region EA2, and the third emission region EA3. The capping layer CAP may include an inorganic insulating material and may cover the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3. The capping layer CAP may prevent the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 from being damaged by external air. In an embodiment, for example, the capping layer CAP may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0133] The bank BNK may be disposed on the first insulating layer IL1 to define the first, second, and third emission regions EA1, EA2, and EA3. The bank BNK may surround the first, second, and third emission regions EA1, EA2, and EA3 in a plan view. The bank BNK may include a first bank BNK1 and a second bank BNK2.

[0134] The first bank BNK1 may be disposed on the first insulating layer IL1, and the second bank BNK2 may be disposed on the first bank BNK1. A side of the first bank BNK1 may be recessed inward from a corresponding side of the second bank BNK2. A side of the second bank BNK2 may protrude from a corresponding side of the first bank BNK1 toward the first emission region EA1, and thus may include a protruding tip. Therefore, an undercut may be formed under the tip of the second bank BNK2. The first bank BNK1 may be thicker than the second bank BNK2.

[0135] The first bank BNK1 and the second bank BNK2 may include different metal materials. The first bank BNK1 and the second bank BNK2 may have different etching rates. In an embodiment, for example, in a wet etching process, during the formation of the first emission area EA1, the second emission area EA2, and the third emission area EA3, the first bank BNK1 may be etched faster and by a larger amount than the second bank BNK2. Therefore, the shape of the side of the first bank BNK1 and the side of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The first bank BNK1 may include a metal material having a relatively high conductivity, and the second bank BNK2 may include a material having a relatively low reflectivity. In an embodiment, for example, the first bank BNK1 may include Al, and the second bank BNK2 may include Ti. However, the disclosure is not limited to this example.

[0136] The openings forming the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be defined in the bank BNK that may overlap the light blocking member BM of the color filter layer CFL. The first bank BNK1 may electrically connect the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 that are spaced apart from each other. The second bank BNK2 may include a material having a relatively low reflectivity, and thus may be able to reduce reflection of external light.

[0137] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may be formed through the dam BNK via a mask process, and the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may be formed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, respectively. The mask process may require a structure for mounting a mask and a relatively large non-display area NDA for allocation control. When the mask process can be minimized, the structure for mounting a mask may not be provided, and the size of the non-display area NDA for allocation control may be minimized.

[0138] The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be formed by a deposition and etching process rather than by a mask process. Since the first bank BNK1 and the second bank BNK2 include different metal materials, the inner sidewall of each of the banks BNK may include a tip, and different layers may be separately formed in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 via a deposition process. In an embodiment, for example, the first light emitting layer EL1 and the first organic pattern ELP1 may include or be composed of the same organic material by a deposition process without using a mask, and may be cut and separated from each other by a tip on the inner sidewall of each of the banks BNK. The first light emitting layer EL1 may be disposed in the first emission area EA1, and the first organic pattern ELP1 may be disposed on a portion of the bank BNK around the first emission area EA1.

[0139] The organic material for forming the first light-emitting layer EL1 may be deposited on the entire surface of the display device 10, and may be removed from the second emission area EA2 and the third emission area EA3. The organic material for forming the second light-emitting layer EL2 may be deposited on the entire surface of the display device 10, and may be removed from the first emission area EA1 and the third emission area EA3. The organic material for forming the third light-emitting layer EL3 may be deposited on the entire surface of the display device 10, and may be removed from the first emission area EA1 and the second emission area EA2. Therefore, different organic layers may be formed in different emission areas by a deposition process and an etching process rather than by a mask process. Since unnecessary processes may be omitted, the manufacturing cost of the display device 10 may be reduced, and the size of the non-display area NDA may be minimized.

[0140] The first organic pattern ELP1 may include the same organic material as that of the first light emitting layer EL1, and may be disposed on the second bank BNK2. The first organic pattern ELP1 may cover the top surface and side surfaces of a portion of the second bank BNK2 around the first emission area EA1. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited by the same process, and may be cut and separated from each other by a tip formed on the second bank BNK2. Therefore, the first organic pattern ELP1 may be disposed on the second bank BNK2 in an area around the first emission area EA1.

[0141] The first electrode pattern CEP1 may include the same metal material as that of the first common electrode CE1, and may be disposed on the first organic pattern ELP1. The first electrode pattern CEP1 may cover the top surface and the side of the first organic pattern ELP1. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in the area around the first emission area EA1.

[0142] The first capping pattern CLP1 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL in the first emission area EA1 and its surrounding area. The first capping pattern CLP1 may cover the top surface and side surfaces of a portion of the etching control layer ECL covering the first electrode pattern CEP1. The capping layer CAP and the first capping pattern CLP1 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the first capping pattern CLP1 may be disposed on a portion of the etching control layer ECL covering the first electrode pattern CEP1.

[0143] The first inorganic layer TL1 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and side of the first capping pattern CLP1 in the first emission area EA1 and the surrounding area thereof. The first inorganic layer TL1 may be disposed in the first emission area EA1 and the surrounding area thereof to cover the side of the etching control layer ECL covering the corresponding side of the first dam BNK1. The first inorganic layer TL1 may include an inorganic material and may prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. In an embodiment, for example, the first inorganic layer TL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0144] The second organic pattern ELP2 may include the same organic material as that of the second light emitting layer EL2, and may be disposed on the second bank BNK2. The second organic pattern ELP2 may cover the top surface and side surfaces of a portion of the second bank BNK2 around the second emission area EA2. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the second organic pattern ELP2 may be disposed on the second bank BNK2 in the area around the second emission area EA2.

[0145] The second electrode pattern CEP2 may include the same material as that of the second common electrode CE2 and may be disposed on the second organic pattern ELP2. The second electrode pattern CEP2 may cover the top surface and the side of the second organic pattern ELP2. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited by the same process and may be cut and separated by the tip of the second bank BNK2. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in the area around the second emission area EA2.

[0146] The second covering pattern CLP2 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL in the second emission area EA2 and its surrounding area. The second covering pattern CLP2 may cover the top surface and side surfaces of a portion of the etching control layer ECL covering the second electrode pattern CEP2. The capping layer CAP and the second covering pattern CLP2 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the second covering pattern CLP2 may be disposed on a portion of the etching control layer ECL covering the second electrode pattern CEP2.

[0147] The second inorganic layer TL2 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and side of the second capping pattern CLP2 in the second emission area EA2 and the surrounding area thereof. The second inorganic layer TL2 may be disposed in the second emission area EA2 and the surrounding area thereof to cover the side of the etching control layer ECL covering the corresponding side of the second embankment BNK2. The second inorganic layer TL2 may include an inorganic material and may prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. In an embodiment, for example, the second inorganic layer TL2 may include one of the aforementioned exemplary materials for forming the first inorganic layer TL1 or be composed of one of the aforementioned exemplary materials for forming the first inorganic layer TL1.

[0148] The third organic pattern ELP3 may include the same organic material as that of the third light emitting layer EL3, and may be disposed on the second bank BNK2. The third organic pattern ELP3 may cover the top surface and side surfaces of a portion of the second bank BNK2 around the third emission area EA3. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited by the same process, and may be cut by the tip of the second bank BNK2. Therefore, the third organic pattern ELP3 may be disposed on the second bank BNK2 in an area around the third emission area EA3.

[0149] The third electrode pattern CEP3 may include the same metal material as the metal material of the third common electrode CE3, and may be disposed on the third organic pattern ELP3. The third electrode pattern CEP3 may cover the top surface and the side of the third organic pattern ELP3. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in the area around the third emission area EA3.

[0150] The third covering pattern CLP3 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL in the third emission area EA3 and its surrounding area. The third covering pattern CLP3 may cover the top surface and side surfaces of a portion of the etching control layer ECL covering the third electrode pattern CEP3. The capping layer CAP and the third covering pattern CLP3 may be deposited by the same process, and may be cut and separated by the tip of the second bank BNK2. Therefore, the third covering pattern CLP3 may be disposed on a portion of the etching control layer ECL covering the third electrode pattern CEP3.

[0151] The third inorganic layer TL3 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and side of the third capping pattern CLP3 in the third emission area EA3 and the surrounding area thereof. The third inorganic layer TL3 may be disposed in the third emission area EA3 and the surrounding area thereof to cover the side of the etching control layer ECL covering the corresponding side of the first embankment BNK1. The third inorganic layer TL3 may include an inorganic material and may prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. In an embodiment, for example, the third inorganic layer TL3 may include one of the aforementioned exemplary materials for forming the first inorganic layer TL1 or be composed of one of the aforementioned exemplary materials for forming the first inorganic layer TL1.

[0152] The encapsulation layer TFEL may be disposed on the first, second, and third inorganic layers TL1, TL2, and TL3 to cover the light emitting element layer EML. The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3.

[0153] The first encapsulation layer TFE1 may be disposed on the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The first encapsulation layer TFE1 may cover an exposed portion of the second bank BNK2 between the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The first encapsulation layer TFE1 may include an inorganic material, and thus may prevent oxygen or moisture from penetrating into the light emitting element layer EML. In an embodiment, for example, the first encapsulation layer TFE1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0154] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1 to flatten the top of the light emitting element layer EML. The second encapsulation layer TFE2 may include an organic material and may protect the light emitting element layer EML from foreign matter such as dust. In an embodiment, for example, the second encapsulation layer TFE2 may include an organic film including or consisting of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a PI resin. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0155] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2. The third encapsulation layer TFE3 may include an inorganic material and may prevent oxygen or moisture from penetrating into the light emitting element layer EML. In an embodiment, for example, the third encapsulation layer TFE3 may include or consist of one of the aforementioned exemplary materials for forming the first encapsulation layer TFE1.

[0156] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a third buffer layer BF3, a bridge electrode BRG, a second insulating layer IL2, a touch electrode TE, and a third insulating layer IL3.

[0157] The third buffer layer BF3 may be disposed on the encapsulation layer TFEL. The third buffer layer BF3 may have an insulating function and an optical function. The third buffer layer BF3 may include at least one inorganic film. In some embodiments, the third buffer layer BF3 may not be disposed.

[0158] The bridge electrode BRG may be disposed on the third buffer layer BF3. The bridge electrode BRG may be disposed in a different layer from the touch electrode TE, and may electrically connect the touch electrodes TE to each other.

[0159] The second insulating layer IL2 may be disposed on the bridge electrode BRG and the third buffer layer BF3. The second insulating layer IL2 may have an insulating function and an optical function. In an embodiment, for example, the second insulating layer IL2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0160] The touch electrode TE may be disposed on the second insulating layer IL2. The touch electrode TE may include a drive electrode and a sensing electrode, and may sense a change in mutual capacitance between the drive electrode and the sensing electrode. The touch electrode TE may not overlap the first emission area EA1, the second emission area EA2, and the third emission area EA3. The touch electrode TE may be formed as a single layer including Mo, Ti, Cu, Al, or ITO, or as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and ITO (e.g., ITO / Al / ITO), a multilayer of a silver (Ag)-palladium (Pd)-copper (Cu) (APC) alloy, or a stack of an APC alloy and ITO (e.g., ITO / APC / ITO).

[0161] The third insulating layer IL3 may be disposed on the touch electrode TE and the second insulating layer IL2. The third insulating layer IL3 may have an insulating function and an optical function. The third insulating layer IL3 may include one of the aforementioned exemplary materials for forming the second insulating layer IL2 or may be composed of one of the aforementioned exemplary materials for forming the second insulating layer IL2.

[0162] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a light blocking member BM, a plurality of color filters, and a planarization layer OC.

[0163] The light blocking member BM may be disposed on the third insulating layer IL3 and may surround the first optical region OPT1, the second optical region OPT2, and the third optical region OPT3. The light blocking member BM may overlap the touch electrode TE. The light blocking member BM may include a light absorbing material and may prevent reflection of light. In an embodiment, for example, the light blocking member BM may include an inorganic black pigment, an organic black pigment, or an organic blue pigment. The inorganic black pigment may be carbon black or a metal oxide such as Ti black, the organic black pigment may be at least one of lactam black, perylene black, and aniline black, and the organic blue pigment may be CI pigment blue. However, the disclosure is not limited thereto. The light blocking member BM may improve the color reproducibility of the display device 10 by preventing color mixing caused by visible light passing through the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0164] The color filter may include first, second, and third color filters CF1, CF2, and CF3. The first, second, and third color filters CF1, CF2, and CF3 may be disposed on the third insulating layer IL3 to correspond to the first, second, and third emission regions EA1, EA2, and EA3, respectively.

[0165] The first color filter CF1 may be disposed on the third insulating layer IL3 in the first emission region EA1. In a plan view, the first color filter CF1 may surround the first emission region EA1. The edge of the first color filter CF1 may cover a portion of the top surface of the light blocking member BM, but the disclosure is not limited thereto. The first color filter CF1 may selectively allow the first color light (e.g., red light) to transmit therethrough, and may block or absorb the second color light (e.g., green light) and the third color light (e.g., blue light). In an embodiment, for example, the first color filter CF1 may be a red color filter and may include a red colorant.

[0166] The second color filter CF2 may be disposed on the third insulating layer IL3 in the second emission region EA2. In a plan view, the second color filter CF2 may surround the second emission region EA2. The edge of the second color filter CF2 may cover a portion of the top surface of the light blocking member BM, but the disclosure is not limited thereto. The second color filter CF2 may selectively transmit the second color light (e.g., green light) through it, and may block or absorb the first color light (e.g., red light) and the third color light (e.g., blue light). In an embodiment, for example, the second color filter CF2 may be a green color filter and may include a green colorant.

[0167] The third color filter CF3 may be disposed on the third insulating layer IL3 in the third emission area EA3. In a plan view, the third color filter CF3 may surround the third emission area EA3. The edge of the third color filter CF3 may cover a portion of the top surface of the light blocking member BM, but the disclosure is not limited thereto. The third color filter CF3 may selectively transmit a third color light (e.g., blue light) through it, and may block or absorb a first color light (e.g., red light) and a second color light (e.g., green light). In an embodiment, for example, the third color filter CF3 may be a blue color filter and may include a blue colorant.

[0168] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may reduce reflected light of external light by absorbing some of the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may prevent color distortion that may be caused by reflection of external light.

[0169] A planarization layer OC may be disposed on the light blocking member BM and the first, second, and third color filters CF1, CF2, and CF3. The planarization layer OC may planarize the top of the color filter layer CFL. In an embodiment, for example, the planarization layer OC may include an organic insulating material.

[0170] Figures 6 to 15 is a cross-sectional view showing an embodiment of a method of manufacturing a display device according to the disclosure.

[0171] Reference Figure 6, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the TFT layer TFTL. In an embodiment, for example, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include at least one of Ag, Cu, Al, Ni, and La, respectively. In another embodiment, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include ITO, IZO, or ITZO, respectively. In another embodiment, the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO, respectively.

[0172] A sacrificial layer SFL may be disposed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The sacrificial layer SFL may be disposed between the top surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 and the first insulating layer IL1. The sacrificial layer SFL may include an oxide semiconductor. In an embodiment, for example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide ("IGZO"), zinc tin oxide ("ZTO"), and IZO.

[0173] A first insulating layer IL1 may be disposed on the TFT layer TFTL and the sacrificial layer SFL. The first insulating layer IL1 may include an inorganic insulating material. The first insulating layer IL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0174] A first bank BNK1 may be disposed on the first insulating layer IL1, and a second bank BNK2 may be disposed on the first bank BNK1. The first bank BNK1 may be thicker than the second bank BNK2.

[0175] A photoresist PR not overlapping the first, second, and third pixel electrodes AE1, AE2, and AE3 may be disposed on the second bank BNK2. The photoresist PR may be disposed in regions other than regions where the first, second, and third emission regions EA1, EA2, and EA3 are to be formed.

[0176] Reference Figure 7, the second bank BNK2 and the first bank BNK1 may be sequentially etched using the photoresist PR as a mask, and a plurality of holes may be formed. The hole may overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3. The first bank BNK1 and the second bank BNK2 may be etched by at least one of dry etching and wet etching. In an embodiment, the first bank BNK1 and the second bank BNK2 may be etched first by dry etching and secondly by wet etching, but the disclosure is not limited thereto. The first bank BNK1 and the second bank BNK2 may include different metal materials and may have different etching rates. In the wet etching process, the first bank BNK1 may be etched faster and etched more than the second bank BNK2. Therefore, the shape of the side of the first bank BNK1 and the side of the second bank BNK2 may be determined by the difference in etching rate between the first bank BNK1 and the second bank BNK2. The second bank BNK2 may include a tip protruding from the first bank BNK1 toward the hole. The side of the first bank BNK1 may be recessed inward from the corresponding side of the second bank BNK2. An undercut may be formed below a tip of the second bank BNK2 . The first bank BNK1 may be thicker than the second bank BNK2 .

[0177] The first bank BNK1 may include a metal material having relatively high conductivity, and the second bank BNK2 may include a material having relatively low reflectivity. In an embodiment, for example, the first bank BNK1 may include Al, and the second bank BNK2 may include Ti. However, the disclosure is not limited to this example.

[0178] The first insulating layer IL1 and the sacrificial layer SFL may be etched by at least one of dry etching and wet etching. In an embodiment, for example, the first insulating layer IL1 may be etched by dry etching, and the sacrificial layer SFL may be etched by wet etching. However, the disclosure is not limited to this example. When etching the first insulating layer IL1 and the sacrificial layer SFL, at least a portion of the top surfaces of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be exposed. In the wet etching process, the sacrificial layer SFL may be etched more than the first insulating layer IL1. When etching the sacrificial layer SFL, a residual pattern RP may be retained between the first insulating layer IL1 and the first pixel electrode AE1. Therefore, the side of each of the residual patterns RP may be recessed inward from the side of the first insulating layer IL1.

[0179] Reference Figure 8, the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1 in the first emission area EA1. Part of the first light emitting layer EL1 may fill the space surrounded by the first pixel electrode AE1, the residual pattern RP, and the first insulating layer IL1, and another part of the first light emitting layer EL1 may cover part of the top surface of the first insulating layer IL1 and some of the sides of the first insulating layer IL1. The first light emitting layer EL1 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2, and the first light emitting layer EL1 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3.

[0180] An organic material for forming the first light emitting layer EL1 and the first organic pattern ELP1 may be deposited on the entire surface of the display device 10. The first organic pattern ELP1 may include the same organic material as that of the first light emitting layer EL1, and may be disposed on the second bank BNK2. The first organic pattern ELP1 may cover the top surface and side surfaces of a portion of the second bank BNK2 around the first emission area EA1. The first light emitting layer EL1 and the first organic pattern ELP1 may be deposited by the same process, and the first light emitting layer EL1 and the first organic pattern ELP1 may be cut and separated by the tip of the second bank BNK2. Therefore, the first organic pattern ELP1 may be disposed on the second bank BNK2 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0181] A first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the first emission area EA1. The first common electrode CE1 may contact a side of the first bank BNK1. The first common electrode CE1 may include a transparent conductive material and may allow light generated by the first light emitting layer EL1 to be transmitted therethrough. Therefore, a first light emitting element ED1 may be formed in one of the holes in the bank BNK, and the first light emitting element ED1 may emit light through the first emission area EA1. The first common electrode CE1 may be directly disposed on the first light emitting layer EL1 in the second emission area EA2 and the third emission area EA3.

[0182] A metal material for forming the first common electrode CE1 and the first electrode pattern CEP1 may be deposited on the entire surface of the display device 10. The first electrode pattern CEP1 may include the same metal material as that of the first common electrode CE1, and may be disposed on the first organic pattern ELP1. The first electrode pattern CEP1 may cover the top surface and the side of the first organic pattern ELP1. The first common electrode CE1 and the first electrode pattern CEP1 may be deposited by the same process, and the first common electrode CE1 and the first electrode pattern CEP1 may be cut and separated by the tip of the second embankment BNK2. Therefore, the first electrode pattern CEP1 may be disposed on the first organic pattern ELP1 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0183] A material for forming an etching control layer ECL may be deposited on the entire surface of the display device 10. The etching control layer ECL may be disposed on the top surface of the first common electrode CE1, the side of the first bank BNK1, the bottom surface of the tip of the second bank BNK2, and the top surface and side of the first electrode pattern CEP1. The etching control layer ECL may be formed by an ALD process, but the disclosure is not limited thereto. The etching control layer ECL may be uniformly deposited on the side of the first bank BNK1 and the bottom surface of the tip of the second bank BNK2 via ALD. In an embodiment, for example, the etching control layer ECL may include at least one of IGZO, IZO, and GZO.

[0184] A capping layer CAP may be provided on the etching control layer ECL in the first emission area EA1. The capping layer CAP may include an inorganic insulating material and may cover the first light emitting element ED1. The capping layer CAP may prevent the first common electrode CE1 from being damaged by external air. In an embodiment, for example, the capping layer CAP may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto. A capping layer CAP may be provided on the etching control layer ECL in the second emission area EA2 and the third emission area EA3.

[0185] An inorganic material for forming a capping layer CAP and a first capping pattern CLP1 may be deposited on the entire surface of the display device 10. The first capping pattern CLP1 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL. The first capping pattern CLP1 may cover the side of a portion of the first electrode pattern CEP1 around the first emission area EA1. The capping layer CAP and the first capping pattern CLP1 may be deposited by the same process, and the capping layer CAP and the first capping pattern CLP1 may be cut and separated by the tip of the second bank BNK2. Therefore, the first capping pattern CLP1 may be disposed on the first electrode pattern CEP1 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0186] An inorganic material for forming the first inorganic layer TL1 may be deposited on the entire surface of the display device 10. The first inorganic layer TL1 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and the side of the first capping pattern CLP1. The first inorganic layer TL1 may include an inorganic material, and may prevent oxygen or moisture from penetrating into the first light emitting element ED1. The first inorganic layer TL1 may be an inorganic encapsulation layer. In an embodiment, for example, the first inorganic layer TL1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but the disclosure is not limited thereto.

[0187] A photoresist PR may also be disposed on the first inorganic layer TL1 in the first emission region EA1. The photoresist PR may be disposed on the first inorganic layer TL1 in regions other than the second and third emission regions EA2 and EA3, and may be used as a mask during an etching process.

[0188] Reference Fig. 9 , portions of the first inorganic layer TL1, the first capping pattern CLP1, and the capping layer CAP that are not covered by the photoresist PR may be etched by an etching process. The first inorganic layer TL1, the first capping pattern CLP1, and the capping layer CAP may be etched by an isotropic etching process. In an embodiment, for example, the first inorganic layer TL1, the first capping pattern CLP1, and the capping layer CAP may be etched by a dry etching process using an F-based etching gas.

[0189] The etching control layer ECL may be used as an etching stopper. The evaporation temperature of the etching control layer ECL for the F-based etching gas may be higher than the evaporation temperature of the first inorganic layer TL1 for the F-based etching gas. The etching control layer ECL may not be etched during the dry etching process using the F-based etching gas due to its relatively high evaporation temperature, and thus the tip of the second bank BNK2 may be prevented from being etched. Therefore, during etching of the first inorganic layer TL1, the etching control layer ECL may protect the tip of the second bank BNK2 around the second emission area EA2 and the third emission area EA3. Since the display device 10 includes the etching control layer ECL, the tip of the second bank BNK2 may be prevented from being damaged or bent.

[0190] Reference Fig.10 , the portions of the etching control layer ECL, the first electrode pattern CEP1, the first organic pattern ELP1, the first common electrode CE1, and the first light emitting layer EL1 that are not covered by the photoresist PR may be etched by an etching process. In an embodiment, for example, the etching control layer EC1, the first electrode pattern CEP1, the first organic pattern ELP1, the first common electrode CE1, and the first light emitting layer EL1 may be etched by a wet etching process, but the disclosure is not limited thereto. Therefore, the second pixel electrode AE2 may be exposed in the second emission area EA2, and the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0191] Reference Fig.11 , a second light emitting layer EL2 may be directly disposed on the second pixel electrode AE2 in the second emission area EA2. Part of the second light emitting layer EL2 may fill a space surrounded by the second pixel electrode AE2, the residual pattern RP, and the first insulating layer IL1, and another part of the second light emitting layer EL2 may cover a portion of the top surface of the first insulating layer IL1 and some of the sides of the first insulating layer IL1. A second light emitting layer EL2 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3.

[0192] An organic material for forming the second light emitting layer EL2 and the second organic pattern ELP2 may be deposited on the entire surface of the display device 10. The second organic pattern ELP2 may include the same organic material as that of the second light emitting layer EL2, and may be disposed on the second bank BNK2. The second organic pattern ELP2 may cover the top surface and the side of the second bank BNK2. The second light emitting layer EL2 and the second organic pattern ELP2 may be deposited by the same process, and the second light emitting layer EL2 and the second organic pattern ELP2 may be cut and separated by the tip of the second bank BNK2. Therefore, the second organic pattern ELP2 may be disposed on the second bank BNK2 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0193] A second common electrode CE2 may be directly disposed on the second light emitting layer EL2 in the second emission area EA2. The second common electrode CE2 may contact the side of the first bank BNK1. The second common electrode CE2 may include a transparent conductive material and may transmit light generated by the second light emitting layer EL2 through it. Therefore, a second light emitting element ED2 may be formed in one of the holes in the bank BNK, and the second light emitting element ED2 may emit light through the second emission area EA2. A second common electrode CE2 may be directly disposed on the second light emitting layer EL2 in the third emission area EA3.

[0194] A metal material for forming the second common electrode CE2 and the second electrode pattern CEP2 may be deposited on the entire surface of the display device 10. The second electrode pattern CEP2 may include the same metal material as the metal material of the second common electrode CE2, and may be disposed on the second organic pattern ELP2. The second electrode pattern CEP2 may cover the top surface and the side of the second organic pattern ELP2. The second common electrode CE2 and the second electrode pattern CEP2 may be deposited by the same process, and the second common electrode CE2 and the second electrode pattern CEP2 may be cut and separated by the tip of the second embankment BNK2. Therefore, the second electrode pattern CEP2 may be disposed on the second organic pattern ELP2 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0195] A material for forming an etching control layer ECL may be deposited on the entire surface of the display device 10. The etching control layer ECL may also be disposed on the top surface of the second common electrode CE2, the side of the first bank BNK1, the bottom surface of the tip of the second bank BNK2, and the top surface and side of the second electrode pattern CEP2. The etching control layer ECL may be formed by an ALD process, but the disclosure is not limited thereto. The etching control layer ECL may be uniformly deposited on the side of the first bank BNK1 and the bottom surface of the tip of the second bank BNK2 via ALD. In an embodiment, for example, the etching control layer ECL may include at least one of IGZO, IZO, and GZO.

[0196] A capping layer CAP may also be disposed on the etching control layer ECL in the second emission area EA2. The capping layer CAP may include an inorganic insulating material and may cover the second light emitting element ED2. The capping layer CAP may prevent the second light emitting element ED2 from being damaged by external air. A capping layer CAP may be disposed on the etching control layer ECL in the third emission area EA3.

[0197] An inorganic material for forming a capping layer CAP and a second capping pattern CLP2 may be deposited on the entire surface of the display device 10. The second capping pattern CLP2 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL. The second capping pattern CLP2 may cover the side of the second electrode pattern CEP2 around the second emission area EA2. The capping layer CAP and the second capping pattern CLP2 may be deposited by the same process, and the capping layer CAP and the second capping pattern CLP2 may be cut and separated by the tip of the second dam BNK2. Therefore, the second capping pattern CLP2 may be disposed on the second electrode pattern CEP2 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0198] An inorganic material for forming the second inorganic layer TL2 may be deposited on the entire surface of the display device 10. The second inorganic layer TL2 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and side of the second capping pattern CLP2. The second inorganic layer TL2 may include an inorganic material and may prevent oxygen or moisture from penetrating into the second light emitting element ED2. The second inorganic layer TL2 may be an inorganic encapsulation layer. In an embodiment, for example, the second inorganic layer TL2 may include one of the aforementioned exemplary materials for forming the first inorganic layer TL1 or be composed of one of the aforementioned exemplary materials for forming the first inorganic layer TL1.

[0199] A photoresist PR may also be disposed on the second inorganic layer TL2 in the second emission region EA2. The photoresist PR may be disposed on the second inorganic layer TL2 in regions other than the first and third emission regions EA1 and EA3, and may be used as a mask during an etching process.

[0200] Reference Fig.12 , portions of the second inorganic layer TL2, the second capping pattern CLP2, and the capping layer CAP that are not covered by the photoresist PR may be etched by an etching process. The second inorganic layer TL2, the second capping pattern CLP2, and the capping layer CAP may be etched by an isotropic etching process. In an embodiment, for example, the second inorganic layer TL2, the second capping pattern CLP2, and the capping layer CAP may be etched by a dry etching process using an F-based etching gas.

[0201] The etching control layer ECL may be used as an etching stopper. The evaporation temperature of the etching control layer ECL for the F-based etching gas may be higher than the evaporation temperature of the first inorganic layer TL1 for the F-based etching gas. The etching control layer ECL may not be etched during the dry etching process using the F-based etching gas due to its relatively high evaporation temperature, and thus the tip of the second bank BNK2 may be prevented from being etched. Therefore, during etching of the second inorganic layer TL2, the etching control layer ECL may protect the tip of the second bank BNK2 around the second emission area EA2 and the third emission area EA3. Since the display device 10 includes the etching control layer ECL, the tip of the second bank BNK2 may be prevented from being damaged or bent.

[0202] Reference Fig.13 , the portions of the etching control layer ECL, the second electrode pattern CEP2, the second organic pattern ELP2, the second common electrode CE2, and the second light emitting layer EL2 that are not covered by the photoresist PR may be etched by an etching process. In an embodiment, for example, the etching control layer ECL, the second electrode pattern CEP2, the second organic pattern ELP2, the second common electrode CE2, and the second light emitting layer EL2 may be etched by a wet etching process, but the disclosure is not limited thereto. Therefore, the third pixel electrode AE3 may be exposed in the third emission area EA3.

[0203] Reference Fig.14 , a third light emitting layer EL3 may be directly disposed on the third pixel electrode AE3 in the third emission area EA3. A portion of the third light emitting layer EL3 may fill a space surrounded by the third pixel electrode AE3, the residual pattern RP, and the first insulating layer IL1, and another portion of the third light emitting layer EL3 may cover a portion of the top surface of the first insulating layer IL1 and some of the side surfaces of the first insulating layer IL1.

[0204] An organic material for forming the third light emitting layer EL3 and the third organic pattern ELP3 may be deposited on the entire surface of the display device 10. The third organic pattern ELP3 may include the same organic material as that of the third light emitting layer EL3, and may be disposed on the second bank BNK2. The third organic pattern ELP3 may cover the top surface and the side of the second bank BNK2. The third light emitting layer EL3 and the third organic pattern ELP3 may be deposited by the same process, and the third light emitting layer EL3 and the third organic pattern ELP3 may be cut and separated by the tip of the second bank BNK2. Therefore, the third organic pattern ELP3 may be disposed on the second bank BNK2 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0205] A third common electrode CE3 may be disposed directly on the third light emitting layer EL3 in the third emission region EA3. The third common electrode CE3 may contact the side of the first bank BNK1. The third common electrode CE3 may include a transparent conductive material and may allow light generated by the third light emitting layer EL3 to be transmitted therethrough. Therefore, a third light emitting element ED3 may be formed in one of the holes in the bank BNK, and the third light emitting element ED3 may emit light through the third emission region EA3.

[0206] A metal material for forming the third common electrode CE3 and the third electrode pattern CEP3 may be deposited on the entire surface of the display device 10. The third electrode pattern CEP3 may include the same metal material as the metal material of the third common electrode CE3, and may be disposed on the third organic pattern ELP3. The third electrode pattern CEP3 may cover the top surface and the side of the third organic pattern ELP3. The third common electrode CE3 and the third electrode pattern CEP3 may be deposited by the same process, and the third common electrode CE3 and the third electrode pattern CEP3 may be cut and separated by the tip of the second embankment BNK2. Therefore, the third electrode pattern CEP3 may be disposed on the third organic pattern ELP3 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0207] A material for forming an etching control layer ECL may be deposited on the entire surface of the display device 10. The etching control layer ECL may also be disposed on the top surface of the third common electrode CE3, the side of the first bank BNK1, the bottom surface of the tip of the second bank BNK2, and the top surface and side of the third electrode pattern CEP3. The etching control layer ECL may be formed by an ALD process, but the disclosure is not limited thereto. The etching control layer ECL may be uniformly deposited on the side of the first bank BNK1 and the bottom surface of the tip of the second bank BNK2 via ALD. In an embodiment, for example, the etching control layer ECL may include at least one of IGZO, IZO, and GZO.

[0208] A capping layer CAP may also be disposed on the etching control layer ECL in the third emission area EA3. The capping layer CAP may include an inorganic insulating material and may cover the third light emitting element ED3. The capping layer CAP may prevent the third light emitting element ED3 from being damaged by external air.

[0209] An inorganic material for forming a capping layer CAP and a third capping pattern CLP3 may be deposited on the entire surface of the display device 10. The third capping pattern CLP3 may include the same inorganic material as that of the capping layer CAP, and may be disposed on the etching control layer ECL. The third capping pattern CLP3 may cover the side of the third electrode pattern CEP3 around the third emission area EA3. The capping layer CAP and the third capping pattern CLP3 may be deposited by the same process, and the capping layer CAP and the third capping pattern CLP3 may be cut and separated by the tip of the second bank BNK2. Therefore, the third capping pattern CLP3 may be disposed on the third electrode pattern CEP3 in an area other than the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0210] An inorganic material for forming the third inorganic layer TL3 may be deposited on the entire surface of the display device 10. The third inorganic layer TL3 may be disposed on the top surface of the capping layer CAP, the side of the etching control layer ECL, and the top surface and side of the third capping pattern CLP3. The third inorganic layer TL3 may include an inorganic material and may prevent oxygen or moisture from penetrating into the third light emitting element ED3. The third inorganic layer TL3 may be an inorganic encapsulation layer. In an embodiment, for example, the third inorganic layer TL3 may include one of the aforementioned exemplary materials for forming the first inorganic layer TL1 or be composed of one of the aforementioned exemplary materials for forming the first inorganic layer TL1.

[0211] A photoresist PR may also be disposed on the third inorganic layer TL3 in the third emission region EA3. The photoresist PR may be disposed on the third inorganic layer TL3 in regions other than the first and second emission regions EA1 and EA2, and may be used as a mask during an etching process.

[0212] Reference Fig.15 Portions of the third inorganic layer TL3 and the third capping pattern CLP3 not covered by the photoresist PR may be etched by an etching process. In an embodiment, for example, the third inorganic layer TL3 and the third capping pattern CLP3 may be etched by a dry etching process using an F-based etching gas.

[0213] Portions of the etching control layer ECL, the third electrode pattern CEP3, and the third organic pattern ELP3 not covered by the photoresist PR may be etched by an etching process. In an embodiment, for example, the etching control layer ECL, the third electrode pattern CEP3, and the third organic pattern ELP3 may be etched by a wet etching process, but the disclosure is not limited thereto.

[0214] Thereafter, the photoresist PR may be removed through a stripping process.

[0215] The etching control layer ECL can protect the tip of the second bank BNK2 during etching of the first inorganic layer TL1 and the second inorganic layer TL2. Since the display device 10 includes the etching control layer ECL, the tip of the second bank BNK2 can be prevented from being damaged or bent, and the first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 and the first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 can be uniformly formed. In addition, the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 can be uniformly formed, and the reliability of the display device 10 can be ensured.

[0216] The disclosed embodiments should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the utility model to those skilled in the art.

[0217] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, characterized in that: The display device comprises: substrate; The light-emitting element layer includes a first pixel electrode, a first light-emitting layer and a first common electrode sequentially stacked in a first emission region; a first embankment surrounding the first emission region; a second bank disposed on the first bank, the second bank including a tip protruding from a side of the first bank; and An etching control layer is disposed on a top surface of the first common electrode, on the side surfaces of the first bank, and on a bottom surface of the tip of the second bank.

2. The display device according to claim 1, characterized in that The display device further includes: A first electrode pattern is disposed on the second bank and surrounds the first emission region, the first electrode pattern including a material that is the same as that of the first common electrode.

3. The display device according to claim 2, characterized in that: The etching control layer is disposed on a top surface and a side surface of the first electrode pattern.

4. The display device according to claim 2, characterized in that: The display device further includes: a capping layer disposed on the etching control layer in the first emission region; and A first covering pattern is disposed on a portion of the etching control layer covering the first electrode pattern, and the first covering pattern includes a material that is the same as that of the covering layer.

5. The display device according to claim 4, characterized in that: The display device further includes a first inorganic layer disposed in the first emission region, on a top surface of the capping layer, on a side of the etching control layer, and on a top surface and a side of the first capping pattern.

6. The display device according to claim 1, characterized in that: The light emitting element layer further includes a second pixel electrode, a second light emitting layer, and a second common electrode which are sequentially stacked in the second emission region.

7. The display device according to claim 6, characterized in that: The first embankment surrounds the second emission region, The second bank is disposed on the first bank, and The etching control layer is disposed on a top surface of the second common electrode, on a side of a portion of the first bank surrounding the second emission region, and on a bottom surface of the tip of the second bank around the second emission region.

8. The display device according to claim 6, characterized in that: The display device further includes: A second electrode pattern is disposed on the second bank and surrounds the second emission region, the second electrode pattern including the same material as that of the second common electrode.

9. The display device according to claim 8, characterized in that: The etching control layer is disposed on a top surface and a side surface of the second electrode pattern.

10. The display device according to claim 8, further comprising: a capping layer disposed on the etching control layer in the second emission region; as well as A second covering pattern is disposed on a portion of the etching control layer covering the second electrode pattern, and the second covering pattern includes a material that is the same as that of the covering layer.

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