Memory circuit

Abstract

The memory circuit includes a first memory cell, a first buffer, a first logic circuit, and a first switching circuit. The first memory cell may be configured to pre-charge in response to receiving a primary sleep signal. The first buffer may be configured to receive the primary sleep signal, generate a delayed primary sleep signal, and provide the delayed primary sleep signal to the second memory cell. The first logic circuit may be configured to generate a first bit column pre-charge signal for a first memory cell of the plurality of memory cells corresponding to a cyclic sleep signal, wherein the cyclic sleep signal is generated based on the delayed main sleep signal. The first switching circuit may be configured to provide power to at least one bit column of the first memory cell corresponding to the first bit column pre-charge signal.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory system, and more particularly to a power management system and method for the semiconductor memory system. Background Art

[0002] The memory device can be configured to operate in multiple states. For example, for energy conservation purposes, the memory device can be configured to operate in an active state and a lower power state (such as off, deep sleep, and shallow sleep). Circuits can be used in the memory device to facilitate transitions between available states. Utility Model Content

[0003] An embodiment of the present disclosure provides a memory circuit, comprising: a first memory unit, configured to be precharged in response to receiving a main sleep signal; a first buffer, configured to receive the main sleep signal and generate a delayed main sleep signal; a first logic circuit, configured to generate a first bit line precharge signal for the first memory unit in response to a cyclic sleep signal, wherein the cyclic sleep signal is generated based on the delayed main sleep signal; and a first switching circuit, configured to provide power to at least one bit line of the first memory unit in response to the first bit line precharge signal.

[0004] In some embodiments, the memory circuit further comprises: a delay circuit, receiving the delayed main sleep signal and generating the cyclic sleep signal, wherein the delay circuit is configured to delay the cyclic sleep signal until the first memory unit is fully precharged before providing it to the first logic circuit.

[0005] In some embodiments, the memory circuit further includes: a second memory unit configured to be precharged in response to receiving the delayed master sleep signal; and a second buffer configured to receive the delayed master sleep signal, generate a cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

[0006] In some embodiments, the memory circuit further includes: a second memory unit, configured to be precharged in response to receiving the delayed master sleep signal; a second buffer, configured to receive the delayed master sleep signal, generate a second delayed master sleep signal and provide the second delayed master sleep signal to a third memory unit; wherein the third memory unit is configured to be precharged in response to receiving the second delayed master sleep signal; and a third buffer, configured to receive the second delayed master sleep signal, generate the cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

[0007] In some embodiments, the third buffer is configured to provide the cyclic sleep signal to a fourth memory unit, and the fourth memory unit is configured to be precharged in response to receiving the cyclic sleep signal.

[0008] In some embodiments, the third buffer is configured to delay providing the cycle sleep signal to the first logic circuit until after the third memory cell is fully precharged.

[0009] In some embodiments, the memory circuit further includes: a first latch circuit receiving the cyclic sleep signal and the first bit line precharge signal and generating a delayed cyclic sleep signal.

[0010] In some embodiments, the memory circuit further includes: a second logic circuit configured to generate a second bit line precharge signal for a second memory cell among the plurality of memory cells, and the second logic circuit is configured to generate the second bit line precharge signal in response to the delay cycle sleep signal; and a second switching circuit configured to provide power to at least one bit line of the second memory cell in response to the second bit line precharge signal.

[0011] In some embodiments, the memory circuit further includes: a second latch circuit, which receives the delayed sleep signal and the second bit line precharge signal and generates a second delayed sleep signal; a third logic circuit, which is configured to generate a third bit line precharge signal for a third memory cell among the multiple memory cells, and the third logic circuit is configured to generate the third bit line precharge signal in response to the second delayed sleep signal; and a third switching circuit, which is configured to provide power to at least one bit line of the third memory cell in response to the third bit line precharge signal; wherein the second latch circuit causes a logic state transition in the second delayed sleep signal to occur after power is provided to at least one bit line of the second memory cell.

[0012] In some embodiments, the memory circuit further includes: a third latch circuit, which receives the second delayed sleep signal and the third bit line precharge signal and generates a third delayed sleep signal; a fourth logic circuit, which is configured to generate a fourth bit line precharge signal for a fourth memory cell among the multiple memory cells, and the fourth logic circuit is configured to generate the fourth bit line precharge signal in response to the third delayed sleep signal; and a fourth switching circuit, which is configured to provide power to at least one bit line of the fourth memory cell in response to the fourth bit line precharge signal; wherein the third latch circuit causes a logic state transition in the third delayed sleep signal to occur after power is provided to at least one bit line of the third memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention is fully disclosed according to the following detailed description and the accompanying drawings.

[0014] Figure 1 is a diagram of an exemplary sleep cycle architecture in accordance with various embodiments of the present disclosure, the architecture being within a power management circuit of a semiconductor memory (eg, static random access memory (SRAM)).

[0015] Figure 2 is a diagram of a power management circuit for an example semiconductor memory (eg, SRAM) consistent with various embodiments of the present disclosure.

[0016] Figure 3 is a timing diagram consistent with various embodiments of the present disclosure, showing Figure 2 An example operation of the power management circuit in FIG.

[0017] Figure 4 is a diagram of another example semiconductor memory (eg, SRAM) power management circuit consistent with various embodiments of the present disclosure.

[0018] Figure 5 is a timing diagram consistent with various embodiments of the present disclosure, showing Figure 4 An example operation of the power management circuit in FIG.

[0019] Figure 6 is a diagram of an example memory array consistent with various embodiments of the present disclosure, which array may be used to Figure 1 , Figure 2 and Figure 4 In the power management circuit.

[0020] Figure 7 An example of an SR latch consistent with one embodiment is shown. The latch can be used as Figure 4 at least one latch circuit.

[0021] Figure 8 is a flow chart of an example method for controlling a memory array wake-up operation in accordance with various embodiments of the present disclosure.

[0022] Fig. 9 is a flow chart of another exemplary method for controlling a memory array wake-up operation consistent with various embodiments of the present disclosure.

[0023] The reference numerals are described as follows:

[0024] 104: Local Input / Output System

[0025] 106: Global I / O System

[0026] 108: Logic Circuits

[0027] 109: Sleep signal

[0028] 110: Clock generator and address decoder

[0029] 115, CLK: global clock signal

[0030] 117, CEB: chip enable signal

[0031] 113: Address character

[0032] 119, SLP_BOT_LEFT: sleep signal

[0033] 121, BL_BOT_LEFT: bit line

[0034] 123, BPCHB_BOT_LEFT: bit line precharge signal

[0035] 125, BLB_BOT_LEFT: complementary bit line

[0036] 127, VDDAI_BOT_LEFT: array power wake-up signal

[0037] 129, SLP_BOT_RIGHT: first delayed sleep signal

[0038] 131, BPCHB_BOT_RIGHT: bit line precharge signal

[0039] 133, BL_BOT_RIGHT: bit line

[0040] 135, BLB_BOT_RIGHT: complementary bit line

[0041] 137, VDDAI_BOT_RIGHT: array power wake-up signal

[0042] 139, SLP_TOP_LEFT: Second delayed sleep signal

[0043] 141, BPCHB_TOP_LEFT: bit line precharge signal

[0044] 143, BL_TOP_LEFT: bit line

[0045] 145, BLB_TOP_LEFT: complementary bit line

[0046] 147, VDDAI_TOP_LEFT: array power wake-up signal

[0047] 149, SLP_TOP_RIGHT: The third delayed sleep signal

[0048] 151, BPCHB_TOP_RIGHT: bit line precharge signal

[0049] 153, BL_TOP_RIGHT: bit line

[0050] 155, BLB_TOP_RIGHT: complementary bit line

[0051] 157, VDDAI_TOP_RIGHT: array power wake-up signal

[0052] 319, SLP_BOT_LEFT: master sleep signal

[0053] 321, BL_BOT_LEFT: bit line

[0054] 323, BPCHB_BOT_LEFT: first bit line precharge signal

[0055] 325, BLB_BOT_LEFT: complementary bit line

[0056] 329, SLP_BOT_RIGHT: Delay master sleep signal

[0057] 331, BPCHB_BOT_RIGHT: Second bit line precharge signal

[0058] 333, BL_BOT_RIGHT: bit line

[0059] 335, BLB_BOT_RIGHT: complementary bit line

[0060] 339, SLP_TOP_LEFT: Second delayed master sleep signal

[0061] 341, BPCHB_TOP_LEFT: third bit line precharge signal

[0062] 343, BL_TOP_LEFT: bit line

[0063] 344: Third buffer

[0064] 345, BLB_TOP_LEFT: complementary bit line

[0065] 351, BPCHB_TOP_RIGHT: The fourth bit line precharge signal

[0066] 353, BL_TOP_RIGHT: bit line

[0067] 355, BLB_TOP_RIGHT: complementary bit line

[0068] 361, SLP_1_BOT_LEFT, SLP_1, SLP_2: Cyclic sleep signal

[0069] 362, SLP_1_BOT_RIGHT: Delay loop sleep signal

[0070] 363, SLP_1_TOP_LEFT: Second delay cycle sleep signal

[0071] 364, SLP_1_TOP_RIGHT: The third delay cycle sleep signal

[0072] 371: First latch circuit

[0073] 372: Second latch circuit

[0074] 373: Third latch circuit

[0075] 410: Arrow

[0076] 10, 100, 300: Power management circuit

[0077] 102,500: Memory array

[0078] 112, 312: first (lower left corner) memory cell

[0079] 114, 314: Second (lower right) memory cell

[0080] 116, 316: third (upper left) memory cell

[0081] 118, 318: Fourth (upper right) memory cell

[0082] 124, 324: First buffer

[0083] 134, 334: Second buffer

[0084] 200, 400: Timing diagram

[0085] 320, 322: First logic circuit

[0086] 800, 900: Method

[0087] 902, 904, 906: Operation

[0088] 120, 130, 140, 150: first logic gate (logic circuit)

[0089] 122, 132, 142, 152: Second logic gate (logic circuit)

[0090] 12, 14, 16, 18: memory cells

[0091] 126, 128, 136, 138, 146, 148, 156, 158: P-type metal oxide semiconductor (PMOS) transistors

[0092] 201, 203, 205, ..., 225: conversion

[0093] 230: wake-up current consumption

[0094] 330, 332: Second logic circuit

[0095] 340, 342: Third logic circuit

[0096] 350, 352: Fourth logic circuit

[0097] 401, 403, 405, ..., 425: Conversion

[0098] 802, 804, 806, ..., 812: Operation

[0099] BPCHB: Bit line precharge signal

[0100] ICLK: clock signal

[0101] SLP: Sleep signal

[0102] TOP, BOT: address signal

[0103] ADR[N:0]:Address input DETAILED DESCRIPTION

[0104] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present disclosure describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, different examples in the following disclosure may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0105] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to facilitate description of the relationship between one element or feature and another element or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0106] As described above, memory devices can be configured to operate in a variety of different power states. Power gates can be used to shut down the periphery and memory array of low-power memory devices (such as SRAM). When the memory exits from a sleep mode (such as shutdown (SD), deep sleep, and shallow sleep), a large power gate can be used to increase the internal supply voltage of the memory. In the design, providing a short wake-up time for the internal supply voltage may result in a large in-rush current. There may be a design trade-off between the in-rush current (such as the wake-up peak current) and the memory wake-up time.

[0107] The power state of a memory can be structured in a variety of ways. For example, in shallow sleep mode, the internal power supply of the word line and the bit line pre-charge circuit of the memory system can be turned off. Memory design guidelines may require keeping the wake-up peak current less than the task mode (Read / Write (R / W) operation) peak current, especially in shallow sleep mode. Some memory systems may not be able to meet this criterion during shallow sleep wakeup because the array power wakeup occurs almost simultaneously with the pre-charge of the bit lines within the memory bank.

[0108] Systems and methods for power management in memory systems are described herein. In certain embodiments, a second sleep cycle is added to a semiconductor memory system (e.g., SRAM) to implement a sequential memory array power precharge operation and a separate sequential bit line precharge operation when exiting a power management mode (e.g., shutdown, deep sleep, and shallow sleep). In this manner, by separating the memory array power on and bit line precharge operations, the wake-up peak current within the memory bank can be reduced compared to existing SRAM architectures. In certain embodiments, the change in required current based on this design change can be reduced by up to 42%.

[0109] The memory device can be implemented by activating / transmitting commands (e.g., word line activation command, column read command, word line / bit line precharge command, sense amplifier precharge command, sense amplifier enable command, read driver command, write driver command), which are usually implemented by multiple memory arrays (e.g., left and right arrays of a memory group, four memory arrays of a memory group). Each memory array includes multiple memory cells, usually arranged in rows and columns.

[0110] Figure 1 FIG. 1 is a diagram of an exemplary power management circuit 10 for operation of a semiconductor memory (e.g., SRAM) with a sleep cycle in accordance with an embodiment. The power management circuit 10 may be composed of many electrical components, including memory cells 12, 14, 16, 18 configured to store information in the form of "0" or "1" as shown, and many other components, such as Figure 2 Those components described in more detail in . The process of storing information in the memory cells 12, 14, 16, 18 is called "writing". The process of reading the information stored on the memory cells 12, 14, 16, 18 is called "reading". Reading and writing are exemplary functions of memory devices. In order to perform these functions, certain electrical components that make up the memory device need to be powered and need to be turned on. However, not all electrical components need to be powered during these functions and can be temporarily turned off (for example, put into sleep mode). The process of starting or shutting down certain electrical components within the memory device is called power management. Power management in the power management circuit 10 is performed using multiple power management signals sent to the electrical components to tell them whether to start or shut down. When the electrical components undergoing the wake-up process have overlapping time frames, large wake-up peak current requirements may result.

[0111] like Figure 1 As shown, the power management circuit 10 can be configured to receive a number of inputs, including a clock input (CLK), a chip enable input (CEB), an address input (ADR[N:0]), and a sleep input signal. The sleep signal includes a main sleep signal path (solid line) for sequentially precharging the memory cells, from the lower left memory cell 12 to the upper right memory cell 18. In addition, a cyclic sleep signal path (dashed line) can be used to sequentially precharge the bit line of each memory cell after each memory cell is precharged via the main sleep path. By using such a cyclic second sleep signal path, the wake-up peak current within the memory group can be reduced because the various bit line precharge and memory array power precharge operations do not occur in substantially overlapping time frames.

[0112] Figure 2 FIG. 1 is a diagram of an exemplary power management circuit 100 for operating a semiconductor memory (e.g., SRAM) without a sleep cycle (loop) in accordance with an embodiment. The exemplary power management circuit 100 includes a memory array 102 having a plurality of memory cells, which is controlled by a local input / output (I / O) system 104 and a global I / O system 106. The global I / O system 106 includes: a logic circuit 108, which generates a sleep signal 119 from an input sleep signal 109; and a clock generator and address decoder 110, which generates a clock signal (ICLK) and an address signal (TOP, BOT) for selecting a memory cell in the memory array 102 for a read or write operation. The clock generator and address decoder 110 generates a clock signal (ICLK) as a function of a global clock signal 115 (CLK) and a chip enable signal 117 (CEB), and generates address signals (TOP, BOT) as a function of an address word 113 (ADR[N:0]) and the chip enable signal 117 (CEB).

[0113] The local I / O system 104 includes logic circuits for each memory cell in the memory array 102, which generates a bit line precharge (BPCHB) signal for controlling the power of the bit line of each memory cell as a function of the sleep signal (SLP), the clock signal (ICLK), and the address signal (TOP, BOT) signal. The local I / O system 104 also includes a plurality of buffers so that the plurality of memory cells in the memory array 102 receive power in sequence.

[0114] exist Figure 2 , the memory array 102 includes a first (lower left corner) memory cell 112, a second (lower right corner) memory cell 114, a third (upper left corner) memory cell 116, and a fourth (upper right corner) memory cell 118. As shown, the sleep signal (SLP) from the global I / O system 106 is received in the local I / O system 104 as a sleep signal 119 (SLP_BOT_LEFT) of the lower left corner memory cell 112.

[0115] The sleep signal 119 is input to the memory cell 112 to precharge the array power of the memory. Specifically, the array power wake-up signal 127 (VDDAI_BOT_LEFT) is used to precharge the memory array. After the array power wake-up is initiated (initiation) in the first memory cell 112, the sleep signal 119 (SLP_BOT_LEFT) is input to the logic circuit 120, 122 of the lower left memory cell 112 together with the clock signal (ICLK) and the address (TOP, BOT) signal. More specifically, the logic circuit of the lower left memory cell 112 includes: a first logic (AND) gate 120, which has an input terminal, which receives the address (TOP, BOT) signal; and a second logic (OR) gate 122, which has an input terminal, which receives the output of the first logic gate 120 and the sleep signal 119 (SLP_BOT_LEFT). The output of the second logic (OR) gate 122 provides a bit line precharge signal 123 (BPCHB_BOT_LEFT) for the switching circuit in the lower left memory cell 112. Specifically, the bit line precharge signal 123 (BPCHB_BOT_LEFT) is received at the gate terminals of a pair of P-type metal oxide semiconductor (PMOS) transistors 126 and 128, the source terminals of which are coupled to the supply voltage; and the drain terminals of which are respectively coupled to the bit line 121 (BL_BOT_LEFT) and the complementary bit line (bitlinebar) 125 (BLB_BOT_LEFT) input terminals of the lower left memory cell 112.

[0116] In response to a transition of the sleep signal 119 (SLP_BOT_LEFT) indicating a memory wake-up operation, the logic circuits 120 and 122 of the lower left memory cell 112 generate a logic state on the bit line precharge signal 123 (BPCHB_BOT_LEFT) to supply power to the bit line 121 (BL_BOT_LEFT) and the complementary bit line 125 (BLB_BOT_LEFT) of the precharged memory cell. More specifically, the PMOS transistors 126 and 128 are controlled by the bit line precharge signal 123 (BPCHB_BOT_LEFT) to provide power to the bit line 121 (BL_BOT_LEFT) and the complementary bit line 125 (BLB_BOT_LEFT) of the memory cell 112 to initialize the bit line voltage to power on the memory array 102 in the corresponding memory wake-up operation (VDDAI_BOT_LEFT). Figure 3 This operation is illustrated in timing diagram 200 shown in FIG.

[0117] refer to Figure 3 As one embodiment, the wake-up operation is initiated by a transition 201 from logic high to logic low of the sleep signal 109 received by the global I / O system 106. The transition 201 of the logic state of the sleep signal 109 causes a corresponding transition 203 of the logic state of the sleep signal 119 (SLP_BOT_LEFT) received by the local I / O system 104. Figure 2 As described in detail, the transition 203 of the logic state in the sleep signal 119 (SLP_BOT_LEFT) causes the precharging of the bottom left memory cell 112 and the precharging of the logic circuits 120, 122 of the bottom left memory cell 112 to transition 205 the logic state of the bit line precharge signal 123 (BPCHB_BOT_LEFT), thereby causing the power supply to precharge the memory cell bit line 121 (BL_BOT_LEFT), the complementary bit line 125 (BLB_BOT_LEFT). Figure 3 The pre-charging of the memory cell bit line 121 (BL_BOT_LEFT), the complementary bit line 125 (BLB_BOT_LEFT) can be seen by the voltage transition 207 occurring in the timing diagram 200, which is a response to the transition 205 of the logic state of the bit line pre-charge signal 123 (BPCHB_BOT_LEFT).

[0118] Reference again Figure 2 The sleep signal 119 (SLP_BOT_LEFT) is also received as an input by the first buffer 124. The first buffer 124 generates a first delayed sleep signal 129 (SLP_BOT_RIGHT) in response to the sleep signal 119 (SLP_BOT_LEFT). Figure 3 In the timing diagram 200 shown, after the bit line precharge signal 123 (BPCHB_BOT_LEFT) begins to transition from logic high to logic low, the first delayed sleep signal 129 (SLP_BOT_RIGHT) begins to transition 209 in logic state. Therefore, the buffer can generate a time delay between precharging the voltage of the bit line 121 (BL_BOT_LEFT) of the bottom left corner memory cell 112, the complementary bit line 125 (BLB_BOT_LEFT), and initiating the wake-up operation of the bottom right corner memory cell 114.

[0119] Reference again Figure 2, the first delayed sleep signal 129 is input to the bottom right memory cell 114 to precharge the array power of the memory. Specifically, the bottom right memory cell 114 is precharged using the array power wake-up signal 137 (VDDAI_BOT_RIGHT). After the array power wake-up is initiated in the bottom right memory cell 114, the first delayed sleep signal 129 (SLP_BOT_RIGHT) is also provided to the logic circuits 130, 132 of the bottom right memory cell 114 as a sleep signal input, and also as an input to the second buffer 134. The logic circuit of the bottom right memory cell 114 includes: a first logic (AND) gate 130 having an input terminal, which receives the address (TOP, BOT) signal; and a second logic (OR) gate 132 having an input terminal, which receives the output of the first logic gate 130 and the first delayed sleep signal 129 (SLP_BOT_RIGHT). The output of the second logic (OR) gate 132 provides a bit line precharge signal 131 (BPCHB_BOT_RIGHT) for the switching circuit in the bottom right memory cell 114. Specifically, the bit line precharge signal 131 (BPCHB_BOT_RIGHT) is received at the gate terminals of a pair of PMOS transistors 136 and 138, the source terminals of the pair of transistors are coupled to the supply voltage, and the drain terminals of the pair of transistors are respectively coupled to the bit line 133 (BL_BOT_RIGHT) and the complementary bit line 135 (BLB_BOT_RIGHT) input terminals of the bottom right memory cell 114.

[0120] In response to a transition of the first delayed sleep signal 129 (SLP_BOT_RIGHT) indicating a memory wake-up operation, the logic circuits 130, 132 of the lower right memory cell 114 generate a logic state on the bit line precharge signal 131 (BPCHB_BOT_RIGHT), causing the PMOS transistors 136, 138 to provide power to precharge the memory cell bit line 133 (BL_BOT_RIGHT) and the complementary bit line 135 (BLB_BOT_RIGHT). Figure 3 In the timing diagram shown, the transition 209 of the logic state of the first delayed sleep signal 129 (SLP_BOT_RIGHT) causes the logic circuits 130, 132 of the lower right memory cell 114 to transition 211 the logic state of the bit line precharge signal 131 (BPCHB_BOT_RIGHT), thereby causing the power supply to precharge the memory cell bit line 133 (BL_BOT_RIGHT) and the complementary bit line 135 (BLB_BOT_RIGHT). Figure 3The pre-charging of the memory cell bit line 133 (BL_BOT_RIGHT) and the complementary bit line 135 (BLB_BOT_RIGHT) can be seen from the voltage transition 213 occurring in the timing diagram 200, which is a response to the transition 211 of the logic state of the bit line pre-charge signal 131 (BPCHB_BOT_RIGHT).

[0121] Reference again Figure 2 The first delayed sleep signal 129 (SLP_BOT_RIGHT) is also received as input by the second buffer 134, which generates a second delayed sleep signal 139. Figure 3 In the timing diagram 200 shown, after the bit line precharge signal 131 (BPCHB_BOT_RIGHT) starts to transition from logic high to logic low, the second delayed sleep signal 139 (SLP_TOP_LEFT) also starts to transition from a high to a low logic state 215. Therefore, the buffer can generate a time delay between the voltage precharge of the bit line 133 (BL_BOT_RIGHT) of the bottom right memory cell 114, the complementary bit line 135 (BLB_BOT_RIGHT), and the start of the wake-up operation of the top left memory cell 116.

[0122] Reference again Figure 2, the second delayed sleep signal 139 is input to the upper left memory cell 116 to precharge the array power of the memory. Specifically, the upper left memory cell 116 is precharged using the array power wake-up signal 147 (VDDAI_TOP_LEFT). After the array power wake-up is initiated in the upper left memory cell 116, the second delayed sleep signal 139 (SLP_TOP_LEFT) is also provided to the logic circuit 140, 142 of the upper left memory cell 116 as a sleep signal input, and also as an input to the third buffer 144. The logic circuit of the upper left memory cell 116 includes: a first logic (AND) gate 140, having an input terminal, which receives the address (TOP, BOT) signal; and a second logic (OR) gate 142, having an input terminal, which receives the output of the first logic gate 140 and the second delayed sleep signal 139 (SLP_TOP_LEFT). The output of the second logic (OR) gate 142 provides a bit line precharge signal 141 (BPCHB_TOP_LEFT) for the switching circuit in the top left memory cell 116. Specifically, the bit line precharge signal 141 (BPCHB_TOP_LEFT) is received at the gate terminals of a pair of PMOS transistors 146 and 148, the source terminals of the pair of transistors are coupled to the supply voltage, and the drain terminals of the pair of transistors are respectively coupled to the bit line 143 (BL_TOP_LEFT) and the complementary bit line 145 (BLB_TOP_LEFT) input terminals of the top left memory cell 116.

[0123] In response to a transition of the second delayed sleep signal 139 (SLP_TOP_LEFT) indicating a memory wake-up operation, the logic circuits 140, 142 of the upper left memory cell 116 generate a logic state on the bit line precharge signal 141 (BPCHB_TOP_LEFT), causing the PMOS transistors 146, 148 to provide power to precharge the memory cell bit line 143 (BL_TOP_LEFT) and the complementary bit line 145 (BLB_TOP_LEFT). Figure 3 In the timing diagram shown, the transition 215 of the logic state of the second delayed sleep signal 139 (SLP_TOP_LEFT) causes the logic circuits 140, 142 of the upper left memory cell 116 to transition 217 the logic state of the bit line precharge signal 141 (BPCHB_TOP_LEFT), thereby causing the power supply to precharge the memory cell bit line 143 (BL_TOP_LEFT) and the complementary bit line 145 (BLB_TOP_LEFT). Figure 3The pre-charging of the memory cell bit line 143 (BL_TOP_LEFT) and the complementary bit line 145 (BLB_TOP_LEFT) can be seen by the voltage transition 219 occurring in the timing diagram 200, which is a response to the transition 217 of the logic state of the bit line pre-charge signal 141 (BPCHB_TOP_LEFT).

[0124] Reference again Figure 2 The second delayed sleep signal 139 (SLP_TOP_LEFT) is also received as input by the third buffer 144, which generates a third delayed sleep signal 149 (SLP_TOP_RIGHT). Figure 3 In the timing diagram 200 shown, after the bit line precharge signal 141 (BPCHB_TOP_LEFT) starts to transition from logic high to logic low, the third delayed sleep signal 149 (SLP_TOP_RIGHT) also starts to transition from a high to a low logic state 221. Therefore, the buffer can generate a time delay between the voltage precharge of the bit line 143 (BL_TOP_LEFT) of the top left memory cell 116, the complementary bit line 145 (BLB_TOP_LEFT), and the start of the wake-up operation of the top right memory cell 118.

[0125] Reference again Figure 2 , the third delayed sleep signal 149 (SLP_TOP_RIGHT) is provided to the logic circuits 150, 152 of the upper right memory unit 118 as sleep signal inputs. The logic circuit of the upper right memory unit 118 includes: a first logic (AND) gate 150 having an input terminal, which receives the address (TOP, BOT) signal; and a second logic (OR) gate 152 having an input terminal, which receives the output terminal of the first logic gate 150 and the third delayed sleep signal 149 (SLP_TOP_RIGHT). The output terminal of the second logic (OR) gate 152 provides a bit line precharge signal 151 (BPCHB_TOP_RIGHT) for the switching circuit in the upper right memory unit 118. Specifically, the bit line precharge signal 151 (BPCHB_TOP_RIGHT) is received at the gate terminals of a pair of PMOS transistors 156 and 158, the source terminals of the pair of transistors are coupled to the supply voltage, and the drain terminals of the pair of transistors are respectively coupled to the bit line 153 (BL_TOP_RIGHT) and complementary bit line 155 (BLB_TOP_RIGHT) input terminals of the upper right memory cell 118.

[0126] In response to a transition of the third delayed sleep signal 149 (SLP_TOP_RIGHT) indicating a memory wake-up operation, the logic circuits 150, 152 of the top right memory cell 118 generate a logic state on the bit line precharge signal 151 (BPCHB_TOP_RIGHT) to enable the PMOS transistors 156, 158 to provide power to precharge the memory cell bit line 153 (BL_TOP_RIGHT) and the complementary bit line 155 (BLB_TOP_RIGHT). Figure 3 In the timing diagram shown, the transition 221 of the logic state of the third delayed sleep signal 149 (SLP_TOP_RIGHT) causes the logic circuits 150, 152 of the upper right memory cell 118 to transition 223 the logic state of the bit line precharge signal 151 (BPCHB_TOP_RIGHT), thereby causing the power supply to precharge the memory cell bit line 153 (BL_TOP_RIGHT) and the complementary bit line 155 (BLB_TOP_RIGHT). Figure 3 The pre-charging of the memory cell bit line 153 (BL_TOP_RIGHT) and the complementary bit line 155 (BLB_TOP_RIGHT) can be seen from the voltage transition 225 occurring in the timing diagram 200, which is a response to the transition 223 of the logic state of the bit line pre-charge signal 151 (BPCHB_TOP_RIGHT).

[0127] In this way, the bit lines of the four memory cells in the power management circuit 100 of the exemplary embodiment, namely the first memory cell 112, the second memory cell 114, the third memory cell 116, and the fourth memory cell 118, are precharged. Figure 3 The example timing diagram 200 shown in FIG. Figure 3 It is further shown that the array power wake-up and bit line pre-charging occurring nearly simultaneously may result in a significant peak in the wake-up current draw 230. Pre-charging the bit lines in sequence may help mitigate the wake-up current draw as described in U.S. Patent Application Publication 2022 / 0068327 filed on January 4, 2022, the entire contents of which are incorporated herein by reference. However, due to the overlap of array power wake-up and bit line pre-charging, staged bit line pre-charging may not be sufficient to reduce the wake-up current draw 230 below a desired level.

[0128] Figure 4 is another example of a power management circuit 300 for a semiconductor memory (eg, SRAM). Figure 2Unlike the system provided in , the power management circuit 300 utilizes an improved sleep cycle architecture that allows separation of array power wakeup and bit line precharging and still benefits from the advantages of sequential wakeup and precharging. In other words, by separating the process of precharging array power from the process of precharging bit lines, effectively creating eight unique, sequential current draws, the peak wakeup current draw can be further reduced. To achieve this separation, at least one sleep signal cycle can be added to the power management circuit.

[0129] Figure 4 The power management circuit 300 of an example according to an embodiment includes many Figure 2 , including a first (lower left corner) memory cell 312, a second (lower right corner) memory cell 314, a third (upper left corner) memory cell 316, and a fourth (upper right corner) memory cell 318. However, Figure 2 Different from the exemplary power management circuit 100 shown in the figure, the exemplary power management circuit 300 includes: a main sleep signal path (including a main sleep signal SLP_BOT_LEFT, a delayed main sleep signal SLP_BOT_RIGHT, and a second delayed main sleep signal SLP_TOP_LEFT), configured to precharge the array power of the memory; and a cyclic sleep signal path (including a cyclic sleep signal SLP_1_BOT_LEFT, a delayed cyclic sleep signal SLP_1_BOT_RIGHT, a second delayed cyclic sleep signal SLP_1_TOP_LEFT, and a third delayed cyclic sleep signal SLP_1_TOP_RIGHT), configured to precharge the bit lines in sequence.

[0130] In the illustrated embodiment, the master sleep signal 319 is input to the bottom left memory cell 312 to precharge the memory array power. Specifically, the master sleep signal 319 (SLP_BOT_LEFT) is used to precharge the bottom left memory cell 312. However, unlike Figure 2Unlike the example power management circuit 100 shown in FIG. 1 , the sleep signal 319 (SLP_BOT_LEFT) is not input into the first logic circuits 320 and 322. Instead, the master sleep signal 319 (SLP_BOT_LEFT) is received as an input by the first buffer 324, which generates a delayed master sleep signal 329 (SLP_BOT_RIGHT) in response to the master sleep signal 319 (SLP_BOT_LEFT). The delayed master sleep signal 329 (SLP_BOT_RIGHT) is then provided to the second memory unit 314, which is configured to be precharged in response to receiving the delayed master sleep signal 329 (SLP_BOT_RIGHT). The second buffer 334 receives the delayed master sleep signal 329 (SLP_BOT_RIGHT), generates a second delayed master sleep signal 339 (SLP_TOP_LEFT), and provides the second delayed master sleep signal 339 (SLP_TOP_LEFT) to the third memory unit 316. The third memory cell 316 is precharged in response to receiving the second delayed master sleep signal 339 (SLP_TOP_LEFT). Subsequently, the third buffer 344 receives the second delayed master sleep signal 339 (SLP_TOP_LEFT) and generates a cyclic sleep signal 361 (SLP_1_BOT_LEFT). The fourth memory cell 318 is then precharged in response to receiving the cyclic sleep signal 361 (SLP_1_BOT_LEFT). Due to this master sleep path, all four memory cells can be precharged in sequence before the bit line precharge occurs.

[0131] like Figure 5 In the timing diagram 400 shown, as an embodiment, the memory cell wake-up operation is initiated by a logic high to logic low transition 401 of the master sleep signal 319 (SLP_BOT_LEFT), which results in a transition 403 of the logic state in the master sleep signal 319 (SLP_BOT_LEFT) and causes precharging of the memory cell 312. Subsequently, the transitions 405, 407, 409 of the logic states occurring sequentially in the delayed master sleep signal 329 (SLP_BOT_RIGHT), the second delayed master sleep signal 339 (SLP_TOP_LEFT), and the cyclic sleep signal 361 (SLP_1_BOT_LEFT) result in precharging of the second memory cell 314, the third memory cell 316, and the fourth memory cell 318, respectively.

[0132] Reference again Figure 4 After the cyclic sleep signal 361 (SLP_1_BOT_LEFT) is generated, it is provided to the first logic circuits 320 and 322 and serves as the input of the first latch circuit 371. Figure 2Similar to the example in FIG. 1 , the first logic circuit 320, 322 of the lower left memory cell 312 generates a logic state on the first bit line precharge signal 323 (BPCHB_BOT_LEFT), so that the power supply precharges the memory cell bit line 321 (BL_BOT_LEFT) and the complementary bit line 325 (BLB_BOT_LEFT). The first bit line precharge signal 323 (BPCHB_BOT_LEFT) and the cyclic sleep signal 361 (SLP_1_BOT_LEFT) are then input into the first latch circuit 371 together with the cyclic sleep signal 361 (SLP_1_BOT_LEFT), which generates the delayed cyclic sleep signal 362 (SLP_1_BOT_RIGHT).

[0133] The delayed cycle sleep signal 362 (SLP_1_BOT_RIGHT) is then provided to the second logic circuits 330, 332 and as an input to the second latch circuit 372. Figure 2 Similar to the example in FIG. 1 , the second logic circuits 330 and 332 of the bottom right memory cell 314 generate a logic state on the second bit line precharge signal 331 (BPCHB_BOT_RIGHT), so that the power supply precharges the memory cell bit line 333 (BL_BOT_RIGHT) and the complementary bit line 335 (BLB_BOT_RIGHT). The second bit line precharge signal 331 (BPCHB_BOT_RIGHT) and the delay cycle sleep signal 362 (SLP_1_BOT_RIGHT) are then input into the second latch circuit 372 together with the delay cycle sleep signal 362 (SLP_1_BOT_RIGHT), which generates the second delay cycle sleep signal 363 (SLP_1_TOP_LEFT).

[0134] The second delay cycle sleep signal 363 (SLP_1_TOP_LEFT) is then provided to the third logic circuits 340, 342 and as an input to the third latch circuit 373. Figure 2 Similar to the example in FIG. 1 , the third logic circuits 340 and 342 of the top left memory cell 316 generate a logic state on the third bit line precharge signal 341 (BPCHB_TOP_LEFT), so that the power supply precharges the memory cell bit line 343 (BL_TOP_LEFT) and the complementary bit line 345 (BLB_TOP_LEFT). The third bit line precharge signal 341 (BPCHB_TOP_LEFT) is then input together with the second delay cycle sleep signal 363 (SLP_1_TOP_LEFT) into the third latch circuit 373, which generates the third delay cycle sleep signal 364 (SLP_1_TOP_RIGHT).

[0135] The third delay cycle sleep signal 364 (SLP_1_TOP_RIGHT) is then provided to the fourth logic circuit 350, 352. As with the previous memory array circuit, the fourth logic circuit 350, 352 of the top right memory cell 318 generates a logic state on the fourth bit line precharge signal 351 (BPCHB_TOP_RIGHT) to cause the power supply to precharge the memory cell bit line 353 (BL_TOP_RIGHT), the complementary bit line 355 (BLB_TOP_RIGHT). The third delay cycle sleep signal 364 (SLP_1_TOP_RIGHT) can then be provided to the next memory group. Therefore, due to this secondary sleep path, the bit lines of all four memory cells can be precharged in sequence.

[0136] Reference again Figure 5, the cyclic sleep signal 361 (SLP_1_BOT_LEFT) is circulated back to the first memory cell 312 as indicated by arrow 410, thereby causing the first logic circuit 320, 322 of the lower left memory cell 312 to transition 411 the logic state of the bit line precharge signal 323 (BPCHB_BOT_LEFT), thereby causing the power supply to precharge the memory cell bit line 321 (BL_BOT_LEFT), the complementary bit line 325 (BLB_BOT_LEFT). The precharging of the memory cell bit line 321 (BL_BOT_LEFT), the complementary bit line 325 (BLB_BOT_LEFT) can be seen by the transition 413 of the voltage that occurs in response to the transition 411 of the logic state of the bit line precharge signal 323 (BPCHB_BOT_LEFT). Likewise, the delayed cycle sleep signal 362 (SLP_1_BOT_RIGHT) then causes the second logic circuits 330, 332 of the bottom right memory cell 314 to switch 415 the logic state of the second bit line precharge signal 331 (BPCHB_BOT_RIGHT), thereby causing power to be supplied to precharge the memory cell bit line 333 (BL_BOT_RIGHT) and the complementary bit line 335 (BLB_BOT_RIGHT), as shown by the voltage transition 417. Next, the second delayed cycle sleep signal 363 (SLP_1_TOP_LEFT) then causes the third logic circuits 340, 342 of the top left memory cell 316 to switch 419 the logic state of the third bit line precharge signal 341 (BPCHB_TOP_LEFT), thereby causing power to be supplied to precharge the memory cell bit line 343 (BL_TOP_LEFT) and the complementary bit line 345 (BLB_TOP_LEFT), as shown by the voltage transition 421. Finally, the third delayed cycle sleep signal 364 (SLP_1_TOP_RIGHT) causes the fourth logic circuits 350, 352 of the upper right memory cell 318 to convert 423 the logic state of the fourth bit line pre-charge signal 351 (BPCHB_TOP_RIGHT), thereby causing the power supply to pre-charge the memory cell bit line 353 (BL_TOP_RIGHT) and the complementary bit line 355 (BLB_TOP_RIGHT), as shown by the voltage conversion 425.

[0137] The buffer for creating multiple delayed master sleep signals and cyclic sleep signals can be an even number of inverters in series. The number of inverters can be selected based on system requirements. For example, the number of inverters forming each buffer can be modified based on the required delay time between the master sleep signals (forming part of the wake-up memory time) and the required wake-up peak current. The first, second and third buffers can be configured to provide the cyclic sleep signal to the first logic circuit only after the third memory cell and / or the fourth memory cell are fully precharged. Therefore, the second and third buffers can form part of a delay circuit that receives the delayed master sleep signal and generates a cyclic sleep signal, wherein the delay circuit is configured to provide the cyclic sleep signal to the first logic circuit only after the specific memory cell is fully precharged. In some aspects, at least one buffer or at least one latch circuit can be excluded while retaining the sleep cycle, thereby retaining the separation or partial separation of the bit line precharge and the array power wake-up.

[0138] Although Figure 4 The cyclic sleep signal in is generated in response to the second delayed master sleep signal, but it should be understood that other configurations that separate the memory array power wake-up and bit line precharge operations can be implemented. The system can have multiple cyclic sleep signals, allowing for continuous wake-up and bit line precharge in each memory cell. For example, the first cyclic sleep signal can be used to precharge the bit lines of the lower left and lower right memory cells after the array power wake-up occurs in these cells but before the array power wake-up occurs in the upper left and upper right memory cells. Thereafter, the upper left and upper right memory cells can subsequently undergo a similar wake-up and bit line precharge sequence via the second cyclic path. In this way, the cyclic sleep signal can be generated based on the delayed master sleep signal, such as by the delayed master sleep signal or its derivative signal (such as the second delayed master sleep signal). Similarly, although many of the embodiments described herein depict the precharge and power sequence proceeding from the lower left memory cell to the lower right memory cell to the upper left memory cell and finally the upper right memory cell, it should be understood that these sequences can have alternative orderings (e.g., starting from the lower right memory cell).

[0139] Figure 6An example of a memory array 500 that may be incorporated into a power management circuit of a memory device described herein is shown in accordance with an embodiment, the memory array having memory cells. The memory array may specifically include a 6T static random access memory. The core of each cell shown in the memory array 500 may be formed by two complementary metal oxide semiconductor (CMOS) inverters. As previously described, the example memory array 500 may receive a bit line precharge signal at a gate terminal of a pair of PMOS transistors, the source terminals of the pair of transistors being coupled to a supply voltage, and the drain terminals of the pair of transistors being coupled to a bit line and a complementary bit line input terminal of each memory cell, respectively. As previously described, by separating the bit line precharge provided to each memory cell and the memory array supply precharge operation, the wake-up peak current may be reduced in the memory group.

[0140] Figure 7 An example of an SR latch consistent with one embodiment is shown. The latch can be used as Figure 4 At least one latch circuit in, namely, one of the first latch circuit 371, the second latch circuit 372, and the third latch circuit 373. The SR latch can effectively delay each cyclic sleep signal provided to each corresponding memory cell. As shown in the figure, the exemplary SR latch may include a pair of logic (NOR) gates and a pair of inverters. The logic (NOR) gates may be connected in a feedback configuration, wherein the output of the first logic (NOR) gate is coupled to the input of the second logic (NOR) gate, and the output of the second logic (NOR) gate is coupled to the input of the first logic (NOR) gate. The first inverter may be coupled to the second input of the first logic gate, and the second inverter 308 is coupled to the output of the second logic (NOR) gate. The bit line precharge signal (e.g., BLPCHB_BOT_LEFT) may be coupled as an input of the first inverter, and the cyclic sleep signal (e.g., SLP_1_BOT_LEFT) may be coupled as a second input of the second logic (NOR) gate. The output of the second inverter may provide a delayed cyclic sleep signal (e.g., SLP_1_BOT_RIGHT). The delayed cyclic sleep signal may be delayed relative to the cyclic sleep signal. The delayed cyclic sleep signal may be provided to the next memory cell where it may be used as an input to additional logic circuitry and as an input to another latch circuit.

[0141] Figure 8 is a flow chart of an example method 800 for controlling a wake-up operation of a memory array including a plurality of memory cells in accordance with one embodiment. The method 800 may be performed by Figure 4 The example power management circuit 300 shown in FIG. 8 is executed. At operation 802, a master sleep signal (eg, Figure 4 The master sleep signal may be generated by a first memory unit (eg, Figure 4 At operation 804, the first memory unit may be precharged in response to the master sleep signal. At operation 806, in a first buffer (e.g. Figure 4 The first buffer 324 in the buffer generates a delayed main sleep signal (eg, Figure 4 At operation 808, a cyclic signal (eg, Figure 4 The signal based on the delayed main sleep signal may include, for example, a second delayed sleep signal (e.g., Figure 4 At operation 810, in a first logic circuit (eg, Figure 4 The first logic circuit 322 in the embodiment generates a first bit line precharge signal (eg, Figure 4 Finally, at operation 812, at least one bit line of the first memory cell is precharged in response to the first bit line precharge signal.

[0142] Fig. 9 is a flow chart of an example method 900 for controlling a wake-up operation of a memory array including a plurality of memory cells in accordance with one embodiment. The method 900 may be performed by Figure 4 The example power management circuit 300 shown in FIG. 1 is executed. At operation 902, a master sleep signal (eg, Figure 4 In operation 904, a signal derived from the master sleep signal (e.g., SLP_BOT_LEFT in FIG. 1 ) is used to precharge at least one memory cell. Figure 4 SLP_1_BOT_LEFT in the first memory cell) generates a first bit line precharge signal (eg, Figure 4 At operation 906, a first bit line precharge signal is provided to precharge at least one bit line of the first memory cell. The first bit line precharge signal may be delayed from the master sleep signal to the extent that the at least one bit line is not precharged until after the first memory cell is fully precharged. Thus, while method 900 does not necessarily include the same components as method 800 (e.g., a first buffer), it can operate in a similar manner to delay bit line precharge until after the first memory cell is substantially precharged.

[0143] In one embodiment, a memory circuit includes: a first memory unit, configured to be precharged in response to receiving a master sleep signal; a first buffer, configured to receive the master sleep signal and generate a delayed master sleep signal; a first logic circuit, configured to generate a first bit line precharge signal for the first memory unit in response to a cyclic sleep signal, wherein the cyclic sleep signal is generated based on the delayed master sleep signal; and a first switching circuit, configured to provide power to at least one bit line of the first memory unit in response to the first bit line precharge signal.

[0144] In another embodiment, the memory circuit further comprises: a delay circuit receiving the delayed main sleep signal and generating a cyclic sleep signal, wherein the delay circuit is configured to delay the cyclic sleep signal until the first memory unit is fully precharged before providing it to the first logic circuit.

[0145] In another embodiment, it further includes: a second memory unit configured to be precharged in response to receiving the delayed master sleep signal; a second buffer configured to receive the delayed master sleep signal, generate a cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

[0146] In another embodiment, the memory circuit further includes: a second memory unit, configured to be precharged in response to receiving a delayed master sleep signal; a second buffer, configured to receive the delayed master sleep signal, generate a second delayed master sleep signal and provide the second delayed master sleep signal to a third memory unit; wherein the third memory unit is configured to be precharged in response to receiving the second delayed master sleep signal; and a third buffer, configured to receive the second delayed master sleep signal, generate a cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

[0147] In another embodiment, the third buffer is configured to provide the cyclic sleep signal to the fourth memory unit, and the fourth memory unit is configured to be precharged in response to receiving the cyclic sleep signal.

[0148] In another embodiment, the third buffer is configured to delay providing the cycle sleep signal to the first logic circuit until after the third memory cell is fully precharged.

[0149] In another embodiment, the memory circuit further includes: a first latch circuit receiving the cyclic sleep signal and the first bit line precharge signal and generating a delayed cyclic sleep signal.

[0150] In another embodiment, a memory circuit wherein the first latch circuit causes a transition in a logic state in the delayed cycling sleep signal to occur after power is provided to at least one bit line of the first memory cell.

[0151] In another embodiment, the memory circuit further includes: a second logic circuit configured to generate a second bit line precharge signal for a second memory cell among the memory cells, and the second logic circuit is configured to generate the second bit line precharge signal in response to the delay cycle sleep signal; and a second switching circuit configured to provide power to at least one bit line of the second memory cell in response to the second bit line precharge signal.

[0152] In another embodiment, the memory circuit further includes: a second latch circuit, which receives the delayed sleep signal and the second bit line precharge signal and generates the second delayed sleep signal; a third logic circuit, which is configured to generate a third bit line precharge signal for a third memory cell among these memory cells, and the third logic circuit is configured to generate the third bit line precharge signal corresponding to the second delayed sleep signal; and a third switching circuit, which is configured to provide power to at least one bit line of the third memory cell corresponding to the third bit line precharge signal; wherein the second latch circuit causes the transition of the logic state in the second delayed sleep signal to occur after power is provided to at least one bit line of the second memory cell.

[0153] In another embodiment, the memory circuit further includes: a third latch circuit, which receives the second delayed sleep signal and the third bit line precharge signal and generates a third delayed sleep signal; a fourth logic circuit, which is configured to generate a fourth bit line precharge signal for a fourth memory cell among these memory cells, and the fourth logic circuit is configured to generate the fourth bit line precharge signal corresponding to the third delayed sleep signal; and a fourth switching circuit, which is configured to provide power to at least one bit line of the fourth memory cell in response to the fourth bit line precharge signal, wherein the third latch circuit causes the transition of the logic state in the third delayed sleep signal to occur after power is provided to at least one bit line of the third memory cell.

[0154] In another embodiment, a control method is applied to a wake-up operation of a memory array including a plurality of memory cells, the control method comprising: receiving a master sleep signal indicating the start of the wake-up operation; precharging a first memory cell in response to the master sleep signal; generating a delayed master sleep signal in a first buffer in response to the master sleep signal; generating a cyclic sleep signal based on the delayed master sleep signal; generating a first bit line precharge signal of a first memory cell among these memory cells in a first logic circuit, the first bit line precharge signal being generated in response to the cyclic sleep signal; and precharging at least one bit line of the first memory cell in response to the first bit line precharge signal.

[0155] In another embodiment, the control method further includes: precharging the second memory unit in response to the delayed master sleep signal; wherein the cyclic sleep signal is generated in the second buffer in response to receiving the delayed master sleep signal.

[0156] In another embodiment, the control method further includes: precharging the second memory unit in response to receiving a delayed master sleep signal; generating a second delayed master sleep signal in a second buffer in response to the delayed master sleep signal; precharging the third memory unit in response to the second delayed master sleep signal; generating a cyclic sleep signal in the third buffer in response to the second delayed master sleep signal; and precharging the fourth memory unit in response to the cyclic sleep signal.

[0157] In another embodiment, the control method, wherein the delayed master sleep signal, the second delayed master sleep signal and the cyclic sleep signal are generated in sequence.

[0158] In another embodiment, the control method further includes: generating a delayed cyclic sleep signal in the first latch circuit in response to the cyclic sleep signal and the first bit line precharge signal.

[0159] In another embodiment, the control method further includes: generating a second bit line precharge signal for a second memory cell among the memory cells in a second logic circuit, the second bit line precharge signal being generated in response to the delay cycle sleep signal; and precharging at least one bit line of the second memory cell in response to the second bit line precharge signal.

[0160] In another embodiment, the control method further includes: generating a second delayed cycle sleep signal in a second latch circuit in response to the delayed cycle sleep signal and the second bit line precharge signal; generating a third bit line precharge signal of a third memory cell among these memory cells in a third logic circuit, the third bit line precharge signal being generated in response to the second delayed cycle sleep signal; precharging at least one bit line of the third memory cell in response to the third bit line precharge signal; generating a third delayed cycle sleep signal in the third latch circuit in response to the second cycle signal and the third bit line precharge signal; generating a fourth bit line precharge signal of a fourth memory cell among these memory cells in a fourth logic circuit in response to the third delayed sleep signal; and precharging at least one bit line of the fourth memory cell in response to the fourth bit line precharge signal.

[0161] In another embodiment, the control method, wherein the delayed cycle sleep signal, the second delayed cycle sleep signal, and the third delayed cycle sleep signal are generated in sequence.

[0162] In another embodiment, a control method is applied to a wake-up operation of a memory array including a plurality of memory cells, the control method comprising: providing a master sleep signal to precharge at least one memory cell; generating a first bit line precharge signal for a first memory cell from a signal derived from the master sleep signal; and providing a first bit line precharge signal to precharge at least one bit line of the first memory cell, wherein the first bit line precharge signal is delayed according to the master sleep signal until the first memory cell is fully precharged before precharging the at least one bit line.

[0163] The foregoing text summarizes the features of many embodiments so that those with ordinary knowledge in the art can better understand the present disclosure from various aspects. Those with ordinary knowledge in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A memory circuit, characterized in that: include: a first memory cell configured to be precharged in response to receiving a master sleep signal; a first buffer configured to receive the master sleep signal and generate a delayed master sleep signal; a first logic circuit configured to generate a first bit line precharge signal for the first memory cell in response to a cyclic sleep signal, wherein the cyclic sleep signal is generated based on the delayed main sleep signal; as well as A first switching circuit is configured to provide power to at least one bit line of the first memory cell in response to the first bit line precharge signal.

2. The memory circuit according to claim 1, wherein: Also includes: A delay circuit receives the delayed main sleep signal and generates the cyclic sleep signal, wherein the delay circuit is configured to delay the cyclic sleep signal until the first memory unit is fully precharged before providing it to the first logic circuit.

3. The memory circuit according to claim 1, wherein: Also includes: a second memory unit configured to be precharged in response to receiving the delayed master sleep signal; and A second buffer is configured to receive the delayed main sleep signal, generate a cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

4. The memory circuit according to claim 1, wherein: Also includes: a second memory unit configured to be precharged in response to receiving the delayed master sleep signal; a second buffer configured to receive the delayed master sleep signal, generate a second delayed master sleep signal and provide the second delayed master sleep signal to a third memory unit; wherein the third memory unit is configured to be precharged in response to receiving the second delayed master sleep signal; and A third buffer is configured to receive the second delayed master sleep signal, generate the cyclic sleep signal and provide the cyclic sleep signal to the first logic circuit.

5. The memory circuit according to claim 4, wherein: The third buffer is configured to provide the cyclic sleep signal to a fourth memory unit, and the fourth memory unit is configured to be precharged in response to receiving the cyclic sleep signal.

6. The memory circuit according to claim 4, wherein: The third buffer is configured to delay providing the cycle sleep signal to the first logic circuit until after the third memory cell is fully precharged.

7. The memory circuit according to claim 1, wherein: Also includes: A first latch circuit receives the cyclic sleep signal and the first bit line precharge signal and generates a delayed cyclic sleep signal.

8. The memory circuit according to claim 7, wherein: Also includes: a second logic circuit configured to generate a second bit line precharge signal for a second memory cell among the plurality of memory cells, and the second logic circuit is configured to generate the second bit line precharge signal in response to the delay cycle sleep signal; and A second switching circuit is configured to provide power to at least one bit line of the second memory cell in response to the second bit line precharge signal.

9. The memory circuit according to claim 8, wherein: Also includes: a second latch circuit, receiving a delayed sleep signal and the second bit line precharge signal and generating a second delayed sleep signal; a third logic circuit configured to generate a third bit line precharge signal for a third memory cell among the plurality of memory cells, and the third logic circuit is configured to generate the third bit line precharge signal in response to the second delayed sleep signal; as well as a third switching circuit configured to provide power to at least one bit line of the third memory cell in response to the third bit line precharge signal; The second latch circuit causes a logic state transition in the second delayed sleep signal to occur after power is provided to at least one bit line of the second memory cell.

10. The memory circuit according to claim 9, wherein: Also includes: a third latch circuit, receiving the second delayed sleep signal and the third bit line precharge signal and generating a third delayed sleep signal; a fourth logic circuit configured to generate a fourth bit line precharge signal for a fourth memory cell among the plurality of memory cells, the fourth logic circuit configured to generate the fourth bit line precharge signal in response to the third delayed sleep signal; and a fourth switching circuit configured to provide power to at least one bit line of the fourth memory cell in response to the fourth bit line precharge signal; The third latch circuit enables a logic state transition in the third delayed sleep signal to occur after power is provided to at least one bit line of the third memory cell.

Images