Semiconductor device

Abstract

A semiconductor device includes: a patterned passivation layer disposed on a contact pad; and the patterned polyimide layer is arranged on the patterned passivation layer. The patterned passivation layer defines a lower portion of a via opening, the via opening passing through the patterned polyimide layer and the patterned passivation layer, and wherein the patterned polyimide layer defines an upper portion of the via opening. The semiconductor device further includes a metal layer formed within the via opening and in contact with the top surface of the contact pad. An upper portion of the via opening has a first width and a lower portion of the via opening has a second width. The second width is smaller than the first width.

Description

Technical Field

[0001] The utility model relates to a semiconductor device and a forming method thereof, in particular to an opening pattern and a forming method thereof. Background Art

[0002] The electronics industry has experienced an increasing demand for smaller or faster semiconductor devices that can simultaneously support a greater number of more complex and sophisticated functions. As a result, there is an ongoing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Currently, these goals have been mostly achieved by reducing the size of semiconductor integrated circuits (e.g., minimum feature size), thereby improving mass production efficiency and reducing related costs. However, such size reductions have also increased the complexity of the semiconductor manufacturing process. Therefore, the continuous evolution in semiconductor integrated circuits and devices has also led to similar evolutions in semiconductor manufacturing processes and technologies.

[0003] For example, as a back-end of line (BEOL) process, one or more passivation layers may be formed on a semiconductor substrate that includes device layers (e.g., transistors and other similar devices) and a multi-layer interconnect (MLI) structure that provides interconnections between various microelectronic components within the substrate. In some embodiments, contact vias may be formed to electrically couple lower contact features to upper contact features (e.g., contact pads) that are connected to external circuits. In various examples, a polyimide (PI) layer formed on one or more passivation layers may be subjected to stress at a corner interface between the polyimide layer and the underlying passivation layer, which may cause cracks in the polyimide layer, thereby reducing the reliability of the device.

[0004] Thus, the prior art is not satisfactory in every respect. Utility Model Content

[0005] A semiconductor device includes: a patterned passivation layer disposed on a contact pad; a patterned polyimide layer disposed on the patterned passivation layer, wherein the patterned passivation layer defines a lower portion of a guide hole opening, and the guide hole opening passes through the patterned polyimide layer and the patterned passivation layer; and a metal layer formed in the guide hole opening and in contact with a top surface of the contact pad. The patterned polyimide layer defines an upper portion of the guide hole opening. The upper portion of the guide hole opening has a first width, and the lower portion of the guide hole opening has a second width. The second width is smaller than the first width.

[0006] In some embodiments, the contact pad is electrically coupled to the underlying multi-layer interconnect structure through a contact via.

[0007] In some embodiments, a multi-layer interconnect structure is disposed on a substrate.

[0008] In some embodiments, the multilayer interconnect structure further comprises: one or more dielectric layers disposed on the substrate; and a contact component passing through the plurality of dielectric layers, wherein the contact via contacts a top surface of the contact component.

[0009] In some embodiments, a first sidewall surface at an upper portion of the via opening and a second sidewall surface at a lower portion of the via opening together define a connected sidewall surface of the via opening, the connected sidewall surface having a step-difference pattern, wherein the first sidewall surface is recessed by a distance from the second sidewall surface.

[0010] In some embodiments, the distance is greater than 600 nm.

[0011] In some embodiments, the patterned polyimide layer does not overlap corners of the patterned passivation layer.

[0012] In some embodiments, the lower portion of the via opening is free of material used to form the patterned polyimide layer.

[0013] In some embodiments, the patterned passivation layer further includes: a barrier layer disposed on the contact pad; an oxide layer disposed on the barrier layer; and a nitrogen-containing layer disposed on the oxide layer.

[0014] In some embodiments, the metal layer further includes: an under bump metal (UBM) disposed on the contact pad; a copper pillar disposed on the under bump metal; and a solder bump disposed on the copper pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the sizes of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0016] Figure 1 is a flow chart of a method for forming a semiconductor device according to some embodiments.

[0017] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 ,and Fig. 9 According to some embodiments, Figure 1 A method is provided to provide a cross-sectional schematic diagram of a semiconductor device at an intermediate stage of the manufacturing process.

[0018] Fig. 8A According to some embodiments, Figure 8An enlarged schematic diagram of a portion of a semiconductor device.

[0019] The reference numerals are described as follows:

[0020] 100: Methods

[0021] 102: Box

[0022] 104: Box

[0023] 106: Box

[0024] 108: Box

[0025] 110: Box

[0026] 112: Box

[0027] 114: Box

[0028] 116: Box

[0029] 118: Box

[0030] 120: Box

[0031] 200: Semiconductor devices

[0032] 202: Base

[0033] 210: Interlayer dielectric

[0034] 220: Carbide layer

[0035] 230: Dielectric layer

[0036] 240: Dielectric layer

[0037] 250: Dielectric layer

[0038] 251: Barrier layer

[0039] 252: First passivation layer

[0040] 254: Lower contact part

[0041] 256: Dielectric layer

[0042] 258: Dielectric layer

[0043] 281: Barrier Layer

[0044] 283: Dielectric layer

[0045] 286: Opening

[0046] 287: Upper contact part

[0047] 290: Second passivation layer

[0048] 291: Dielectric layer

[0049] 292: Dielectric layer

[0050] 300: Polyimide layer

[0051] 301: Opening

[0052] 302: Opening

[0053] 303: Under Bump Metal

[0054] 305: Copper Pillar

[0055] 307: Welding bump

[0056] 310: Side wall

[0057] 312: Corner

[0058] 317: Part

[0059] D: Distance

[0060] W1: Top width

[0061] W2: bottom width

[0062] W3: Top width

[0063] W4: bottom width DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments or examples for implementing different components of the provided services. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description mentions that the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present invention may repeat reference symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0065] Furthermore, spatially relative terms, such as "below," "below," "below," "above," "above," and the like, may be used herein to describe the relationship of one element or component to other elements or components as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein may be interpreted in that rotated orientation as well.

[0066] In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, such terms are intended to cover numbers within a reasonable range, which is a reasonable range within the number understood by a person of ordinary skill in the art, such as within ±10% of the number. For example, the term "about 5 nanometers" covers a size range of 4.5 nanometers to 5.5 nanometers.

[0067] In various embodiments, as a back-end process, one or more passivation layers may be formed on a semiconductor substrate, the semiconductor substrate including component layers (e.g., transistors and other similar components) and a multi-layer interconnect (MLI) structure that provides interconnections between various microelectronic components within the substrate. In some embodiments, contact vias may be formed to electrically couple a lower contact component to an upper contact component (e.g., a contact pad), which is connected to an external circuit. In various examples, an opening is formed in the passivation layer to expose the surface of the upper contact component for electrical connection thereto. After forming the opening in the passivation layer, a polyimide layer may be formed and patterned. However, in some cases, stress at the corner interface between the passivation layer and the polyimide layer may cause cracks in the polyimide layer, thereby reducing device reliability. Thus, existing methods are not satisfactory in every respect.

[0068] Embodiments of the present invention provide advantages over the prior art, although it should be understood that other embodiments may provide different advantages, not all advantages need to be discussed herein, and no particular advantages are required for all embodiments. For example, the embodiments discussed herein include methods for improving the reliability of a patterned polyimide layer formed on one or more passivation layers (as a back-end process). The disclosed embodiments also provide a simplified process for forming a patterned polyimide layer at a lower cost (e.g., by reducing the number of masks used to make the device). In particular, in various embodiments, a single photolithography step (e.g., a single mask) may be used to pattern the polyimide layer and the underlying passivation layer (e.g., to form a via to expose the surface of the upper contact component). Furthermore, relative to existing implementation methods, no portion of the polyimide layer will be left in the via formed in the underlying passivation layer, or at the corners of the via opening. As a result, stress at the corner interface between the passivation layer and the polyimide layer, and potential cracks in the polyimide layer caused by the stress, can be avoided. Additional details of embodiments of the present invention are provided below, and additional benefits and / or other advantages will become more apparent to those having ordinary skill in the art.

[0069] Reference Figure 1 , according to some embodiments, a method 100 of forming a semiconductor device is illustrated. The method 100 will refer to Figure 2 to Figure 9 As detailed below, Figure 2 to Figure 9 A schematic cross-sectional view of a semiconductor device 200 at various stages of manufacture is provided in accordance with an embodiment of the present invention. It will be understood that method 100 is merely an example and is not intended to limit the embodiments of the present invention to the contents explicitly depicted in method 100. In addition, additional process steps may be performed before, during, or after method 100, and some of the process steps described may be replaced or eliminated according to various embodiments of method 100. It should also be noted that for clarity of discussion, not all steps are described in detail herein. In addition, portions of method 100 may be performed by existing complementary metal oxide semiconductor (CMOS) technology manufacturing processes, and therefore only some processes are briefly described herein.

[0070] The method 100 begins at block 102, where a substrate including one or more dielectric layers is provided. Figure 2 , and In one embodiment of block 102, the semiconductor device 200 includes a provided substrate 202. The substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various film layers, including conductive or insulating film layers formed on the substrate 202. The substrate 202 may include various doping configurations, depending on the design requirements of the prior art. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Furthermore, in some embodiments, the substrate 202 may include an epitaxial layer, the substrate 202 may be strained to improve performance, the substrate 202 may include a silicon-on-insulator (SOI) structure, and / or the substrate 202 may have other suitable enhancement components.

[0071] In some embodiments, substrate 202 includes one or more active and / or passive semiconductor devices, such as transistors, diodes, optoelectronic devices, resistors, capacitors, sensors, or other devices. In various examples, transistors may include source / drain components, gate structures, gate spacers, contact components, isolation structures (such as shallow trench isolation (STI) structures), or other suitable components. For example, active and / or passive semiconductor devices formed in substrate 202 may be formed as part of a front-end of line (FEOL) process.

[0072] In various examples, the substrate 202 may also include an interconnect structure (e.g., a multilayer interconnect structure) that may include multiple patterned dielectric layers and conductive layers to provide interconnections (e.g., wiring) between various microelectronic components formed within the substrate 202. For example, the multilayer interconnect structure and other film layers, components, components, or elements formed on the multilayer interconnect structure may be formed as part of a back-end process. In addition, in at least some cases, one or more dielectric layers and / or conductive layers of the multilayer interconnect structure may be formed on the substrate 202. As described above, the interconnect structure may include multiple conductive components and multiple dielectric components used to provide isolation between the conductive components. In some embodiments, the conductive components may include contacts, vias, or metal lines to provide horizontal and vertical interconnections. In some cases, the metal lines may include copper (Cu), aluminum (Al), aluminum copper (AlCu) alloy, ruthenium (Ru), cobalt (Co), or other suitable metal layers. In some examples, the contacts and / or vias may include copper, aluminum, aluminum-copper alloy, ruthenium, cobalt, tungsten (W), or other suitable metal layers. In some embodiments, the dielectric components of the multilayer interconnect structure may include silicon oxide (SiO) or silicon oxide-containing materials (where silicon is present in various suitable states). In some examples, the dielectric components may include a low-k dielectric layer (e.g., having a dielectric constant less than silicon dioxide (SiO 2 ) having a dielectric constant of about 3.9), such as tetraethoxysilane (TEOS) oxide, undoped silicate glass (USG), or doped silicon oxide (such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable low dielectric constant dielectric materials).

[0073] In some embodiments, and in further embodiments of block 102, an interlayer dielectric (ILD) 210 is formed on the substrate 202. The interlayer dielectric 210 may include silicon oxide, a silicon oxide-containing material, or a low-k dielectric layer, such as tetraethoxysilane oxide, undoped silicate glass, or doped silicon oxide (such as boron-doped phosphosilicate glass, fluorosilicate glass, phosphosilicate glass, boron-doped silicate glass, and / or other suitable low-k dielectric materials). In various examples, the interlayer dielectric 210 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. As an example, the interlayer dielectric 210 may have a thickness of about 200 nm. In other embodiments, the interlayer dielectric 210 may have a thickness between about 150 nm and 250 nm. The interlayer dielectric 210 may be conformally deposited to have a substantially uniform thickness.

[0074] In some examples, and in further embodiments of block 102, a carbide layer 220 may be formed on the interlayer dielectric 210. In some embodiments, the carbide layer 220 may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof. In some embodiments, the carbide layer 220 may include a silicon carbide layer, although other types of carbide materials may be used. In some examples, the carbide layer 220 may have a thickness of about 55 nm. In other embodiments, the carbide layer 220 may have a thickness between about 45 nm and 65 nm. In some embodiments, the carbide layer 220 may be conformally deposited to have a substantially uniform thickness.

[0075] Continue to refer to Figure 2, and in a further embodiment of block 102, the semiconductor device 200 further includes a dielectric layer 230 formed on the carbide layer 220. In some embodiments, the dielectric layer 230 may include silicon oxide or a material containing silicon oxide. In some cases, the dielectric layer 230 may include undoped silicate glass. In various examples, the dielectric layer 230 may be deposited by plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition, physical vapor deposition, or a combination thereof. In some cases, the dielectric layer 230 may have a thickness of about 620 nm. In other embodiments, the dielectric layer 230 may have a thickness between about 575 nm and 675 nm. In some embodiments, the dielectric layer 230 may be conformally deposited to have a substantially uniform thickness.

[0076] In some embodiments, and in further embodiments of block 102, a dielectric layer 240 may be formed on dielectric layer 230. In some cases, dielectric layer 240 may include a nitrogen-containing material and / or a carbon-containing material. For example, dielectric layer 240 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide, silicon oxycarbonitride (SiOCN), silicon nitride (SiN), or a combination thereof. In some embodiments, dielectric layer 240 may have a thickness of about 50 nm. In other embodiments, dielectric layer 240 may have a thickness between about 45 nm and 55 nm. In various examples, dielectric layer 240 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In some cases, dielectric layer 240 may serve as an etch stop layer (ESL).

[0077] The method 100 proceeds to block 104 where a lower contact feature is formed. Figure 2, and in one embodiment of block 104, a dielectric layer 250 may be deposited on the dielectric layer 240. In some embodiments, the dielectric layer 250 includes silicon oxide or a material containing silicon oxide. In some cases, the dielectric layer 250 may include undoped silicate glass. In various examples, the dielectric layer 250 may be deposited by plasma assisted chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In some cases, the dielectric layer 250 may have a thickness of about 900 nm. In other embodiments, the dielectric layer 250 may have a thickness between about 800 nm and 1000 nm. In some embodiments, the dielectric layer 250 may be conformally deposited to have a substantially uniform thickness.

[0078] After the deposition of the dielectric layer 250, and in further embodiments of block 104, the dielectric layer 250 may be patterned to form trenches. In various examples, the patterning of the dielectric layer 250 may use a suitable combination of photolithography processes (e.g., photoresist deposition, exposure, and development) to form an etch mask, and an etch process using the etch mask to form the trenches. In some cases, a hard mask layer (e.g., a nitrogen-containing layer) may be used as part of the patterning process of the dielectric layer 250.

[0079] In some embodiments, and in further embodiments of block 104, a lower contact feature 254 is formed in a trench provided by the patterned dielectric layer 250. It will be appreciated that other lower contact features may be similarly formed in other trenches, also provided by the patterned dielectric layer. Although the lower contact feature 254 is disposed below the upper contact feature (described below), the lower contact feature 254, as well as any other lower contact features, are sometimes referred to as top metal (TM) contacts because they represent the top metal layer of a multi-layer interconnect structure (as described above). In some embodiments, the lower contact feature 254 may include a barrier layer 251, and a metal fill layer to complete the overall structure. For example, forming the lower contact feature 254 includes multiple processes. In some embodiments, a barrier layer 251 is formed in each trench (provided by the patterned dielectric layer 250), followed by deposition of a metal fill layer on the barrier layer 251. In some embodiments, the barrier layer 251 includes titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In some embodiments, the metal filling layer includes a metal or a metal alloy, such as copper, cobalt, nickel (Ni), aluminum, tungsten, titanium (Ti), or a combination thereof. In some embodiments, the metal filling layer is formed by deposition or electroplating, followed by a chemical mechanical planarization (CMP) process.

[0080] After forming the lower contact feature 254, the method 100 proceeds to block 106 where a first passivation layer is formed. Figure 2 As shown, and in one embodiment of block 106, a first passivation layer 252 is formed in the semiconductor device 200 (including on the lower contact member 254). In some embodiments, the first passivation layer 252 includes a dielectric layer 256 formed on the lower contact member 254. In some embodiments, the thickness of the dielectric layer 256 is about 75 nm. In other embodiments, the dielectric layer 256 may have a thickness between about 65 nm and 85 nm. The dielectric layer 256 may include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 256 may include silicon carbonitride, silicon oxycarbide, silicon carbide, silicon oxycarbonitride, silicon nitride, or a combination thereof. In various examples, the dielectric layer 256 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In some embodiments, the dielectric layer 256 may protect the lower contact member 254 from oxidation.

[0081] The first passivation layer 252 may further include a dielectric layer 258 formed on the dielectric layer 256. In some embodiments, the dielectric layer 258 may include silicon oxide or a material containing silicon oxide. In some cases, the dielectric layer 258 may include undoped silicate glass. The dielectric layer 258 may be deposited by plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. Thus, in some cases, the dielectric layer 258 may be referred to as plasma-enhanced oxide (PEOX). In some cases, the dielectric layer 258 may have a thickness of about 750 nm. In other embodiments, the dielectric layer 258 may have a thickness between about 600 nm and 1000 nm. In at least some embodiments, the first passivation layer 252 may only include the dielectric layer 256, but not the dielectric layer 258.

[0082] After forming the first passivation layer 252, the method 100 proceeds to block 108 where an opening is formed to expose the lower contact feature. Figure 3 As shown, and in one embodiment of block 108, an opening 286 is formed. The opening 286 may penetrate the first passivation layer 252 (including the dielectric layer 258 and the dielectric layer 256) to expose the top surface of the lower contact member 254. In some embodiments, the opening 286 may be formed using an etching process (e.g., a dry etching process, a wet etching process, or a combination thereof). In various embodiments, the sidewalls of the opening 286 may expose the sidewalls of various film layers that are exposed through the penetration of the opening 286. In some cases, such as when the first passivation layer 252 does not include the dielectric layer 258, the opening 286 may simply penetrate the dielectric layer 256 to expose the top surface of the lower contact member 254.

[0083] The method 100 proceeds to block 110 where an upper contact feature is formed. Figure 4 , and in one embodiment of block 110, forming an upper contact feature 287 in and over the opening 286. The upper contact feature 287 includes a contact via that fills the opening 286 and may be referred to as a contact via, a metal via, or a metal line. In some embodiments, to form the upper contact feature 287, a barrier layer 281 is first conformally deposited on the first passivation layer 252 and in the opening 286 using a suitable deposition technique (e.g., atomic layer deposition, physical vapor deposition, or chemical vapor deposition), and then a metal fill layer is deposited on the barrier layer 281 using a suitable deposition technique (e.g., atomic layer deposition, physical vapor deposition, or chemical vapor deposition). Then, the deposited barrier layer 281 and the metal fill layer are patterned to form the upper contact feature 287, such as Figure 4In some cases, the upper contact feature 287, and similar contact features formed therefrom, may be referred to as contact pads. In some embodiments, the barrier layer 281 and the metal fill layer are patterned in a two-stage or multi-stage etching process. Figure 4 In the example of FIG. 2 , the portion of the upper contact member 287 extending above the first passivation layer 252 has substantially straight sidewalls. However, in some alternative embodiments, the portion of the upper contact member 287 extending above the first passivation layer 252 may have tapered sidewalls.

[0084] In some embodiments, the upper portion of upper contact component 287, and other similar contact components, is part of a redistribution layer (RDL), which includes various metal lines used to redistribute bonding pads to different locations, such as from peripheral locations to be evenly distributed on the surface of the wafer. In various examples, the redistribution layer couples the multi-layer interconnect structure to the bonding pads, which are connected to external circuits. In addition, the upper contact component (such as upper contact component 287) provides electrical contact to the lower contact component (such as lower contact component 254).

[0085] The method 100 proceeds to block 112 where a second passivation layer is formed. Figure 5 , and in one embodiment of block 112, a second passivation layer 290 is formed in the semiconductor device 200 (including on the upper contact member 287 and on the first passivation layer 252). In some embodiments, the second passivation layer 290 includes a dielectric layer 291 formed on the upper contact member 287 and on the first passivation layer 252. In some embodiments, the dielectric layer 291 may include silicon oxide or a silicon oxide-containing material. In some cases, the dielectric layer 291 may include undoped silicate glass. The dielectric layer 291 may be deposited by plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. Thus, in some cases, the dielectric layer 291 may be referred to as plasma-enhanced oxide (PEOX). In some cases, the dielectric layer 291 may have a thickness of about 900 nm. In other embodiments, the dielectric layer 291 may have a thickness between about 800 nm and 1000 nm. In some cases, dielectric layer 283 may be formed on the portion of upper contact feature 287 disposed above first passivation layer 252 as part of second passivation layer 290 and before dielectric layer 291 is deposited, such as Figure 5As shown. In some embodiments, the thickness of the dielectric layer 283 is about 200nm. In other embodiments, the dielectric layer 283 may have a thickness between about 75nm and 300nm. The dielectric layer 283 may include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 283 may include silicon carbonitride, silicon oxycarbide, silicon carbide, silicon oxycarbonitride, silicon nitride, or a combination thereof. In various examples, the dielectric layer 283 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof. In some embodiments, the dielectric layer 283 may serve as a barrier layer and may protect the upper contact member 287 from oxidation. In some examples, the second passivation layer 290 further includes a dielectric layer 292 formed on the dielectric layer 291. In some embodiments, the thickness of the dielectric layer 292 is about 800nm. In other embodiments, the dielectric layer 292 may have a thickness between about 700nm and 900nm. The dielectric layer 292 may include a nitrogen-containing material and / or a carbon-containing material. For example, the dielectric layer 292 may include silicon carbonitride, silicon oxycarbide, silicon carbide, silicon oxycarbonitride, silicon nitride, or a combination thereof. In various examples, the dielectric layer 292 may be deposited by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof.

[0086] The method 100 proceeds to block 114 where a polyimide layer is formed. Figure 6 , and in one embodiment of block 114, a polyimide layer 300 is deposited on the dielectric layer 292 using a suitable deposition technique, such as spin-on coating or vapor-deposition process (VDP). The polyimide layer 300 may include a photosensitive material (e.g., a photosensitive agent), such as the polyimide layer 300 including a negative tone or positive tone photosensitive polyimide layer. For discussion purposes, the polyimide layer 300 includes a negative tone photosensitive polyimide layer. For confirmation, in at least some embodiments, the polyimide layer 300 may have non-photosensitive properties. In some examples, the polyimide layer 300 may have a thickness between about 2.2 μm and 5.0 μm. In some embodiments, a baking (or curing) process may be performed after the polyimide layer 300 is deposited. The formation of the polyimide layer 300, as shown and described herein, can be in contrast to at least some prior art embodiments, which form openings to expose the upper contact features prior to depositing the polyimide layer. By first depositing (and subsequently patterning) the polyimide layer 300, the process can be simplified and costs can be reduced (e.g., by reducing the number of masks used in the process), as described below.

[0087] After forming the polyimide layer 300, the method 100 proceeds to block 116 where the polyimide layer is patterned. Figure 7, and in one embodiment of block 116, the polyimide layer 300 is patterned to form an opening 301 to expose the dielectric layer 292 of the second passivation layer 290. In some embodiments, since the polyimide layer 300 is photosensitive, a suitable photolithography process (such as an exposure process and a development process) can be used to pattern the polyimide layer 300 without using a subsequent etching process. However, in other embodiments where the polyimide layer 300 is non-photosensitive, the patterning of the polyimide layer 300 can use another suitable combination of photolithography processes (such as photoresist deposition, exposure, and development) to form an etching mask, and then an etching process can be performed using the etching mask to form the opening 301.

[0088] The method 100 proceeds to block 118 where an opening is formed to expose the upper contact feature. Figure 8 As shown, and in one embodiment of box 118, an opening 302 is formed. In some examples, the formation of the opening 302 can be referred to as enlarging or expanding the opening 301 (as described above). In some embodiments, the opening 302 can pass through (from top to bottom) the polyimide layer 300, the dielectric layer 292, the dielectric layer 291, and the dielectric layer 283 to expose the top surface of the upper contact member 287, wherein the sidewalls of the opening 302 expose the sidewalls of the various film layers, which are exposed through the passage of the opening 302. In various embodiments, the opening 302 can define a via opening that exposes the top surface of the upper contact member 287, wherein the upper portion of the via opening is defined by the patterned polyimide layer 300, and the lower portion of the via opening is defined by the patterned second passivation layer 290 (e.g., the patterned dielectric layer 292, the dielectric layer 291, the dielectric layer 283). In Figure 8 In the example of Fig. 8A As more clearly shown in FIG. 3 (showing an enlarged schematic diagram of portion 317 of semiconductor device 200 including opening 302), each of the upper portion and the lower portion of the via opening has a tapered sidewall, wherein a top width W1 of the upper portion is greater than a bottom width W2 of the upper portion, and wherein a top width W3 of the lower portion is greater than a bottom width W4 of the lower portion. However, in some alternative embodiments, one or both of the upper portion and the lower portion of the via opening may have substantially straight sidewalls.

[0089] It is noteworthy that the result of patterning the polyimide layer 300 (block 116) prior to forming the opening 302 is that no polyimide layer 300 remains within the lower portion of the via opening, which is defined by the patterned second passivation layer 290. Stated another way, the lower portion of the via opening is free of material used to form the polyimide layer 300. In various embodiments, forming the opening 302 may result in the sidewall surface 310 of the patterned polyimide layer 300 within the upper portion of the via opening being etched back by a corner 312 (of the patterned second passivation layer 290 within the lower portion of the via opening) to a distance D, with the corner 312 defined along both side surfaces of the opening 302, such that the corner 312 is completely exposed. In some embodiments, the distance D is greater than about 600 nm. Stated another way, etching back the sidewall surface 310 of the patterned polyimide layer 300 to a distance D will result in a composite via opening (e.g., including both an upper portion and a lower portion) having a jog pattern such that a bottom width W2 of the upper portion of the via opening is greater than a top width W3 of the lower portion of the via opening. Thus, in some examples, the jog pattern can be said to have a width greater than about 600 nm. In the case where each of the upper and lower portions of the via opening has substantially straight sidewalls, it can be simply said that the width of the upper portion of the via opening is greater than the width of the lower portion of the via opening. By ensuring that the patterned polyimide layer 300 does not overlap the corner 312, potential stress at the corner 312 and potential cracks in the patterned polyimide layer 300 resulting from the stress thereof can be avoided.

[0090] In some embodiments, an etching process (e.g., a dry etching process, a wet etching process, or a combination thereof) may be used to form the opening 302. In some cases, the etching process used to form the opening 302 etches downward through the second passivation layer 290 (e.g., dielectric layer 292, dielectric layer 291, dielectric layer 283) exposed by the previously formed opening 301, while etching laterally from the corner 312 to recess the sidewall surface 310 of the patterned polyimide layer 300 to a distance D. In other embodiments, a dry etching process and a wet etching process may be performed sequentially to form the opening 302. For example, in some cases, a dry etching process may first be performed using the previously patterned polyimide layer 300 as an etching mask to etch downward through the second passivation layer 290 (e.g., dielectric layer 292, dielectric layer 291, dielectric layer 283), and then a wet etching process may be performed to recess the sidewall surface 310 of the patterned polyimide layer 300 to a distance D from the corner 312. In some cases, the etching chemistry of the dry etching process used to form the opening 302 includes carbon tetrafluoride (CF 4 ), nitrogen trifluoride (NF 3), argon (Ar), oxygen (O 2 ), combinations thereof, and / or other suitable etching chemicals. In some embodiments, the etching chemicals of the wet etching process used to form the opening 302 include ST250, dilute hydrofluoric acid (dHF), combinations thereof, and / or other suitable etching chemicals. Although some examples of etching processes and etching chemicals used to form the opening 302 have been proposed, it will be understood that other and / or additional processes and additional etching chemicals may be used without departing from the scope of the embodiments of the present invention. In addition, regardless of the exact etching process and etching chemicals used to form the opening 302, it is worth noting that the disclosed embodiments provide for the use of a single mask to form the opening 302, which simplifies the device process and reduces costs. Specifically, a mask can be used to pattern the polyimide layer of the box 116 to form the opening 301, without the need for an additional mask to further form the opening 302 of the box 118.

[0091] The method 100 proceeds to block 120 where a bumping process is performed. Fig. 9, and in one embodiment of block 120, the bump process includes forming an under bump metallization (UBM) 303, a copper pillar 305 (or copper bump) on the under bump metallization 303, and a solder bump 307 on the copper pillar 305. In some embodiments, the under bump metallization 303 provides a low resistance electrical connection to the redistribution layer in the upper portion of the upper contact member 287. The under bump metallization 303 also seals very tightly and prevents other bump metals from diffusing into the semiconductor device 200. In various examples, the under bump metallization 303 includes multiple layers of different metals, such as an adhesion layer (e.g., titanium, chromium (Cr), aluminum, or other similar materials), a diffusion barrier layer (e.g., chromium copper (CrCu) alloy), a solder layer, and an oxidation barrier layer (e.g., gold (Au)). The various film layers of the under bump metal 303 may be deposited by electroplating, sputtering, evaporation, or other suitable methods. In some embodiments, a copper seed layer may be deposited before forming the copper pillar 305, which may be formed by an electroplating process. In addition, in some cases, a diffusion barrier layer (e.g., nickel) may be formed between the copper pillar 305 and the solder bump 307 to prevent the formation of an intermetallic layer and / or microvoids. After forming the copper pillar 305, an electroplating process may be used to form the solder bump 307 on the copper pillar 305. One or more patterning processes (e.g., lithography and / or etching processes) may be performed to pattern one or more film layers deposited during the bump process. In some embodiments, after the solder deposition, a reflow process may also be performed to form the solder bump 307. For example, the formation of the under bump metal 303, the copper pillar 305, and the solder bump 307 provides a contact structure to connect to an external circuit. In some prior art implementations where a polyimide layer is formed on the corners 312, stress and potential cracks in the polyimide layer 300 are maximized during the bumping process. However, according to various embodiments disclosed herein, stress and potential cracks in the polyimide layer 300 are avoided by ensuring that the patterned polyimide layer 300 does not overlap the corners 312. Thus, the reliability of the patterned polyimide layer 300 is improved.

[0092] Various embodiments described herein provide multiple advantages over the prior art. It will be understood that not all advantages need to be discussed herein, no particular advantage is required for all embodiments, and other embodiments may provide different advantages. For example, the embodiments discussed herein include methods for improving the reliability of a patterned polyimide layer formed on one or more passivation layers (as a back-end process). The disclosed embodiments also provide a simplified process for forming a patterned polyimide layer at a lower cost (e.g., by reducing the number of masks used to make the device). In particular, in various embodiments, a single photolithography step (e.g., a single mask) can be used to pattern the polyimide layer and the underlying passivation layer (e.g., to form a via to expose the surface of the upper contact component). Furthermore, relative to existing embodiments, no portion of the polyimide layer will be left in the via formed in the underlying passivation layer, or at the corners of the via opening. As a result, stress at the corner interface between the passivation layer and the polyimide layer, and any potential cracks in the polyimide layer caused by the stress therefrom, can be avoided. Additional benefits and / or other advantages will become apparent to those having ordinary skill in the art.

[0093] Thus, one embodiment of the present invention describes a method for forming a semiconductor device, comprising: depositing a passivation layer on an upper contact component; forming a polyimide layer on the passivation layer; patterning the polyimide layer to form a patterned polyimide layer, the patterned polyimide layer comprising a first opening exposing a portion of the passivation layer on the upper contact component; and performing one or more etching processes to form a second opening exposing a top surface of the upper contact component. The etching process etches the passivation layer through the first opening to form a patterned passivation layer. The etching process recesses multiple sidewall surfaces of the patterned polyimide layer by multiple corners of the patterned passivation layer. The corners are defined along two side surfaces of the second opening.

[0094] In some embodiments, the second opening defines a via opening, including an upper portion defined by a patterned polyimide layer and a lower portion defined by a patterned passivation layer, the patterned polyimide layer having a recessed sidewall surface. In some embodiments, the top width (W1) of the upper portion is greater than the bottom width (W2) of the upper portion, wherein the top width (W3) of the lower portion is greater than the bottom width (W4) of the lower portion, and wherein the bottom width (W2) of the upper portion is greater than the top width (W3) of the lower portion. In some embodiments, the lower portion of the via opening does not have a material used to form a polyimide layer. In some embodiments, the etching process recesses the sidewall surface of the patterned polyimide layer by a distance greater than about 600 nm from the corner of the patterned passivation layer. In some embodiments, the via opening includes a step pattern defined along both side surfaces of the second opening. In some embodiments, the first width of the upper portion of the via opening is greater than the second width of the lower portion of the via opening. In some embodiments, depositing the passivation layer further includes: depositing a barrier layer on the upper contact member; depositing an oxide layer on the barrier layer; and depositing a nitrogen-containing layer on the oxide layer. In some embodiments, the etching process simultaneously etches the passivation layer through the first opening and recesses the sidewall surface of the patterned polyimide layer. In some embodiments, performing the etching process includes sequentially performing a dry etching process and a wet etching process, wherein the dry etching process etches the passivation layer through the first opening, and wherein the wet etching process recesses the sidewall surface of the patterned polyimide layer. In some embodiments, the method for forming a semiconductor device further includes: after forming the second opening, performing a bump process to form a plurality of contact structures in the second opening.

[0095] In another embodiment of the present invention, a method for forming a semiconductor device is discussed, including: forming a contact pad, electrically coupling the contact pad to a multilayer interconnect structure below via a contact via; depositing an oxide layer on the contact pad, a nitride layer on the oxide layer, and a polyimide layer on the nitride layer; and forming a via opening through the polyimide layer, the nitride layer, and the oxide layer, and exposing a top surface of the contact pad. The via opening includes an upper portion and a lower portion. The upper portion has a first width, and the lower portion has a second width. The second width is less than the first width.

[0096] In some embodiments, the upper portion and the lower portion together define a step pattern along a plurality of sidewall surfaces of the via opening. In some embodiments, the step pattern has a width greater than about 600 nm. In some embodiments, the upper portion includes a polyimide layer, wherein the lower portion includes a nitride layer and an oxide layer, and wherein the via opening is formed by etching a plurality of sidewall surfaces of the polyimide layer of the upper portion by a plurality of corners of the nitride layer of the lower portion, the corners being defined along the sidewall surfaces of the via opening. In some embodiments, the lower portion of the via opening does not have a material for depositing a polyimide layer. In some embodiments, the method for forming a semiconductor device further includes: after forming the via opening, performing a bump process to form a plurality of contact structures within the via opening.

[0097] In yet another embodiment of the present invention, a semiconductor device is discussed, comprising: a patterned passivation layer disposed on a contact pad; a patterned polyimide layer disposed on the patterned passivation layer, wherein the patterned passivation layer defines a lower portion of a via opening, the via opening passing through the patterned polyimide layer and the patterned passivation layer; and a metal layer formed in the via opening and in contact with a top surface of the contact pad. The patterned polyimide layer defines an upper portion of the via opening. The upper portion of the via opening has a first width, and the lower portion of the via opening has a second width. The second width is less than the first width.

[0098] In some embodiments, the contact pad is electrically coupled to the underlying multi-layer interconnect structure through the contact via. In some embodiments, the first sidewall surface of the upper portion of the via opening and the second sidewall surface of the lower portion of the via opening together define a connected sidewall surface of the via opening, the connected sidewall surface having a step difference pattern, and wherein the first sidewall surface is recessed by the second sidewall surface for a distance.

[0099] The features of several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the concepts of the embodiments of the utility model. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the utility model to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such or other structures with similar effects do not deviate from the spirit and scope of the embodiments of the utility model, and various changes, substitutions and replacements can be made without violating the spirit and scope of the embodiments of the utility model.

Claims

1. A semiconductor device, characterized in that: include: a patterned passivation layer disposed on a contact pad; a patterned polyimide layer disposed on the patterned passivation layer, wherein the patterned passivation layer defines a lower portion of a via opening, the via opening passes through the patterned polyimide layer and the patterned passivation layer, and wherein the patterned polyimide layer defines an upper portion of the via opening; and a metal layer formed in the via opening and in contact with the top surface of the contact pad; The upper portion of the guide hole opening has a first width, and the lower portion of the guide hole opening has a second width, which is smaller than the first width.

2. The semiconductor device according to claim 1, wherein The contact pad is electrically coupled to a multi-layer interconnection structure below through a contact via.

3. The semiconductor device according to claim 2, wherein: The multi-layer interconnection structure is arranged on a substrate.

4. The semiconductor device according to claim 3, wherein: The multi-layer interconnect structure further comprises: one or more dielectric layers disposed on the substrate; and A contact component passes through the plurality of dielectric layers, wherein the contact via contacts a top surface of the contact component.

5. The semiconductor device according to claim 1, wherein: A first side wall surface of the upper portion of the via opening and a second side wall surface of the lower portion of the via opening together define a connected side wall surface of the via opening, the connected side wall surface has a step pattern, and the first side wall surface is recessed by the second side wall surface for a distance.

6. The semiconductor device according to claim 5, wherein: This distance is greater than 600 nm.

7. The semiconductor device according to claim 5, wherein: The patterned polyimide layer does not overlap multiple corners of the patterned passivation layer.

8. The semiconductor device according to claim 1, wherein The lower portion of the via opening is free of material used to form the patterned polyimide layer.

9. The semiconductor device according to claim 1, wherein: The patterned passivation layer further comprises: a barrier layer disposed on the contact pad; an oxide layer disposed on the barrier layer; and A nitrogen-containing layer is disposed on the oxide layer.

10. The semiconductor device according to claim 1, wherein The metal layer further comprises: an under bump metallization disposed on the contact pad; a copper pillar disposed on the under bump metallurgy; and A welding bump is disposed on the copper column.

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