SiC groove MOSFET device

Abstract

The utility model discloses a SiC trench MOSFET device comprising an epitaxial layer, the epitaxial layer is provided with two gate trenches, silicon dioxide layers are formed on the bottoms and the side walls of the gate trenches, the remaining positions of the trenches on the upper surfaces of the silicon dioxide layers in the trenches are filled with gate polycrystalline silicon, the middle trench between the two gate trenches is filled with polycrystalline silicon, and the gate trenches are filled with silicon dioxide. The side face and the bottom of the grid groove are each provided with a P well region, an N + source region and a P + region are formed in the P well region on the side face, the P well at the bottom and the bottom of the N + region are surrounded by a P + shielding layer, and the P + shielding layer is in a step shape. An additional N + source region is arranged at the bottom of the groove, so that the channel density is improved, the specific on-resistance of the device is remarkably reduced, the chip area is further reduced, and the production cost is reduced; meanwhile, an integrated JFET device is introduced through the two P + regions at the bottom of the gate trench and the polycrystalline silicon in the middle trench, the bipolar degeneration effect of a body diode during reverse opening is eliminated, and the reliability of the device is greatly improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of semiconductors, and in particular relates to a SiC trench MOSFET device. Background Art

[0002] As the third generation wide bandgap semiconductor material, silicon carbide (SiC) has the advantages of wide bandgap, high critical breakdown electric field, high electron saturation mobility and high thermal conductivity, and has become a hot topic in current power device research. SiC planar MOSFET has been commercialized for a long time. In order to further improve the electrical performance of the device, SiC trench MOSFET was proposed. Compared with SiC planar MOSFET, the vertical channel distribution of trench MOSFET greatly improves the device density, reduces the chip area, makes the device power density higher and reduces the cost.

[0003] Traditional Fig.13 As shown in the figure: In order to reduce the silicon dioxide electric field at the bottom corner of the trench, the SiC trench MOSFET introduces a P+ shielding layer at the bottom of the trench, but the introduced shielding layer will increase the device's specific on-resistance (Ron, sp); at the same time, the traditional SiC MOSFET also has a bipolar degradation effect caused by the body diode, which reduces the reliability of the device.

[0004] Therefore, the main purpose of the utility model patent is to provide a SiC trench MOSFET device and a manufacturing method thereof to solve the above-mentioned problems. Utility Model Content

[0005] This utility model patent aims to provide a SiC trench MOSFET without bipolar degradation effect and low specific on-resistance (Ron, sp) due to the reduced device reliability and higher specific on-resistance (Ron, sp) caused by bipolar degradation in the reverse conduction state of the existing SiC trench MOSFET devices.

[0006] In order to solve the above technical problems, the utility model is realized by the following technical solutions:

[0007] A SiC trench MOSFET device comprises an N-type doped epitaxial layer, wherein two gate trenches are etched on the epitaxial layer, a first P+ region is provided at the bottom of the gate trench, a first P well region and a first N+ region are provided on the surface of the first P+ region, the gate trench is filled with first polysilicon, and a silicon dioxide layer is provided between the gate trench and the filled first polysilicon;

[0008] The epitaxial layer has a second P-well region on the outer sides corresponding to the two gate trenches, and the surface of the second P-well region has a second N+ region and a second P+ region, and source metal is grown in the second N+ region and the second P+ region;

[0009] A trench is etched between the epitaxial layer corresponding to the two gate trenches and filled with the second polysilicon. The first polysilicon and the second polysilicon are grown with gate metal.

[0010] The thickness of the silicon dioxide layer near the center of the epitaxial layer of the two gate trenches is higher than that of the silicon dioxide layer far from the center of the device, and the ratio of the silicon dioxide layer near the center line of the epitaxial layer to the silicon dioxide layer far from the center line of the epitaxial layer is 3:1. The thickness of the silicon dioxide layer near the center line of the epitaxial layer is 150nm, and the thickness of the silicon dioxide layer far from the center line of the epitaxial layer is 50nm.

[0011] The trench depth is higher than the two gate trenches, the bottom of the trench is 0.35-0.45 microns away from the bottom of the gate trench, and is located between the silicon dioxide layers on the side walls of the two gate trenches. The bottom of the first P+ well region is stepped and used as a shielding layer to reduce the electric field strength at the corner of the trench and reduce the on-resistance.

[0012] The utility model aims to provide a SiC trench MOSFET without bipolar degeneration effect and low specific on-resistance (Ron,sp), wherein the SiC trench MOSFET comprises an epitaxial layer, on which are two gate trenches and a middle trench, wherein the middle trench is located between the two gate trenches, and the gate trench and the middle trench are both filled with polysilicon.

[0013] The oxide dielectric layer is silicon dioxide and is located on the sidewall and bottom of the gate trench.

[0014] The thickness of the silicon dioxide layer near the center of the two gate trenches is higher than that away from the center of the device. The thickness of silicon dioxide between the gate trench and the middle trench is thicker, and the thickness of silicon dioxide at the bottom of the gate trench and the other sidewall away from the middle trench is the same and thinner, with a thickness ratio of 3:1. The thickness of the silicon dioxide layer near the center of the device is 150nm, and the thickness of the silicon dioxide layer away from the center of the device is 50nm.

[0015] A middle trench with a depth higher than the gate trench is formed between the two gate trenches. The bottom of the middle trench is about 0.35-0.45 microns away from the bottom of the gate trench. It is sandwiched between the silicon dioxide layers on the side walls of the two gate trenches. The above three trenches are all filled with polysilicon.

[0016] There are N+ region and P-well region at the bottom of the gate trench, and there is a stepped P+ shielding layer at the bottom of the N+ region and the P-well region. The sides of the N+ region and the P+ shielding layer are middle trenches filled with polysilicon.

[0017] The above-mentioned trenches filled with polysilicon are all connected to the gate metal, and the surfaces of the two N+ regions and the P+ region on the side of the trench are connected to the source metal.

[0018] The N+ doping concentration at the bottom of the gate trench is the same as the doping concentration of the N+ source region on the side wall of the trench, and the thickness is the same; the P-well region at the bottom of the gate trench has a higher doping concentration than the P-well region on the side wall of the trench, and the doping concentration ratio is 3:1; there is a stepped P+ shielding layer at the bottom of the N+ region and the P-well region to reduce the electric field strength at the corner of the trench and reduce the on-resistance.

[0019] Particularly, the doping concentration of the P-well region at the bottom of the gate trench is lower than that of the P-well region on the sidewall of the gate trench, and the ratio of the doping concentration of the P-well region at the bottom of the gate trench to the doping concentration of the P-well region 202 on the sidewall of the gate trench is 0.9:1.

[0020] The utility model has the following beneficial effects: the utility model patent sets an additional N+ source region at the bottom of the groove, improves the channel density, significantly reduces the device's specific on-resistance (Ron, sp), thereby reducing the chip area and reducing production costs; at the same time, an integrated JFET device is introduced through the two P+ regions at the bottom of the gate groove and the polysilicon filled in the middle groove, eliminating the bipolar degradation effect of the body diode when reversely turned on, greatly improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for describing the embodiments are briefly introduced below.

[0022] Figure 1 : A cross-sectional structural diagram of a SiC trench MOSFET device of the present invention.

[0023] Figures 2 to 10 : A diagram showing the stages of the SiC trench MOSFET device preparation process of the present invention.

[0024] Fig.11 : Comparison of on-state output characteristic curves of existing devices.

[0025] Fig.12 : Comparison of reverse conduction characteristic curves of existing devices.

[0026] Fig.13 : Cross-sectional structure diagram of a traditional SiC trench MOSFET device.

[0027] In the accompanying drawings, the components represented by each reference numeral are listed as follows: epitaxial layer 201, well region 202, N+ source region 204, P+ region 203, gate trench 205, N+ region 208, well region 210, P+ shielding layer 209, intermediate trench 214, hard mask 206, silicon dioxide 211, hard mask 213, source metal 216, and gate metal 217. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0029] Figure 1 The cross-sectional structure diagram of the SiC trench MOSFET device of the utility model is shown in the figure. As shown in the figure, the SiC trench MOSFET device of the utility model includes an epitaxial layer 201, the epitaxial layer 201 is of the first doping type, and the epitaxial layer 201 is of the N-type doping type. A well region 202 is provided above the epitaxial layer 201, and the well region 202 is of the second doping type, which is opposite to the first doping type, and the well region 202 is a P-type doping region (P-Body) of the P-type doping type. There are an active region 204 and a P+ region 203 on the well region 202, the source region 204 is of the first doping type, and the P+ region 203 is of the second doping type.

[0030] There are two gate trenches 205 on the epitaxial layer 201. The two gate trenches 205 preferably pass through the source region 204 and the well region 202 from top to bottom and extend into the epitaxial layer 201. The bottom of the two gate trenches 205 connects with the N+ region 208 and the well region 210 from the middle of the device to both sides. The bottom of the N+ region 208 and the well region 210 are wrapped by the P+ shielding layer 209. The two gate trenches 205 are filled with polysilicon.

[0031] A trench 214 is formed between the two gate trenches 205 . The trench 214 is filled with polysilicon. The polysilicon filled in the trench 214 is connected to the N+ region 208 and the P+ shielding layer 209 in sequence from top to bottom.

[0032] Specifically, in the utility model patent, the preparation process of SiC trench MOSFET is as follows:

[0033] Step 1 Figure 2 As shown: ion implantation and high temperature annealing to activate ions are performed on the epitaxial layer 201 in the P well region 202, the N+ region 204 and the P+ region 203;

[0034] Step 2 Figure 3 As shown: a hard mask (HM) 206 is grown on the upper part of the N+ source region 204 and the P+ region 203, and two gate trenches 205 are etched;

[0035] Step 3 Figure 4 As shown: ion implantation and high temperature annealing to activate ions are performed in the P well region 210, N+ region 208 and P+ region 209 at the bottom of the etched gate trench;

[0036] Step 4 Figure 5As shown: the hard mask (HardMask) 206 is removed and the oxide silicon dioxide 211 is grown in the gate trench 205;

[0037] Step 5 Figure 6 As shown: the gate trench 205 is filled with polysilicon (Poly);

[0038] Step 6 Figure 7 As shown: a hard mask 213 is grown on the upper part of the polysilicon of the N+ source region 204, the P+ region 203 and the gate trench 205, and the middle trench 214 is etched;

[0039] Step 7 Figure 8 As shown: the middle trench 214 is filled with polysilicon (Poly);

[0040] Step 8 Fig. 9 As shown: the hard mask (Hard Mask) 213 is removed;

[0041] Step 9 Fig.10 As shown: a source metal 216 is grown on the N+ source region 204 and the P+ region 203 , and a gate metal 217 is grown on the polysilicon in the gate trench 205 and the polysilicon in the middle trench 214 .

[0042] Through the above process flow, taking 1200V SiC MOSFET as an example, the epitaxial layer 201 preferably has a doping concentration of 5.0E15, the well region 202 (P-Body, aluminum) has an implantation concentration of 1.0E17, the opening width of the gate trench 205 is 0.75um, the depth of the gate trench 205 is 1.65um, the silicon dioxide thickness between the gate trench 205 and the middle trench 214 is 150nm, the silicon dioxide thickness of the bottom and sidewall of the gate trench connected to the well region is 50nm, the depth of the middle trench 214 is 2.05um, and the width is 0.65um. The doping concentration of the P+ shielding layer 209 (aluminum) at the bottom of the gate trench is 2E18, the doping concentration of the N+ region 208 is 1E19, and the doping concentration of the P well region 210 is 3E17.

[0043] It can be seen that the SiC MOSFET device of the present invention introduces an intermediate trench 214 between the two gate trenches 205, and directly contacts the SiC epitaxial layer 201 by filling polysilicon in the intermediate trench. In addition, at the bottom of the gate trench 205, the P+ shielding layer 209 on the sidewall of the intermediate trench 214 can form a JFET device together with the polysilicon of the intermediate trench 214; the N+ region 208 at the bottom of the trench can be used as a newly introduced source region of the device, and can form a channel with the P-well region when inverted, thereby increasing the channel density of the device and improving the characteristic on-resistance (Ron, sp) of the device. Fig.11 The on-state output characteristic curve comparison diagram of the utility model device and the existing device is as follows: Figure 4 It can be seen that the N+ source region 208 introduced at the bottom of the gate trench 205 of the utility model patent does improve the channel density of the device, reduces the characteristic on-resistance (Ron, sp) of the device by 24%, and greatly improves the FOM value of the device. Fig.12 The reverse conduction characteristic curve comparison diagram of the device of the utility model and the existing device shows that the integrated JFET device introduced in the middle trench 214 reduces the reverse turn-on voltage of the SiC MOSFET from 2.15V to 1.76V, indicating that the integrated JFET device is turned on earlier than the body diode of the SiC MOSFET, and the integrated JFET device replaces the body diode to act as a reverse freewheeling device, and the minority carrier conduction of the body diode is changed to the majority carrier conduction of the JFET device, eliminating the bipolar degradation occurring when the minority carrier conduction recombination occurs, thereby greatly improving the reliability of the device.

[0044] This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can better understand and utilize the present invention.

Claims

1. A SiC trench MOSFET device, characterized in that: The invention comprises an N-type doped epitaxial layer (201), wherein the epitaxial layer (201) is etched with two gate trenches (205), the bottom of the gate trench (205) has a first P+ region (209), the surface of the first P+ region (209) has a first P well region (210) and a first N+ region (208), the gate trench (205) is filled with first polysilicon, and a silicon dioxide layer (211) is provided between the gate trench (205) and the filled first polysilicon; The outer sides of the epitaxial layer (201) corresponding to the two gate trenches (205) are provided with a second P-well region (202), the surface of the second P-well region (202) is provided with a second N+ region (204) and a second P+ region (203), and the second N+ region (204) and the second P+ region (203) are grown with an active metal (216); A groove (214) is etched between the epitaxial layer (201) and corresponds to two gate grooves (205), and is filled with second polysilicon, and gate metal (217) is grown on the first polysilicon and the second polysilicon.

2. A SiC trench MOSFET device according to claim 1, characterized in that: The thickness of the silicon dioxide layer near the center of the epitaxial layer of the two gate trenches (205) is higher than that of the silicon dioxide layer far from the center of the device, and the thickness ratio of the silicon dioxide layer near the center line of the epitaxial layer to the silicon dioxide layer far from the center line of the epitaxial layer is 3:

1.

3. A SiC trench MOSFET device according to claim 2, characterized in that: The thickness of the silicon dioxide layer close to the center line of the epitaxial layer is 150 nm, and the thickness of the silicon dioxide layer far from the center line of the epitaxial layer is 50 nm.

4. A SiC trench MOSFET device according to claim 1, characterized in that: The depth of the trench (214) is higher than that of the two gate trenches (205); the bottom of the trench (214) is 0.35-0.45 microns away from the bottom of the gate trench (205), and is located between the silicon dioxide layers (211) on the side walls of the two gate trenches (205).

5. The SiC trench MOSFET device according to claim 1, characterized in that: The bottom of the first P+ well region (209) is stepped and serves as a shielding layer to reduce the electric field strength at the corner of the trench and lower the on-resistance.

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