Flip-chip integrated circuit chip and light-emitting device

Abstract

The utility model discloses a flip-chip integrated circuit chip and a light-emitting device. The flip chip type integrated circuit chip comprises a chip body, a plurality of metal connecting pads, a circuit redistribution layer and a plurality of flip chip connecting pads. The plurality of metal pads are disposed on a surface of the chip body. The circuit redistribution layer is generated on the surface of the chip body, and a plurality of metal connecting pads are embedded in the circuit redistribution layer. The plurality of flip chip pads are disposed on the circuit redistribution layer and electrically coupled to the plurality of metal pads through the circuit redistribution layer, respectively. A layout distribution of the plurality of flip chip pads is more uniform than a layout distribution of the plurality of metal pads. A plurality of projection areas are respectively generated by orthographic projections of the plurality of flip chip connecting pads towards the surface of the chip body, and the positions of the projection areas are not in a central area of the layout.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing, and in particular to a flip-chip integrated circuit chip and a light-emitting device. Background Technology

[0002] Existing integrated circuit chips used to drive LED chips have multiple wire bonding pads that are only applicable to wire bonding. Therefore, the architecture of any light-emitting device using existing integrated circuit chips will be affected by the multiple wire bonding pads and will be difficult to improve further.

[0003] Therefore, the inventor believed that the above-mentioned defects could be improved, and thus devoted himself to research and applied scientific principles, and finally proposed this application with a reasonable design that effectively improves the above-mentioned defects. Utility Model Content

[0004] The technical problem to be solved by this application is to provide a flip-chip integrated circuit chip and a light-emitting device to address the shortcomings of the prior art.

[0005] This application discloses a flip-chip integrated circuit chip, comprising: a chip body; a plurality of metal pads disposed on a surface of the chip body; a circuit redistribution layer formed on the surface of the chip body and embedding the plurality of metal pads therein; and a plurality of flip-chip pads disposed on the circuit redistribution layer and electrically coupled to the plurality of metal pads respectively through the circuit redistribution layer; wherein, the layout distribution of the plurality of flip-chip pads is more even than the layout distribution of the plurality of metal pads, and the plurality of flip-chip pads project onto the surface of the chip body to generate a plurality of projection areas, the position of each projection area being outside the central area of ​​the layout distribution.

[0006] Optionally, the area of ​​the central region is equal to or smaller than any of the flip-chip pads.

[0007] Optionally, the edges of the plurality of metal pads define a layout boundary, each side of which sits on at least two of the projected areas.

[0008] Optionally, at least a portion of the plurality of projection regions are symmetrically arranged along at least one axis of symmetry.

[0009] This application also discloses a light-emitting device, comprising: a substrate; a flip-chip integrated circuit chip as described above; and at least one flip-chip light-emitting diode chip disposed at a distance from the flip-chip integrated circuit chip, wherein the at least one flip-chip light-emitting diode chip is electrically coupled to the flip-chip integrated circuit chip through the substrate.

[0010] Optionally, the substrate includes: a first layer for carrying the flip-chip integrated circuit chip and the at least one flip-chip light-emitting diode chip; a second layer disposed on one side of the first layer, the second layer including an upper insulating layer, a plurality of first conductive pads, and a plurality of first conductive pillars, the plurality of first conductive pads being disposed on the upper insulating layer and electrically coupled to the plurality of flip-chip pads through the plurality of first conductive pillars; a third layer disposed on the side of the second layer away from the first layer, the third layer including a lower insulating layer, a plurality of second conductive pads, and a plurality of second conductive pillars, the plurality of second conductive pads being disposed on the lower insulating layer and electrically coupled to the plurality of first conductive pads through the plurality of second conductive pillars; and a fourth layer disposed on the side of the third layer away from the first layer, the fourth layer including a plurality of outer pads, the plurality of outer pads being electrically coupled to the plurality of second conductive pads.

[0011] Optionally, there is a first predetermined interval between any two adjacent first conductive pads and between any two adjacent second conductive pads, and there is a second predetermined interval between the first conductive pad near one edge of the upper insulating layer and the edge of the upper insulating layer, and between the second conductive pad near one edge of the lower insulating layer and the edge of the lower insulating layer, wherein the first predetermined interval and the second predetermined interval are 60 micrometers.

[0012] Optionally, the at least one flip-chip LED chip has a red LED chip, a green LED chip, and a blue LED chip, wherein the major axes of the red LED chip, the green LED chip, and the blue LED chip are parallel to each other, and the red LED chip, the green LED chip, and the blue LED chip are arranged in a triangular configuration.

[0013] Optionally, the at least one flip-chip LED chip has a red LED chip, a green LED chip, a blue LED chip, and a white LED chip. The short axis extension lines of the red LED chip, the green LED chip, and the blue LED chip can overlap each other, and the white LED chip is located on a common side of the red LED chip, the green LED chip, and the blue LED chip.

[0014] Beneficial effects of utility model

[0015] The flip-chip integrated circuit chip and light-emitting device disclosed in this application can provide ideal product reliability while miniaturizing through the design of "a layout distribution of multiple flip-chip pads is more average than the layout distribution of multiple metal pads" and "multiple projection areas are generated by the orthographic projection of multiple flip-chip pads toward the surface of the chip body, and the position of each projection area is not in a central area of ​​the layout distribution".

[0016] To further understand the features and technical content of this application, please refer to the following detailed description and drawings of this application. However, these descriptions and drawings are only used to illustrate this application and are not intended to limit the scope of protection of this application in any way. Attached Figure Description

[0017] Figure 1 This is a perspective view of the light-emitting device according to the first embodiment of this application.

[0018] Figure 2 for Figure 1 A schematic diagram of its breakdown.

[0019] Figure 3 for Figure 2 An exploded view of a flip-chip integrated circuit chip.

[0020] Figure 4 for Figure 2 A schematic cross-sectional view along section line IV-IV.

[0021] Figure 5 for Figure 2 A bottom view of a flip-chip integrated circuit chip (solder resist layer omitted).

[0022] Figure 6 for Figure 2 An exploded view of the substrate.

[0023] Figure 7 for Figure 1 A schematic cross-sectional view along section line VII-VII.

[0024] Figure 8 This is a three-dimensional schematic diagram of the light-emitting device according to Embodiment 2 of this application.

[0025] Figure 9 for Figure 8 A cross-sectional view along section line IX-IX.

[0026] Figure 10 This is a three-dimensional schematic diagram of the light-emitting device according to Embodiment 3 of this application.

[0027] Figure 11 for Figure 10A cross-sectional view along section line XI-XI.

[0028] Figure 12 This is a three-dimensional schematic diagram of the light-emitting component according to Embodiment 4 of this application.

[0029] Figure 13 for Figure 12 A schematic cross-sectional view along section line XIII-XIII.

[0030] Figure 14 This is a top view of the light-emitting device (excluding the wall) according to the fifth embodiment of this application.

[0031] Figure 15 for Figure 14 A magnified view of a portion of the image.

[0032] Figure 16 This is a top view of the light-emitting device (excluding the wall) according to the fifth embodiment of this application in another state.

[0033] Figure 17 for Figure 16 A magnified view of a portion of the image.

[0034] Figure 18 This is a cross-sectional schematic diagram of the light-emitting device according to the sixth embodiment of this application.

[0035] Figure 19 This is a schematic diagram of the process of manufacturing a light-emitting device according to the sixth embodiment of this application.

[0036] Figure 20 for Figure 19 The manufacturing method is illustrated in step S101.

[0037] Figure 21 for Figure 19 The manufacturing method is illustrated in step S103.

[0038] Figure 22 for Figure 19 The manufacturing method is illustrated in step S105.

[0039] Figure 23 for Figure 19 The manufacturing method is illustrated in step S107.

[0040] Figure 24 for Figure 19 The manufacturing method is illustrated in step S109.

[0041] Figure 25 for Figure 19 The manufacturing method is illustrated in the schematic diagrams of steps S111 and S113.

[0042] Figure 26 for Figure 19 The manufacturing method is illustrated in step S115.

[0043] Figure 27 This is a cross-sectional schematic diagram of the light-emitting device according to the seventh embodiment of this application.

[0044] Figure 28 This is a schematic diagram of the manufacturing process of the light-emitting device according to the seventh embodiment of this application.

[0045] Figure 29 for Figure 28 The manufacturing method is illustrated in step S201.

[0046] Figure 30 for Figure 28 The manufacturing method is illustrated in step S203.

[0047] Figure 31 for Figure 28 The manufacturing method is illustrated in step S205.

[0048] Figure 32 for Figure 28 The manufacturing method is illustrated in step S207.

[0049] Figure 33 This is a schematic diagram illustrating the process of another manufacturing method of the light-emitting device according to the seventh embodiment of this application.

[0050] Figure 34 for Figure 33 The manufacturing method is illustrated in step S301.

[0051] Figure 35 for Figure 33 The manufacturing method is illustrated in step S303.

[0052] Figure 36 for Figure 33 The manufacturing method is illustrated in step S305.

[0053] Figure 37 for Figure 33 The manufacturing method is illustrated in step S307.

[0054] Figure 38 for Figure 33 The manufacturing method is illustrated in step S309.

[0055] Figure 39 for Figure 33 The manufacturing method is illustrated in step S311. Detailed Implementation

[0056] The following specific embodiments illustrate the implementation methods disclosed in this application. Those skilled in the art can understand the advantages and effects of this application from the content disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this application. Furthermore, the accompanying drawings of this application are for simple illustration only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this application in detail, but the disclosed content is not intended to limit the scope of protection of this application.

[0057] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein may, depending on the context, include any combination of one or more of the related listed items. Moreover, the term "electrical coupling" as used herein refers to either "indirect electrical connection" or "direct electrical connection."

[0058] First Embodiment

[0059] Please see Figures 1 to 7 As shown, this is the first embodiment of this application. Figure 1 and Figure 2 As shown, this embodiment discloses a light-emitting device 100 or a light-emitting diode (LED) package structure 100, comprising a flip-chip integrated circuit (FCIC) chip 1, at least one flip-chip LED chip 2, a substrate 3, a surrounding wall 4, and a light-transmitting package 5. The FCIC chip 1 and the at least one flip-chip LED chip 2 are mounted on the substrate 3, for example, by using a tin-plating design with openings in a steel plate to apply solder paste to the substrate 3. Therefore, the FCIC chip 1 and the at least one flip-chip LED chip 2 can be soldered onto the substrate 3 using solder paste. This application reduces the overall thickness of the light-emitting device 100 by replacing solder balls / solder bumps with tin plating. The surrounding wall 4 is formed on the substrate 3 and surrounds the outside of the FCIC chip 1 and the at least one flip-chip LED chip 2, while the light-transmitting package 5 is disposed within the surrounding wall 4 and formed on the substrate 3 to embed the FCIC chip 1 and the at least one flip-chip LED chip 2 within it.

[0060] It should be noted that although the flip-chip integrated circuit chip 1 is described in this embodiment as being used in conjunction with the aforementioned components, this application is not limited thereto. For example, in other embodiments not illustrated in this application, the flip-chip integrated circuit chip 1 can be used independently (e.g., for sale) or in conjunction with other components. The structure and connection relationship of each component of the light-emitting device 100 will be described below. Furthermore, for ease of explanation, the number of at least one flip-chip light-emitting diode chip 2 is described as multiple, but in practical applications, the number of at least one flip-chip light-emitting diode chip 2 can be adjusted to one according to the designer's needs.

[0061] like Figures 3 to 5 As shown, the flip-chip integrated circuit chip 1 includes a chip body 11, a plurality of metal pads 12 electrically coupled to the chip body 11, a redistribution layer (RDL) 13 connected to the plurality of metal pads 12, a metal layer 14 connected to the redistribution layer 13, and a solder resist layer 15 covering the metal layer 14. The solder resist layer 15 has a plurality of openings so that the metal layer 14 defines a plurality of flip-chip pads 141 exposed outside the solder resist layer from the plurality of openings, and the flip-chip integrated circuit chip 1 is bonded to the substrate 3 through the plurality of flip-chip pads 141.

[0062] The chip body 11 functions (e.g., driving) to correspond to multiple flip-chip LED chips 2, and multiple metal pads 12 are disposed on one surface 111 of the chip body 11 (e.g., ...). Figure 3 The chip body 11 (bottom surface) has a redistribution layer 13 formed on the surface 111 of the chip body 11, and a plurality of metal pads 12 are embedded therein. A plurality of flip-chip pads 141 are disposed on the redistribution layer 13 and electrically coupled to the plurality of metal pads 12 through the redistribution layer 13. For example, the metal pad 12 can be an aluminum pad, suitable for wire bonding; that is, the metal pad 12 can serve as a wire bonding pad. The metal pad 12 may also include an alloy layer, such as gold or nickel-gold, which may be further disposed on the aluminum pad.

[0063] Furthermore, the multiple metal pads 12 applicable only to the wire bonding process can be extended and arranged through the circuit redistribution layer 13 to form multiple flip-chip pads 141 suitable for the flip-chip process. For ease of understanding, the circuit redistribution layer 13 is described in this embodiment with the following structure, but the specific structure of the circuit redistribution layer 13 can be adjusted and varied according to design requirements and is not limited to the structure described in this embodiment.

[0064] The circuit redistribution layer 13 has a multi-layer structure, comprising at least a first polymer layer 131, a second polymer layer 133, and a circuit extension layer 132. The first polymer layer 131 is formed on the surface 111 and disposed around the plurality of metal pads 12. In this embodiment, the first polymer layer 131 is coplanar with the plurality of metal pads 12 and covers the entire surface 111.

[0065] The second polymer layer 133 is disposed on the first polymer layer 131. The circuit extension layer 132 is disposed on the first polymer layer 131 and the plurality of metal pads 12 and is electrically coupled to the plurality of metal pads 12. The second polymer layer 133 is disposed around the circuit extension layer 132, and the circuit extension layer 132 and the second polymer layer 133 are coplanar. The metal layer 14 is disposed on the circuit extension layer 132 and protrudes from the surfaces of the circuit extension layer 132 and the second polymer layer 133.

[0066] Furthermore, the circuit extension layer 132 can be made of a material (e.g., silver paste) that can be stably and securely connected to the plurality of metal pads 12, while the metal layer 14 can be made of a metal / alloy material that can be solder-resistant and can stably connect to the circuit extension layer 132, thereby facilitating the use of the plurality of flip-chip pads 141 in flip-chip processes. The metal layer 14 can be made of a solder-resistant metal or alloy material, such as gold or nickel-gold.

[0067] The solder resist layer 15 is disposed on the metal layer 14 and exposes a plurality of flip-chip pads 141 through openings. That is, a portion of the metal layer 14 is embedded within the solder resist layer 15.

[0068] More specifically, the flip-chip integrated circuit chip 1 can be adjusted to face multiple surfaces suitable for the flip-chip process through the circuit redistribution layer 13. For example, in this embodiment, the material of any one of the flip-chip pads 141 (e.g., gold or nickel-gold) is different from the material of any one of the metal pads 12 (e.g., aluminum), and the areas of the multiple flip-chip pads 141 are all the same. The area of ​​any one of the flip-chip pads 141 is larger than the area of ​​the metal pad 12 to which it is electrically coupled, thereby facilitating the stable connection of any one of the flip-chip pads 141 in the flip-chip process.

[0069] Furthermore, the flip-chip integrated circuit chip 1 can also achieve an even distribution of multiple flip-chip pads 141 corresponding to the surface 111 through the circuit redistribution layer 13. That is, the layout distribution of the multiple flip-chip pads 141 is more even than the layout distribution of the multiple metal pads 12, which is beneficial for application in flip-chip manufacturing processes. For the sake of illustration, a layout boundary B is defined on the edge of the multiple metal pads 12, and the multiple metal pads 12 are located within the layout boundary B; wherein, the layout boundary B is described as a square in this embodiment, but this application is not limited thereto.

[0070] Furthermore, the plurality of flip-chip pads 141 are located within the layout boundary B, and at least one of the flip-chip pads 141 is spaced apart from the layout boundary B. In this embodiment, a portion of the plurality of flip-chip pads 141 (e.g., located within) Figure 5 The partial edges of the two flip-chip pads 141 (lower left and upper right) fall on the layout boundary B, while the remaining portions of the plurality of flip-chip pads 141 are spaced apart from the layout boundary B. Accordingly, the flip-chip integrated circuit chip 1 can be provided with the circuit redistribution layer 13 so that at least one flip-chip pad 141 moves toward the inside of the layout boundary B, thereby facilitating the even distribution of the plurality of flip-chip pads 141 corresponding to the surface 111.

[0071] Furthermore, to illustrate the degree to which the plurality of flip-chip pads 141 are evenly distributed on the surface 111, the layout boundary B may further define a 9-square area J, and the nine empty spaces in the 9-square area J have substantially the same area.

[0072] The number of empty spaces in the 3x3 grid area J for the plurality of metal pads 12 is less than the number of flip-chip pads 141. That is, at least one empty space in the 3x3 grid area J corresponds to at least two metal pads 12, so the distribution of the plurality of flip-chip pads 141 appears relatively dense.

[0073] Furthermore, the projection area formed by the orthographic projection of the plurality of flip-chip pads 141 toward the surface 111 of the chip body 11 has the same number of empty spaces in the 3x3 grid area J as the plurality of flip-chip pads 141. That is, any empty space in the 3x3 grid area J corresponds to at most one flip-chip pad 141, so the distribution of the plurality of flip-chip pads 141 appears relatively even, which is beneficial for even solder application and less rotation during the flip-chip process, thereby ensuring stable connection.

[0074] In other words, the number of empty spaces in the grid area J (e.g., seven in this embodiment) generated by the orthographic projection of the plurality of flip-chip pads 141 onto the surface 111 of the chip body 11 is greater than the number of empty spaces in the grid area J (e.g., five in this embodiment) of the plurality of metal pads 12.

[0075] Furthermore, the projection area generated by the orthographic projection of the plurality of flip-chip pads 141 toward the surface 111 of the chip body 11 does not cover any of the metal pads 12, thereby avoiding crosstalk between any of the flip-chip pads 141 and the corresponding metal pads 12 due to the formation of the circuit redistribution layer 13 and thus affecting the yield.

[0076] like Figure 2 , Figure 6 ,and Figure 7 As shown, the substrate 3 supports the flip-chip integrated circuit chip 1 and a plurality of flip-chip light-emitting diode chips 2, and the flip-chip integrated circuit chip 1 and the plurality of flip-chip light-emitting diode chips 2 are arranged at intervals. Furthermore, the substrate 3 is electrically coupled to a plurality of flip-chip pads 141 of the flip-chip integrated circuit chip 1 and a plurality of electrodes 21 of the plurality of flip-chip light-emitting diode chips 2.

[0077] Furthermore, in order to enable the substrate 3 to accurately connect the plurality of flip-chip pads 141 of the flip-chip integrated circuit chip 1 and the plurality of electrodes 21 of the flip-chip light-emitting diode chips 2 in the flip-chip process, the substrate 3 is described in this embodiment with the following structure. However, the specific structure of the substrate 3 can be adjusted and changed according to design requirements and is not limited to the embodiment described herein.

[0078] The substrate 3 includes a first insulating layer 31, a first metal layer 32 and a second insulating layer 33 located on opposite sides of the first insulating layer 31, and a second metal layer 34 and a third metal layer 35 formed on the second insulating layer 33.

[0079] In this embodiment, the first insulating layer 31 is stepped and has a lower step portion 311 and two upper step portions 312 formed at intervals on the lower step portion 311. The first metal layer 32 is formed on the two upper step portions 312 of the first insulating layer 31. In this embodiment, the first metal layer 32 includes an integrated circuit chip die-bonding region 321 and a light-emitting diode chip die-bonding region 322, which are respectively located on the two upper step portions 312.

[0080] The second insulating layer 33 is connected to the lower step portion 311 of the first insulating layer 31. The second metal layer 34 is embedded within the first insulating layer 31 and the second insulating layer 33, while the third metal layer 35 is located on the side of the second insulating layer 33 away from the first insulating layer 31. The second metal layer 34 includes multiple extending leads 341 spanning the two upper steps 312 and multiple conductive posts 342 connected to the multiple extending leads 341. The second metal layer 34 is connected to the die-bonding region 322 of the LED chip, the die-bonding region 321 of the integrated circuit chip, and the third metal layer 35 respectively through the multiple conductive posts 342, so that the second metal layer 34 and the third metal layer 35 are electrically coupled to each other, and the die-bonding region 322 of the LED chip is electrically coupled to the die-bonding region 321 of the integrated circuit chip through the second metal layer 34.

[0081] Furthermore, in this embodiment, the substrate 3 may further include an upper solder resist layer 36 and a lower solder resist layer 37 located on opposite sides. The upper solder resist layer 36 is formed on the first insulating layer 31 (the two upper steps 312), and the upper solder resist layer 36 has a plurality of openings 361 to expose the die-bonding region 321 of the integrated circuit chip and the die-bonding region 322 of the light-emitting diode chip. In this embodiment, the upper solder resist layer 36 includes a light-emitting diode chip solder resist region 363 and an integrated circuit chip solder resist region 362, which are separated from each other (disposed on the two upper steps 312) and each has a plurality of openings 361. In addition, the lower solder resist layer 37 is disposed on one side of the second insulating layer 33 and adjacent to the third metal layer 35.

[0082] The enclosure 4 is disposed on the substrate 3 and forms a first accommodating space 41 corresponding to the solder resist area 362 of the integrated circuit chip and a second accommodating space 42 corresponding to the solder resist area 363 of the light-emitting diode chip. The flip-chip integrated circuit chip 1 is located in the first accommodating space 41, while a plurality of flip-chip light-emitting diode chips 2 are located in the second accommodating space 42.

[0083] The light-transparent package 5 is disposed on the substrate 3 and fills the first accommodating space 41 and the second accommodating space 42, so that the flip-chip integrated circuit chip 1 and the plurality of flip-chip light-emitting diode chips 2 are embedded therein, but this application is not limited thereto. For example, in other embodiments not illustrated in this application, the light-transparent package 5 may only fill the second accommodating space 42, so that the plurality of flip-chip light-emitting diode chips 2 are embedded therein. Accordingly, in this application, the light-transparent package 5 at least fills the second accommodating space 42.

[0084] More specifically, in this embodiment, the light-transmitting encapsulation body 5 includes a light-emitting surface 51, which is parallel to the substrate 3 and faces away from the substrate 3. In this embodiment, the light-emitting surface 51 is coplanar with the top surface of the enclosure 4, but this application is not limited thereto.

[0085] Additionally, the substrate 3 can also be understood as a multilayer board structure. Specifically, the substrate 3 includes a first layer, a second layer disposed on one side of the first layer, a third layer disposed on the side of the second layer away from the first layer, and a fourth layer disposed on the side of the third layer away from the first layer.

[0086] The first layer carries the flip-chip integrated circuit chip 1 and the at least one flip-chip light-emitting diode chip 2. The second layer includes an upper insulating layer (e.g., the upper solder resist layer 36), a plurality of first conductive pads, and a plurality of first conductive pillars (e.g., the first metal layer 32). The plurality of first conductive pads are disposed on the upper insulating layer, and the plurality of first conductive pads are electrically coupled to the plurality of flip-chip pads through the plurality of first conductive pillars.

[0087] Furthermore, the third layer includes a lower insulating layer (e.g., the second insulating layer 33), a plurality of second conductive pads, and a plurality of second conductive posts (e.g., the second metal layer 34). The plurality of second conductive pads are disposed on the lower insulating layer, and are electrically coupled to the plurality of first conductive pads via the plurality of second conductive posts. The fourth layer includes a plurality of outer pads (e.g., the third metal layer 35), which are electrically coupled to the plurality of second conductive pads.

[0088] Second Embodiment

[0089] Please see Figure 8 and Figure 9As shown, this is the second embodiment of this application. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the first embodiment described above are explained as follows:

[0090] In this embodiment, the light-emitting surface 51 is perpendicular to the substrate 3 and faces away from the flip-chip integrated circuit chip 1. The light-emitting surface 51 is not located on the top surface of the light-transmitting package 5; that is, the light-emitting surface 51 is located on the side of the light-emitting device 100 and is coplanar with the side end face 44 of the enclosure 4. Furthermore, the first accommodating space 41 is a sealed space enclosed within the enclosure 4; that is, the flip-chip integrated circuit chip 1 and the corresponding portion of the light-transmitting package 5 located within the first accommodating space 41 are embedded within the enclosure 4.

[0091] Third Embodiment

[0092] Please see Figure 10 and Figure 11 As shown, this is the third embodiment of this application. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the first embodiment described above are explained as follows:

[0093] In this embodiment, the flip-chip integrated circuit chip 1 is encapsulated and embedded within the enclosure 4; that is, the space occupied by the flip-chip integrated circuit chip 1 is the first accommodating space 41. The enclosure 4 also forms a third accommodating space 43, and the first accommodating space 41 is located between the second accommodating space 42 and the third accommodating space 43. The light-emitting device 100 includes a light sensor 6 located within the third accommodating space 43, and the light-transmitting package 5 fills the second accommodating space 42 and the third accommodating space 43, so that multiple flip-chip light-emitting diode chips 2 and the light sensor 6 are embedded within them. The multiple flip-chip light-emitting diode chips 2 may include two green light-emitting diode chips and one infrared light chip, but are not limited thereto.

[0094] More specifically, in this embodiment, the light-transmitting package 5 includes a light-emitting surface 51 corresponding to the plurality of flip-chip LED chips 2 and a light-incident surface 52 corresponding to the photosensor 6. Both the light-emitting surface 51 and the light-incident surface 52 are substantially parallel to the substrate 3 and face away from the substrate 3. In this embodiment, the light-emitting surface 51 and the light-incident surface 52 are coplanar on the top surface of the enclosure 4, but this application is not limited thereto. The light-emitting device 100 of this embodiment integrates a flip-chip integrated circuit chip 1 (e.g., an analog front-end chip), a light source, and a photosensor 6, making it more suitable for thinner and lighter wearable devices, providing a LED package structure with the smallest area and thinnest thickness.

[0095] Fourth embodiment

[0096] Please see Figure 12 and Figure 13 As shown, this is the fourth embodiment of this application. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the first embodiment described above are explained as follows:

[0097] This embodiment discloses a light-emitting component 10, which differs from the light-emitting device 100 of the first embodiment in that it does not include a substrate 3. The light-emitting component 10 includes a flip-chip integrated circuit chip 1, a plurality of flip-chip light-emitting diode chips 2 disposed at intervals from the flip-chip integrated circuit chip 1, and a light-transmitting package 5. The flip-chip integrated circuit chip 1 and the plurality of flip-chip light-emitting diode chips 2 in this embodiment are similar to those in the first embodiment described above, and will not be described in detail here. The plurality of flip-chip light-emitting diode chips 2 may be one or a combination of red light-emitting diode chips, blue light-emitting diode chips, and green light-emitting diode chips, and are not limited thereto.

[0098] In this embodiment, the light-emitting component 10 does not include the substrate 3 of the first embodiment, and the light-transmitting package 5 is a single-piece structure integrally formed and encapsulates the flip-chip integrated circuit chip 1 and the plurality of flip-chip light-emitting diode chips 2. The plurality of flip-chip pads 141 of the flip-chip integrated circuit chip 1 and the plurality of electrodes 21 of the plurality of flip-chip light-emitting diode chips 2 are exposed outside the light-transmitting package 5 for direct flip-chip mounting to a predetermined object (e.g., a circuit board or substrate 3).

[0099] Fifth embodiment

[0100] Please see Figures 14 to 17As shown, this is the fifth embodiment of this application. Since this embodiment is similar to the first embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the first embodiment described above are explained as follows:

[0101] The flip-chip integrated circuit chip 1 has a plurality of flip-chip pads (i.e., Figure 14 141A~141G, or Figure 16 141A to 141H) can be oriented toward the surface 111 of the chip body 11 (in conjunction with) Figure 4 As shown, orthographic projection generates multiple projection regions, and the positions of each projection region are not within a central region CA of the layout distribution (e.g., Figure 15 and Figure 17 (As shown).

[0102] Specifically, the edges of the plurality of metal pads 12 define a layout boundary B on the surface 111 of the chip body 11 (the layout boundary B substantially overlaps the outline of the chip body 11 in this embodiment), the layout boundary B also defines a nine-grid area, and the central area CA can be a central empty space of the nine-grid area.

[0103] For example, such as Figure 15 As shown, the plurality of flip-chip pads define a first flip-chip pad 141A, a second flip-chip pad 141B, a third flip-chip pad 141C, a fourth flip-chip pad 141D, a fifth flip-chip pad 141E, a sixth flip-chip pad 141F, and a seventh flip-chip pad 141G. The nine-square grid area has a first empty space J1, a second empty space J2, ..., a ninth empty space J9, from left to right and from top to bottom. The first flip-chip pad 141A is substantially located within the first empty space J1; the second flip-chip pad 141B is substantially located within the second empty space J2; the third flip-chip pad 141C is substantially located between the third empty space J3 and the sixth empty space J6; the fourth flip-chip pad 141D is substantially located within the fourth empty space J4; the fifth flip-chip pad 141E is substantially located between the sixth empty space J6 and the ninth empty space J9; the sixth flip-chip pad 141F is substantially located within the seventh empty space J7; and the seventh flip-chip pad 141G is substantially located within the eighth empty space J8. Notably, the central region CA within the fifth empty space J5 contains no flip-chip pads. Therefore, compared to the first embodiment, this embodiment of the light-emitting device 100 better avoids pad damage during the die bonding process, thereby ensuring product reliability.

[0104] It is worth noting that the area of ​​the central region CA is preferably equal to or smaller than any of the flip-chip pads. That is, there are no flip-chip pads within the area corresponding to the center position of the chip body 11 to avoid the possibility of the flip-chip pads being damaged by the ejector pins, while the multiple flip-chip pads are evenly distributed around the lower surface of the chip body 11 to ensure high product reliability.

[0105] Specifically, such as Figure 17 As shown, the plurality of flip-chip pads 141 define a first flip-chip pad 141A, a second flip-chip pad 141B, a third flip-chip pad 141C, a fourth flip-chip pad 141D, a fifth flip-chip pad 141E, a sixth flip-chip pad 141F, a seventh flip-chip pad 141G, and an eighth flip-chip pad 141H. The portion of the first flip-chip pad 141A generally falls within the first empty space J1; the portion of the second flip-chip pad 141B generally falls between the second empty space J2 and the fifth empty space J5; the portion of the third flip-chip pad 141C generally falls within the third empty space J3; the portion of the fourth flip-chip pad 141D generally falls within the fourth empty space J4; the portion of the fifth flip-chip pad 141E generally falls within the sixth empty space J6; the portion of the sixth flip-chip pad 141F generally falls within the seventh empty space J7; the portion of the seventh flip-chip pad 141G generally falls between the eighth empty space J8 and the fifth empty space J5; and the portion of the eighth flip-chip pad 141H generally falls within the ninth empty space J9. Although portions of the second flip-chip pad 141B and the seventh flip-chip pad 141G are located within the fifth space J5, the positions of the second flip-chip pad 141B and the seventh flip-chip pad 141G within the fifth space J5 do not fall within the central region CA (i.e., the circular region) of the fifth space J5.

[0106] In addition, such as Figure 15 and Figure 17 As shown, each side of the layout boundary B can also have at least two of the projection areas, making the positions of the multiple flip-chip pads on the flip-chip integrated circuit chip 1 more evenly distributed. In addition, taking the nine-grid area as an example, the first column, the third column, the first row, and the third row each have at least two of the projection areas (i.e., the flip-chip pads).

[0107] Accordingly, during the soldering process of the flip-chip integrated circuit chip 1, at least two flip-chip pads at each of the side positions corresponding to the layout boundary B can ensure that the stress generated by the solder on the flip-chip integrated circuit chip 1 is consistent, thereby increasing the bonding reliability between the flip-chip integrated circuit chip 1 and the substrate 3.

[0108] Optionally, in order to avoid warping or rotation of the flip-chip integrated circuit chip 1, at least a portion of the plurality of projection regions can be symmetrically arranged along at least one axis of symmetry SA.

[0109] In one embodiment, such as Figure 15 As shown, taking at least one axis of symmetry SA as one, and the axis of symmetry SA passing through the fourth space J4, the fifth space J5, the sixth space J6 and the center point of the nine-square grid area, the first flip-chip pad 141A, the fourth flip-chip pad 141D, and the sixth flip-chip pad 141F form a first symmetry group SG1, the second flip-chip pad 141B and the seventh flip-chip pad 141G form a second symmetry group SG2, and the third flip-chip pad 141C and the fifth flip-chip pad 141E form a third symmetry group SG3.

[0110] In another embodiment, such as Figure 17 As shown, with the axis of symmetry SA passing through the fourth space J4, the fifth space J5, the sixth space J6, and the center point of the nine-square grid area, the first flip-chip pad 141A, the fourth flip-chip pad 141D, and the sixth flip-chip pad 141F form a first symmetry group SG1; the second flip-chip pad 141B and the seventh flip-chip pad 141G form a second symmetry group SG2; and the third flip-chip pad 141C, the fifth flip-chip pad 141E, and the eighth flip-chip pad 141H form a third symmetry group SG3.

[0111] In principle, the flip-chip integrated circuit chip 1 may have at least one of the first symmetry group SG1, the second symmetry group SG2, and the third symmetry group SG3.

[0112] Of course, the number of the at least one axis of symmetry SA can also be multiple. For example, in another example not shown, the number of the multiple flip-chip pads 141 is eight, and the eight flip-chip pads 141 are respectively located at the center positions of the first space J1, the second space J2, the third space J3, the fourth space J4, the sixth space J6, the seventh space J7, the eighth space J8, and the ninth space J9. Accordingly, in this example, the number of the at least one axis of symmetry SA is more than four, and the flip-chip integrated circuit chip 1 has more than six symmetry groups.

[0113] Furthermore, to ensure optimal performance (e.g., uniformity) of the red, blue, and green light emitted by the light-emitting device 100 during mixing, the plurality of flip-chip LED chips can be arranged in a triangular configuration (e.g., Figure 14(As shown). Specifically, in this embodiment, the plurality of flip-chip LED chips include a red LED chip 2R, a green LED chip 2G, and a blue LED chip 2B. The major axes of the red LED chip 2R, the green LED chip 2G, and the blue LED chip 2B are parallel to each other. That is, the red LED chip 2R, the green LED chip 2G, and the blue LED chip 2B are generally arranged in a triangular configuration, but this application is not limited thereto.

[0114] For example, in another embodiment, when the light-emitting device 100 can emit red, blue, green, and white light for mixed light, the plurality of flip-chip light-emitting diode chips can be arranged in a matrix (e.g., Figure 16 (As shown). Specifically, in this embodiment, the plurality of flip-chip LED chips include a red LED chip 2R, a green LED chip 2G, a blue LED chip 2B, and a white LED chip 2W. The short-axis extension lines of the red LED chip 2R, the green LED chip 2G, and the blue LED chip 2B can overlap each other, and the white LED chip 2W is located on a common side of the red LED chip 2R, the green LED chip 2G, and the blue LED chip 2B. For example, with... Figure 16 As can be seen, the white light-emitting diode chip 2W is located to the right of the red light-emitting diode chip 2R, the green light-emitting diode chip 2G, and the blue light-emitting diode chip 2B.

[0115] Sixth Embodiment

[0116] Please see Figures 18 to 26 As shown, this is the sixth embodiment of this application. Since this embodiment is similar to the fifth embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the fifth embodiment described above are explained as follows:

[0117] like Figure 18 As shown, in this embodiment, the substrate 3 of the light-emitting device 200 has a first plate surface 38 and a second plate surface 39 that are opposite to each other, and the number of flip-chip light-emitting diode chips 2 is one. Specifically, the flip-chip integrated circuit chip 1 is disposed on the first plate surface 38, and a plurality of flip-chip light-emitting diode chips 2 are disposed on the second plate surface 39. That is, the flip-chip integrated circuit chip 1 and the flip-chip light-emitting diode chips 2 are arranged perpendicularly on the substrate 3.

[0118] Additionally, it should be noted that, within the same volume for miniaturization, the light-emitting device 200 of this embodiment, by being vertically configured, can achieve a higher efficiency compared to the light-emitting device 100 of the first embodiment, which is configured planarly (e.g., ...). Figure 7 (As shown) the flip-chip LED chip 2 provides a larger light-emitting area. In other words, under the same light emission conditions, the light-emitting device 200 of this embodiment can also save more volume compared to the light-emitting device 100 of the first embodiment.

[0119] In addition, the light-emitting device 200 in this embodiment also includes a resin layer 210, a connecting line 220, a plurality of solders 230, a solder resist coating 240, and a reflector 250.

[0120] The resin layer 210 is disposed on the first plate surface 38 and covers the flip-chip integrated circuit chip 1. The connection line 220 is formed on the first plate surface 38, the second plate surface 39, and the resin layer 210, and the flip-chip light-emitting diode chip 2 can be electrically coupled to the flip-chip integrated circuit chip 1 through the connection line 220.

[0121] Specifically, the connection line 220 includes a first circuit layer 221, a second circuit layer 222, a plurality of conductive pillars 223, and an outer circuit layer 224. The first circuit layer 221 is disposed on the first board surface 38, and the first circuit layer 221 is covered by the resin layer 210.

[0122] Furthermore, the first circuit layer 221 can be electrically coupled to the multiple flip-chip pads 141 via the multiple solders 230. That is, each solder 230 is disposed between the first circuit layer 221 and the multiple flip-chip pads 141, and the flip-chip integrated circuit chip 1 can be fixed on the first circuit layer 221 and electrically coupled to the first circuit layer 221 via the multiple solders 230.

[0123] The second circuit layer 222 is disposed on the second board surface 39, and the second circuit layer 222 is electrically coupled to the flip-chip LED chip 2 and the first circuit layer 221. In practical applications, the second circuit layer 222 can be electrically coupled to the first circuit layer 221 through multiple via holes on the substrate 3, so that the second circuit layer 222 can be electrically coupled to the flip-chip LED chip 2 via multiple flip-chip pads 141 electrically coupled to the first circuit layer 221.

[0124] Furthermore, the outer circuit layer 224 is disposed on an outer side P210 of the resin layer 210 away from the substrate 3, and the outer circuit layer 224 can be used to connect an external circuit or component. The outer circuit layer 224 is electrically coupled to the first circuit layer 221 through a plurality of conductive pillars 223 embedded in the resin layer 210. That is, one end of each conductive pillar 223 is electrically coupled to the first circuit layer 221, and the other end of each conductive pillar 223 is electrically coupled to the outer circuit layer 224.

[0125] It is worth noting that the plurality of conductive pillars 223 are preferably hollow structures with a filling space SP, and the filling space SP of each conductive pillar 223 can be filled by a portion of the resin layer 210. Specifically, the resin layer 210 includes a covering portion 211 and a filling portion 212. The covering portion 211 is disposed on the first plate surface 38 and covers the flip-chip integrated circuit chip 1, such that the covering portion 211 has the outer surface P210 on which the outer circuit layer 224 is disposed. Preferably, there is a predetermined distance D1 of more than 30 micrometers between the outer surface P210 of the covering portion 211 and the chip body 11, so that the covering portion 211 can adequately protect the chip body 11 on the basis of miniaturization.

[0126] Furthermore, the covering portion 211 has a plurality of mounting holes 2111, and a plurality of conductive posts 223 are respectively mounted in the plurality of mounting holes 2111. In practical applications, each conductive post 223 may be formed by coating a conductive metal on the inner edge of each mounting hole 2111, so that the conductive post 223 creates the filling space SP within the mounting hole 2111. The filling portion 212 then fills the filling space SP of the plurality of conductive posts 223.

[0127] It should be noted that, in practical applications, the design of "each of the conductive pillars 223 having the filling space SP and filling the filling portion 212" can be adjusted according to the designer's needs. For example, in other embodiments not shown, each of the conductive pillars 223 may also be a solid conductive pillar (i.e., the conductive pillar 223 does not have the filling space SP), so that the resin layer 210 does not have the filling portion 212 filling the filling space SP.

[0128] Re-reference Figure 18As shown, the solder resist coating 240 is disposed on the outer surface P210 and the second plate surface 39, and the solder resist coating 240 surrounds the outer circuit layer 224 and the second circuit layer 222. That is, the solder resist coating 240 can be applied to the non-conductive areas of the outer surface P210 and the non-conductive areas of the second plate surface 39, so that the solder resist coating 240 can improve the circuit reliability of the light-emitting device 200.

[0129] Cooperate Figure 18 As shown, the reflective wall 250 is disposed on the second plate surface 39, and the reflective wall 250 surrounds the flip-chip LED chip 2. Furthermore, the light-emitting device 200 may also include a light-transmitting package 260, which is inserted into the reflective wall 250 and covers the flip-chip LED chip 2.

[0130] Of course, in practical applications, the reflective wall 250 and the light-transmitting encapsulation body 260 can be omitted according to the designer's needs. That is to say, the light-emitting device 200 of this application is not limited to having the reflective wall 250 and the light-transmitting encapsulation body 260.

[0131] Secondly, to facilitate a clearer understanding of the light-emitting device 200 described in this embodiment, one example of its fabrication will be used below for illustration, but this application is not intended to limit the scope of the invention. For example, Figure 19 As shown, the manufacturing method of the light-emitting device 200 includes steps S101 to S117.

[0132] Step S101: A flip-chip integrated circuit chip 1 is fixed onto a first surface 38 of a substrate 3 using multiple solder balls 230 (e.g., solder balls), so that the flip-chip integrated circuit chip 1 is electrically coupled to a first circuit layer 221 on the substrate (e.g., solder balls). Figure 20 (As shown).

[0133] Step S103: Using a vacuum hot press (not shown), a resin material is applied to the first plate surface 38, forming a covering portion 211 (e.g., ...). Figure 21 (As shown).

[0134] Step S105: Using a laser device (not shown), a plurality of mounting holes 2111 are formed in the cover portion 211, and the position of each mounting hole 2111 corresponds to the first circuit layer 221 (e.g., ...). Figure 22 (As shown).

[0135] Step S107: Electroplat a conductive metal (such as...) onto the surface of the cover portion 211 and the inner edge of each of the provided holes 2111. Figure 23 (As shown).

[0136] Step S109: The conductive metal and a metal surface located on a second plate surface 39 of the substrate 3 are processed by etching, so that the conductive metal on the surface of the cover portion 211 forms an outer circuit layer 224, the conductive metal located at the inner edge of each of the provided holes 2111 forms a hollow conductive pillar 223, and the metal surface on the second plate surface 39 forms a second circuit layer 222 (e.g., ...). Figure 24 (As shown).

[0137] Step S111: Fill each of the conductive pillars 223 with the resin material to form a filling portion 212 and electroplate it with metal (i.e., a portion of the outer circuit layer 224, such as...). Figure 25 (As shown). The manufacturing method of the light-emitting device 200 can omit step S111 according to the designer's requirements. For example, when each of the conductive pillars 223 is a solid conductive pillar, step S109 can be completed before directly implementing step S113.

[0138] Step S113: Apply a solder resist material to the surface of the cover portion 211 and the second plate surface 39 to form a solder resist coating 240 (e.g., Figure 25 (As shown).

[0139] Step S115: Fix the flip-chip LED chip 2 to the second board surface 39 using multiple solder balls 230 (e.g., solder balls), so that the flip-chip LED chip 2 is electrically coupled to the second circuit layer 222 (e.g., ...). Figure 26 (As shown).

[0140] Step S117: Install a reflective wall 250 and a light-transmitting encapsulation body 260 onto the second plate surface 39, such that the reflective wall 250 surrounds the flip-chip LED chip 2, and the light-transmitting encapsulation body 260 covers the flip-chip LED chip 2 (e.g., Figure 18 (As shown). The manufacturing method of the light-emitting device 200 can omit step S117 according to the designer's requirements. For example, when the light-emitting device 200 does not have the reflective wall 250 and the light-transmitting encapsulation body 260 installed according to the designer's requirements, the light-emitting device 200 can be obtained by completing step S115.

[0141] Accordingly, the light-emitting device 200 can be manufactured through the above steps S101 to S117.

[0142] Seventh Embodiment

[0143] Please see Figures 27 to 39As shown, this is the seventh embodiment of this application. Since this embodiment is similar to the sixth embodiment described above, the similarities between the two embodiments will not be repeated. The main differences between this embodiment and the sixth embodiment described above are explained as follows:

[0144] like Figure 27 As shown, the covering portion 211 of the resin layer 210 is disposed on the first plate surface 38 and covers the flip-chip integrated circuit chip 1. That is, in this embodiment, the covering portion 211 only covers the flip-chip integrated circuit chip 1 and a portion of the first circuit layer 221, and the covering portion 211 does not completely cover the first circuit layer 221.

[0145] Furthermore, in this embodiment, the connecting line 220 replaces the plurality of conductive pillars 223 and the outer circuit layer 224 in the sixth embodiment through a circuit cover plate 225. Specifically, the circuit cover plate 225 is disposed on the first plate surface 38, and the circuit cover plate 225 is electrically coupled to the first circuit layer 221. In this embodiment, the height of the circuit cover plate 225 is greater than the height of the reflective wall 250, but this application is not limited thereto.

[0146] Furthermore, the circuit cover plate 225 has an opening OP, which can accommodate the flip-chip integrated circuit chip 1 and the resin layer 210. That is, the circuit cover plate 225 surrounds the flip-chip integrated circuit chip 1 and the resin layer 210.

[0147] The circuit cover plate 225 has a predetermined distance D2 between its outer surface P225B, which is away from the substrate 3, and the resin layer 210. The predetermined distance D2 is preferably more than 30 micrometers, so that the circuit cover plate 225 can protect the flip-chip integrated circuit chip 1 within the opening OP.

[0148] In addition, in order to ensure that the flip-chip integrated circuit chip 1 has an ideal heat dissipation environment, the circuit cover plate 225 has a heat dissipation gap D3 between an inner side surface P225A in the opening OP and the resin layer 210 (that is, the heat dissipation gap D3 connects to the opening OP), and the heat dissipation gap D3 is preferably greater than 50 micrometers.

[0149] It is worth noting that, in this embodiment, the circuit cover plate 225 and the flip-chip integrated circuit chip 1 are connected by multiple low-temperature solders of the light-emitting device 200 (i.e., Figure 27The 230B and 230B' of the circuit are electrically coupled to the first circuit layer 221. Specifically, each of the low-temperature solders is disposed between the first circuit layer 221 and the circuit cover plate 225, and between the first circuit layer 221 and the plurality of flip-chip pads 141, so that the circuit cover plate 225 and the flip-chip integrated circuit chip 1 can be fixed to the first circuit layer 221 by the plurality of low-temperature solders.

[0150] Furthermore, to accommodate the multiple low-temperature solders, the flip-chip LED chip is electrically coupled to the second circuit layer 222 via multiple high-temperature solders 230A of the light-emitting device. In other words, each of the high-temperature solders 230A is disposed between the second circuit layer 222 and the flip-chip LED chip 2, so that the flip-chip LED chip 2 is fixed to the second circuit layer 222 by the multiple high-temperature solders 230A. Here, each high-temperature solder refers to a soldering material with a higher melting point than the low-temperature solder, and the melting point difference between the multiple high-temperature solders 230A and the multiple low-temperature solders is not less than 20 degrees Celsius. Accordingly, the light-emitting device 200 can be more easily manufactured using the multiple low-temperature solders and the multiple high-temperature solders 230A.

[0151] To more easily understand the light-emitting device 200 of this embodiment (e.g., the manufacturing advantages resulting from the plurality of low-temperature solders and the plurality of high-temperature solders 230A), one manufacturing example of the light-emitting device 200 will be described below, but this application is not limited thereto. For example, Figure 28 As shown, the manufacturing method of the light-emitting device 200 includes steps S201 to S209.

[0152] Step S201: Using multiple high-temperature solder 230A (e.g., high-temperature solder balls), fix the flip-chip LED chip 2 onto a second surface 39 of a substrate 3 having double-sided circuitry and a solder resist coating 240, so that the flip-chip LED chip 2 is electrically coupled to a second circuit layer 222 on the second surface 39 (e.g., high-temperature solder balls). Figure 29 (As shown).

[0153] Step S203: Install a reflective wall 250 and a light-transmitting encapsulation body 260 onto the second plate surface 39, such that the reflective wall 250 surrounds the flip-chip LED chip 2, and the light-transmitting encapsulation body 260 covers the flip-chip LED chip 2 (e.g., Figure 30(As shown). The manufacturing method of the light-emitting device 200 can omit step S203 according to the designer's requirements. For example, when the light-emitting device 200 does not install the reflective wall 250 and the light-transmitting encapsulation body 260 according to the designer's requirements, step S205 can be directly implemented after step S201 is completed.

[0154] Step S205: Fix the flip-chip integrated circuit chip 1 onto a first surface 38 of the substrate 3 using a plurality of first low-temperature solder 230B (e.g., low-temperature solder balls), so that the flip-chip integrated circuit chip 1 is electrically coupled to a first circuit layer 221 on the substrate 3 (e.g., low-temperature solder balls). Figure 31 (As shown).

[0155] Step S207: Molding a resin material onto the flip-chip integrated circuit chip 1, thereby forming a resin layer 210 (e.g., ...) on the surface of the flip-chip integrated circuit chip 1. Figure 32 (As shown). The resin material can be molded onto the flip-chip integrated circuit chip 1 using a mold M, but this application is not limited thereto.

[0156] Step S209: A circuit cover plate 225 is fixed to the first surface 38 of the substrate 3 and surrounding the flip-chip integrated circuit chip 1 using multiple second low-temperature solder 230B' (e.g., low-temperature solder balls), so that the circuit cover plate 225 is electrically coupled to the first circuit layer 221 on the substrate (e.g., low-temperature solder balls). Figure 27 (As shown).

[0157] Accordingly, the flip-chip LED chip 2 will not be affected by step S209 by the high-temperature solder 230A and the second circuit layer 222 will not be separated. The light-emitting device 200 can be fabricated through the aforementioned steps S201-S209, but the way the resin layer 210 covers the flip-chip integrated circuit chip 1 can also be different. For another example, such as... Figure 33 As shown, the method for manufacturing the light-emitting device includes steps S301 to S311.

[0158] Step S301: Obtain an additional circuit board 300 (e.g., one with multiple flip-chip integrated circuit chips 1) that is configured on it. Figure 34 (As shown).

[0159] Step S303: Apply a resin material to the additional circuit board 300 to form a resin layer 210 on the surface of each flip-chip integrated circuit chip 1 (e.g., ...). Figure 35 (As shown).

[0160] Step S305: Cut and remove the additional circuit board 300 to obtain one of the flip-chip integrated circuit chips 1 (e.g., one covered by the resin layer 210) Figure 36 (As shown).

[0161] Step S307: Using multiple high-temperature solder 230A (e.g., high-temperature solder balls), fix the flip-chip LED chip 2 onto a second surface 39 of a substrate 3 having double-sided circuitry, so that the flip-chip LED chip 2 is electrically coupled to a second circuit layer 222 on the second surface 39 (e.g., high-temperature solder balls). Figure 37 (As shown).

[0162] Step S309: Install a reflective wall 250 and a light-transmitting encapsulation 260 onto the second plate surface 39, such that the reflective wall 250 surrounds the flip-chip LED chip 2, and the light-transmitting encapsulation 260 covers the flip-chip LED chip 2 (e.g., ...). Figure 38 (As shown). The manufacturing method of the light-emitting device 200 can omit step S309 according to the designer's requirements. For example, when the light-emitting device 200 does not install the reflective wall 250 and the light-transmitting encapsulation body 260 according to the designer's requirements, step S307 can be completed before directly implementing step S311.

[0163] Step S311: Using multiple low-temperature solders (e.g., low-temperature solder balls), fix the flip-chip integrated circuit chip 1 and a circuit cover plate 225 onto a first surface 38 of the substrate 3, so that the flip-chip integrated circuit chip 1 and the circuit cover plate 225 are electrically coupled to a first circuit layer 221 on the substrate 3 (e.g., ...). Figure 39 (As shown).

[0164] Accordingly, the light-emitting device 200 can be manufactured through the above steps S301 to S311.

[0165] Technical effects of this application

[0166] In summary, the flip-chip integrated circuit chip and light-emitting device disclosed in this application can provide ideal product reliability while miniaturizing through the design that "the layout distribution of the plurality of flip-chip pads is more average than the layout distribution of the plurality of metal pads" and "the orthographic projection of the plurality of flip-chip pads toward the surface of the chip body generates a plurality of projection areas, and the position of each projection area is not in a central area of ​​the layout distribution".

[0167] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. All equivalent changes and modifications made in accordance with the claims of this application shall fall within the scope of protection of the claims of this application.

Claims

1. A flip-chip integrated circuit chip, characterized in that: The flip-chip integrated circuit chip comprises: A chip body; A plurality of metal pads are disposed on a surface of the chip body; a circuit redistribution layer formed on the surface of the chip body and burying a plurality of the metal pads therein; and A plurality of flip chip pads are disposed on the circuit redistribution layer and are respectively electrically coupled to the plurality of metal pads through the circuit redistribution layer; Among them, a layout distribution of the multiple flip-chip pads is average compared to the layout distribution of the multiple metal pads, and the multiple flip-chip pads are projected toward the surface of the chip body to generate multiple projection areas respectively, and the position of each projection area is not within a central area of ​​the layout distribution.

2. The flip chip integrated circuit chip according to claim 1, characterized in that: The area of ​​the central region is equal to or smaller than any of the flip chip pads.

3. The flip chip integrated circuit chip according to claim 1, characterized in that: The edges of the plurality of metal pads define a layout boundary, and each side of the layout boundary is located in at least two of the projection areas.

4. The flip chip integrated circuit chip according to claim 1, characterized in that: At least a portion of the plurality of projection areas are symmetrically arranged along at least one symmetry axis.

5. A light emitting device, characterized in that: The light emitting device comprises: a substrate; The flip chip integrated circuit chip according to any one of claims 1 to 4; and At least one flip-chip light emitting diode chip is disposed at intervals from the flip-chip integrated circuit chip. The at least one flip-chip light emitting diode chip is electrically coupled to the flip-chip integrated circuit chip through the substrate.

6. The light emitting device according to claim 5, characterized in that: The substrate comprises: A first layer board, carrying the flip-chip integrated circuit chip and the at least one flip-chip light-emitting diode chip; a second layer board disposed on one side of the first layer board, the second layer board comprising an upper insulating layer, a plurality of first conductive pads, and a plurality of first conductive pillars, the plurality of first conductive pads being disposed on the upper insulating layer, and the plurality of first conductive pads being electrically coupled to the plurality of flip chip pads through the plurality of first conductive pillars; a third layer board, disposed on a side of the second layer board away from the first layer board, the third layer board comprising a lower insulating layer, a plurality of second conductive pads, and a plurality of second conductive pillars, the plurality of second conductive pads being disposed on the lower insulating layer, and the plurality of second conductive pads being electrically coupled to the plurality of first conductive pads through the plurality of second conductive pillars; A fourth layer board is disposed on a side of the third layer board away from the first layer board, and the fourth layer board includes a plurality of outer pads, and the plurality of outer pads are electrically coupled to the plurality of second conductive pads.

7. The light emitting device according to claim 6, characterized in that: There is a first predetermined spacing distance between any two adjacent first conductive pads and between any two adjacent second conductive pads, a second predetermined spacing distance between the first conductive pad adjacent to an edge of the upper insulating layer and the edge of the upper insulating layer, and a second predetermined spacing distance between the second conductive pad adjacent to an edge of the lower insulating layer and the edge of the lower insulating layer, and the first predetermined spacing distance and the second predetermined spacing distance are 60 microns.

8. The light emitting device according to claim 6, characterized in that: The at least one flip-chip LED chip has a red LED chip, a green LED chip, and a blue LED chip. The long axis of the red LED chip, the long axis of the green LED chip, and the long axis of the blue LED chip are parallel to each other, and the red LED chip, the green LED chip, and the blue LED chip are arranged in a triangle.

9. The light emitting device according to claim 6, characterized in that: The at least one flip-chip LED chip has a red light diode chip, a green light diode chip, a blue light diode chip, and a white light diode chip. The short axis extension line of the red light diode chip, the short axis extension line of the green light diode chip, and the short axis extension line of the blue light diode chip can overlap with each other, and the white light diode chip is located on a common side of the red light diode chip, the green light diode chip, and the blue light diode chip.

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