Charging and discharging management circuit and charging base

Abstract

The embodiment of the utility model provides a charging and discharging management circuit and a charging base. The charging and discharging management circuit is characterized in that the drain electrode of a first transistor is connected with a direct-current power supply; the grid electrode of the second transistor is coupled with the grid electrode of the first transistor to form a common grid electrode, and the source electrode of the second transistor is coupled with the source electrode of the first transistor to form a common source electrode; the voltage starting end of the management chip is coupled with the direct-current power supply; the first switch control end is coupled with the common source electrode; the second switch control end is coupled with the common gate; the voltage reference end is coupled with the voltage starting end; the current setting end is coupled with the voltage reference end; the overcurrent protection end is coupled with the voltage reference end; the overvoltage protection end is coupled with the output end of the power supply circuit; two ends of the input current sampling end are coupled with a sixth resistor; the output terminal and the feedback terminal are coupled to the positive output terminal. According to the invention, the voltage and current of the battery in the charging and discharging processes are kept in a safe range, potential risks such as over-charging, over-discharging and overheating of the battery are effectively avoided, and the service life of the lithium battery is remarkably prolonged.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power supply circuits, and in particular to a charge and discharge management circuit and a charging base. Background Art

[0002] With the popularity of portable electronic devices, the demand for efficient and safe battery charge and discharge management technology is growing. The core of the battery management system (BMS) is to accurately control the charge and discharge process to extend the battery life, ensure safety and optimize energy efficiency. Traditional charge and discharge management solutions often focus on the realization of a single function, such as overcharge protection, over-discharge protection, short circuit protection, etc., but in complex and changing application environments, a single-function charge and discharge management system is difficult to meet the needs of high-performance battery management systems. Modern intelligent battery management systems require real-time monitoring of battery status, such as voltage, current, temperature, etc., and dynamically adjust the charge and discharge strategy according to these parameters to ensure that the battery works in the best state. Especially for devices using lithium-ion batteries, due to the chemical characteristics of lithium-ion batteries, overcharging, over-discharging, and excessive or low temperatures may cause irreversible damage to them, and even cause safety problems. Therefore, it is particularly important to develop a charge and discharge management circuit with high integration, rapid response, and precise control. Existing charge and discharge management circuits often face challenges in design, such as how to achieve fast and accurate over-current and over-voltage protection, how to accurately control the charging current and voltage to match the battery characteristics, and how to effectively use the feedback mechanism to adjust the output in real time to ensure the stability and safety of the battery charging state. In addition, improving the energy efficiency of the circuit and reducing heat generation are also important considerations in the design. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a charge and discharge management circuit and a charging base to solve the problems in the related art.

[0004] A first aspect of the present disclosure provides a charge and discharge management circuit, which includes: a power supply circuit and a management circuit;

[0005] The input end of the power supply circuit is coupled to external alternating current, and the output end of the power supply circuit outputs direct current power;

[0006] The input end of the management circuit is coupled to the output end of the power supply circuit, the output end of the management circuit is coupled to an external load, and the management circuit includes:

[0007] a first transistor, wherein a drain of the first transistor is connected to the DC power supply;

[0008] a second transistor, wherein a gate of the second transistor is coupled to a gate of the first transistor to form a common gate, and a source of the second transistor is coupled to a source of the first transistor to form a common source;

[0009] A management chip, the management chip comprising a voltage start terminal, a first switch control terminal, a second switch control terminal, a voltage reference terminal, a current setting terminal, an overcurrent protection terminal, an overvoltage protection terminal, an output terminal, an input current sampling terminal, a driver output terminal, an output current sampling terminal and a feedback terminal;

[0010] The voltage starting terminal is coupled to the DC power supply through a starting circuit;

[0011] The first switch control terminal is coupled to the common source through a first resistor; the second switch control terminal is coupled to the common gate through a second resistor;

[0012] The conduction of the first transistor and the second transistor is controlled by a voltage difference between the first switch control terminal and the second switch control terminal;

[0013] The voltage reference terminal is coupled to the voltage start terminal via a first capacitor and a second capacitor, and the voltage reference terminal outputs a reference voltage;

[0014] The current setting end is coupled to the voltage reference end via a third resistor and a fourth resistor, and the current setting end is grounded via a fifth resistor;

[0015] The overcurrent protection terminal is coupled to the voltage reference terminal through an overcurrent protection circuit;

[0016] The overvoltage protection terminal is coupled to the output terminal of the power supply circuit through an overvoltage protection circuit;

[0017] Two ends of the input current sampling terminal are coupled to a sixth resistor, one end of the sixth resistor is coupled to the drain of the second transistor, and the other end of the sixth resistor is coupled to the driver output terminal via a third capacitor;

[0018] The output end is coupled to the positive output end via the first inductor and the seventh resistor;

[0019] Two ends of the output current sampling terminal are respectively coupled to two ends of the seventh resistor;

[0020] The feedback end is coupled to a feedback circuit, and is coupled to the positive output end through the feedback circuit.

[0021] In an embodiment of the first aspect, the startup circuit includes:

[0022] A first diode, wherein an anode of the first diode is coupled to the output end of the power supply circuit, and a cathode of the first diode is coupled to the voltage start end through an eighth resistor.

[0023] In an embodiment of the first aspect, the overcurrent protection circuit includes:

[0024] a ninth resistor, one end of which is coupled to the overcurrent protection terminal, and the other end of which is grounded;

[0025] A tenth resistor, one end of the tenth resistor is coupled to the overcurrent protection end, and the other end of the tenth resistor is coupled to the voltage reference end through an eleventh resistor.

[0026] In an embodiment of the first aspect, the overvoltage protection circuit includes:

[0027] an eleventh resistor, one end of the eleventh resistor being coupled to the output end of the power supply circuit, and the other end of the eleventh resistor being grounded via a twelfth resistor;

[0028] A connection point between the eleventh resistor and the twelfth resistor is coupled to the overvoltage protection terminal.

[0029] In an embodiment of the first aspect, the feedback circuit comprises:

[0030] a thirteenth resistor, one end of the thirteenth resistor being coupled to the positive output terminal, and the other end of the thirteenth resistor being grounded and / or coupled to the negative output terminal via a fourteenth resistor;

[0031] A connection point between the thirteenth resistor and the fourteenth resistor is coupled to the feedback terminal.

[0032] In an embodiment of the first aspect, the management chip further includes: an output control terminal, the output control terminal being grounded through a third capacitor and / or a fourth capacitor;

[0033] The third capacitor is connected in parallel with the fourth capacitor.

[0034] In an embodiment of the first aspect, the management chip further includes an out-of-time protection terminal, an over-temperature protection terminal, and a status indication terminal;

[0035] The overtime protection terminal is grounded via a fifth capacitor;

[0036] The over-temperature protection terminal is grounded via a fifteenth resistor;

[0037] The state indicating terminal outputs an indication signal for indicating whether the state is in a charging state.

[0038] In an embodiment of the first aspect, the input current sampling terminal includes an input current sampling positive input terminal and an input current sampling negative input terminal, the input current sampling positive input terminal is coupled to one end of the sixth resistor, and the input current sampling negative input terminal is coupled to the other end of the sixth resistor.

[0039] In an embodiment of the first aspect, the output current sampling terminal includes an output current sampling positive input terminal and an output current sampling negative input terminal, the output current sampling positive input terminal is coupled to one end of the seventh resistor, and the output current sampling negative input terminal is coupled to the other end of the seventh resistor; the ratio of the voltage difference between the current sampling positive input terminal and the output circuit sampling negative input terminal to the seventh resistor is the actual charging current of the management chip.

[0040] A second aspect of the present disclosure provides a charging base, which includes the charge and discharge management circuit described in any one of the above items.

[0041] Beneficial effects of the present disclosure: The present disclosure ensures that the voltage and current of the battery are kept within a safe range during the charging and discharging process by integrating a management chip with multiple functions such as voltage start-up, switch control, current setting, overcurrent protection, and overvoltage protection, thereby effectively avoiding potential risks such as battery overcharging, overdischarging, and overheating, and significantly extending the service life of the lithium battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram showing the circuit principle of a management circuit of a charge and discharge management circuit in one embodiment of the present disclosure is shown.

[0043] Figure 2 A schematic diagram showing the circuit principle of a power supply circuit of a charge and discharge management circuit in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] The following is an explanation of the embodiments of the present disclosure by specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the information disclosed by the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application modules without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0045] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0046] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or a group of embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.

[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, "a group" means two or more, unless otherwise clearly and specifically defined.

[0048] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0049] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0050] Although the terms first, second, etc. are used to represent various elements in this article in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate that there are the described features, steps, operations, elements, modules, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or a group of other features, steps, operations, elements, modules, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0051] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0052] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with relevant technical literature and the message of the present disclosure, and shall not be overly interpreted as ideal or very formal meanings unless defined.

[0053] In related technologies, charge and discharge management solutions often focus on the realization of a single function, such as overcharge protection, over-discharge protection, short-circuit protection, etc. However, in complex and changeable application environments, a single-function charge and discharge management system is difficult to meet the needs of a high-performance battery management system. Modern intelligent battery management systems require real-time monitoring of battery status, such as voltage, current, temperature, etc., and dynamically adjust the charge and discharge strategy based on these parameters to ensure that the battery works in the best state. Especially for devices using lithium-ion batteries, due to the chemical characteristics of lithium-ion batteries, overcharging, over-discharging, and excessive or low temperatures may cause irreversible damage to them and even cause safety issues.

[0054] A first aspect of the present disclosure provides a charge and discharge management circuit, which includes: a power supply circuit and a management circuit.

[0055] The input terminal of the power supply circuit is coupled to external AC power, and the output terminal SW1 of the power supply circuit outputs DC power.

[0056] The input terminal of the management circuit is coupled to the output terminal SW1 of the power supply circuit, and the output terminal SW1 of the management circuit is coupled to the battery. Figure 1 In the embodiment, the management circuit includes: a first transistor Q1, a second transistor Q2 and a management chip.

[0057] The drain of the first transistor Q1 is connected to the DC power supply.

[0058] The gate of the second transistor Q2 is coupled to the gate of the first transistor Q1 to form a common gate, and the source of the second transistor Q2 is coupled to the source of the first transistor Q1 to form a common source.

[0059] The management chip includes a voltage startup terminal AVCC, a first switch control terminal CMSRC, a second switch control terminal ACDRV, a voltage reference terminal VREF, a current setting terminal ISET, an overcurrent protection terminal IACSET, an overvoltage protection terminal OVPSET, an output terminal SW1, an input current sampling terminal, a driver output terminal BATDRV, an output current sampling terminal and a feedback terminal FB1.

[0060] The voltage startup terminal AVCC is coupled to the DC power supply through a startup circuit.

[0061] The first switch control terminal CMSRC is coupled to the common source through a first resistor R1 ; the second switch control terminal ACDRV is coupled to the common gate through a second resistor R2 .

[0062] The conduction of the first transistor Q1 and the second transistor Q2 is controlled by a voltage difference between the first switch control terminal CMSRC and the second switch control terminal ACDRV.

[0063] The voltage reference terminal VREF is coupled to the voltage start terminal AVCC via the first capacitor C1 and the second capacitor C2 , and the voltage reference terminal VREF outputs a reference voltage.

[0064] The current setting terminal ISET is coupled to the voltage reference terminal VREF via the third resistor R3 and the fourth resistor R4 , and the current setting terminal ISET is grounded via the fifth resistor R5 .

[0065] The over-current protection terminal IACSET is coupled to the voltage reference terminal VREF through an over-current protection circuit.

[0066] The overvoltage protection terminal OVPSET is coupled to the output terminal SW1 of the power supply circuit through an overvoltage protection circuit.

[0067] Two ends of the input current sampling terminal are coupled to a sixth resistor R6 , one end of the sixth resistor R6 is coupled to the drain of the second transistor Q2 , and the other end of the sixth resistor R6 is coupled to the driver output terminal BATDRV via a third capacitor C3 .

[0068] The output terminal SW1 is coupled to the positive output terminal VO+ via the first inductor and the seventh resistor R7.

[0069] Two ends of the output current sampling terminal are respectively coupled to two ends of the seventh resistor R7.

[0070] The feedback terminal FB1 is coupled to a feedback circuit, and coupled to the positive output terminal VO+ through the feedback circuit.

[0071] Optionally, in some embodiments, Figure 2In the embodiment, the power supply circuit includes: an input circuit, a power chip, an RCD absorption circuit, a transformer T1 and an output circuit.

[0072] The input end of the input circuit is coupled to the live wire L and the neutral wire N, and the output end SW1 of the input circuit is coupled to the transformer T1 via a rectifier bridge.

[0073] The transformer T1 includes a primary coil, an auxiliary coil and a secondary coil. The primary coil includes a first end 1 and a second end 2, the secondary coil includes a third end 3 and a fourth end 4, and the auxiliary coil includes a fifth end 5 and a sixth end 6. The second end 2 and the third end 3 are the same end; the second end 2 and the fifth end 5 are the same end.

[0074] Among them, the secondary coil is used to supply power to the power chip.

[0075] exist Figure 2 In the embodiment, the input circuit includes: an adjustable variable resistor RV1, an eleventh capacitor C11, a seventeenth resistor R17, an eighteenth resistor R18 and a common mode suppression inductor T2.

[0076] The live wire L is coupled to one end of the adjustable resistor RV1 through the first fuse F1, and the neutral wire N is coupled to the other end of the adjustable resistor RV1 through the second fuse F2. The first fuse F1 is disconnected when there is an overcurrent to protect the back-end circuit. The second fuse F2 is a thermistor that can absorb surge energy when there is a transient surge. The adjustable resistor RV1 is a varistor that can clamp the voltage to protect the back-end circuit when a lightning surge generates a transient overvoltage.

[0077] The eleventh capacitor C11 is connected in parallel with the adjustable resistor RV1; the eleventh capacitor C11 is used to suppress differential mode interference; one end of the seventeenth resistor R17 is coupled to one end of the eleventh capacitor C11, and the other end of the seventeenth resistor R17 is coupled to the other end of the eleventh capacitor C11 through the eighteenth resistor R18. The seventeenth resistor R17 and the eighteenth resistor R18 are leakage resistors of the eleventh resistor R11.

[0078] The common-mode suppression inductor T2 is used to suppress common-mode interference. The common-mode suppression inductor T2 includes a first side and a second side. One end of the first side is coupled to the live line L, and the other end of the first side is coupled to the input end of the rectifier bridge; one end of the second side is coupled to the neutral line N, and the other end of the second side is coupled to the input end of the rectifier bridge.

[0079] Optional, in Figure 2 In the embodiment, the power chip includes a power input terminal, an overcurrent detection terminal, a power chip power supply terminal, a feedback terminal FB1 and a power chip ground terminal.

[0080] In some embodiments, the power chip may be implemented as a chip of model PN6653 and a related series with similar functions, or a power chip of other manufacturers with similar principles.

[0081] The power input terminal is coupled to the second terminal 2; the overcurrent detection terminal is coupled to an overcurrent detection circuit; the power supply terminal of the power chip is coupled to the auxiliary coil through a chip power supply circuit; the feedback terminal FB1 is coupled to the fifth terminal 5 through a feedback circuit; and the power chip ground terminal is grounded.

[0082] The overcurrent detection circuit is used to determine whether the battery is overcurrent, and the overcurrent detection circuit includes: a twenty-fifth resistor R25 and a twenty-sixth resistor R26; one end of the twenty-fifth resistor R25 is coupled to the overcurrent detection end, and the other end of the twenty-fifth resistor R25 is grounded; the twenty-fifth resistor R25 and the twenty-sixth resistor R26 are connected in parallel. When the battery is overcurrent, the voltage on the twenty-fifth resistor R25 and the twenty-sixth resistor R26 changes and is transmitted to the overcurrent detection end, thereby triggering a protection mechanism, such as cutting off the power supply or reducing the current, to effectively prevent damage caused by overcurrent.

[0083] exist Figure 2 In the embodiment, the chip power supply circuit includes: a third diode D3, a twenty-second resistor R22 and a second energy storage filter capacitor EC2.

[0084] The anode of the third diode D3 is coupled to the fifth terminal 5, and the cathode of the third diode D3 is coupled to the power supply terminal of the power chip through the 22nd resistor R22; the third diode D3 is used to rectify the voltage output by the auxiliary coil, and the 22nd resistor R22 is used to limit the current to avoid instantaneous large current impacting the power chip and ensure the reliable operation of the circuit; the anode of the second energy storage filter capacitor EC2 is coupled to the power supply terminal of the power chip, and the cathode of the second energy storage filter capacitor EC2 is coupled to the sixth terminal 6. The second energy storage filter capacitor EC2 can store energy obtained from the auxiliary coil.

[0085] exist Figure 2In the embodiment, the feedback circuit includes: a twenty-third resistor R23 and a twenty-fourth resistor R24, one end of the twenty-third resistor R23 is coupled to the fifth end 5, and the other end of the twenty-third resistor R23 is grounded through the twenty-fourth resistor R24; the connection point between the twenty-third resistor R23 and the twenty-fourth resistor R24 ​​is coupled to the feedback terminal FB1. The twenty-third resistor R23 and the twenty-fourth resistor R24 ​​are used to detect the voltage of the auxiliary coil and feed it back to the feedback terminal FB1; the power chip controls the duty cycle and frequency of the MOS on and off inside the power chip according to the signal fed back from the feedback terminal FB1 to achieve output constant voltage. The thirteenth capacitor C13 is used for filtering, so that the signal detected by the feedback circuit is more accurate.

[0086] A first energy storage filter capacitor EC1 is also provided between the output terminal SW1 of the rectifier bridge and the first terminal 1, the positive electrode of the first energy storage filter capacitor EC1 is coupled to the output terminal SW1 of the rectifier bridge and / or the first terminal 1, and the second terminal 2 of the first energy storage filter capacitor EC1 is grounded. The first energy storage filter capacitor EC1 is an energy storage capacitor, which is used to power the back-end circuit.

[0087] The RCD absorption circuit is used to absorb the peak voltage generated by the power input terminal of the power chip when the MOS tube built in the power chip is turned on and off. Figure 2 In the embodiment, the RCD absorption circuit includes: a nineteenth resistor R19, a twentieth resistor R20, a twenty-second resistor R22, a twelfth capacitor C12 and a second diode D2.

[0088] One end of the nineteenth resistor R19 is coupled to the first end 1, and the other end of the nineteenth resistor R19 is coupled to the cathode of the second diode D2 through the twenty-second resistor R20; therefore, the current can be allowed to be shunted at the peak, and before the second diode D2 is turned on, the nineteenth resistor R19 and the twentieth resistor R20 consume part of the transient energy to mitigate the impact. The positive electrode of the second diode D2 is coupled to the power input terminal; when the power supply circuit starts to work normally, the second diode D2 responds to the peak voltage and quickly turns on the protection circuit. One end of the twelfth capacitor C12 is coupled to the first end 1, and the other end of the twelfth capacitor C12 is coupled to the cathode of the second diode D2 through the twenty-second resistor R22.

[0089] The nineteenth resistor R19 is connected in parallel with the twelfth capacitor C12 for filtering; the twentieth resistor R20 is connected in parallel with the twenty-second resistor R22.

[0090] Optional, in Figure 2In the embodiment, the output circuit includes: a rectifier chip, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a fifteenth capacitor C15, a sixteenth capacitor C16, a third energy storage filter capacitor EC3 and a fourth energy storage filter capacitor EC4.

[0091] In some embodiments, the rectifier chip may be implemented as a PN8308M chip or a related series chip with similar functions, or a rectifier chip from other manufacturers with similar principles.

[0092] The rectifier chip is a secondary synchronous rectifier chip, which is used to rectify the output voltage of transformer T1 into a more stable direct current. Figure 2 In the embodiment, the rectifier chip includes: a rectifier chip power supply terminal VDD2, a rectifier chip ground terminal GND2 and a rectifier chip feedback terminal SW3.

[0093] One end of the 27th resistor R27 is coupled to the third end 3, and the other end of the 27th resistor R27 is coupled to the rectifier chip power supply end VDD2; one end of the 15th capacitor C15 is coupled to the 27th resistor R27, and the other end of the 15th capacitor C15 is coupled to the rectifier chip ground end GND2; the 15th capacitor C15 is used to supply power to the rectifier chip, and the 27th resistor R27 is used to limit current to protect the rectifier chip power supply end VDD2; one end of the 28th resistor R28 is coupled to the fourth end 4, and the other end of the 28th resistor R28 is coupled to the rectifier chip ground end GND2 through the 16th capacitor C16; the rectifier chip feedback end SW3 is coupled to the fourth end 4. The 28th resistor R28 and the 16th capacitor C16 are used for filtering, absorbing voltage spikes, and making the voltage more stable.

[0094] The third energy storage filter capacitor EC3 is connected in parallel with the fourth energy storage filter capacitor EC4, the positive electrode of the third energy storage filter capacitor EC3 is coupled to the third end 3, the negative electrode of the third energy storage filter capacitor EC3 is coupled to the fourth end 4, and the third energy storage filter capacitor EC3 is used to make the output voltage more stable.

[0095] A fourteenth capacitor C14 is further provided between the first end 1 and the ground end.

[0096] Optionally, the charge and discharge management circuit includes: a management circuit for managing output voltage, output current, overcurrent protection, overvoltage protection, etc. through a management chip.

[0097] In some embodiments, the management chip may be implemented as a chip of model SC89171 and a related series with similar functions, or a management chip of other manufacturers with similar principles.

[0098] Among them, Figure 1In the embodiment, the drain of the first transistor Q1 is connected to a DC power supply output by a power supply circuit. When the management chip is started, the first switch control terminal CMSRC and the second switch control terminal ACDRV draw power from the inside of the management chip. Since the gate of the first transistor Q1 and the gate of the second transistor Q2 are a common gate and are controlled by the first switch control terminal CMSRC, and the source of the first transistor Q1 and the source of the second transistor Q2 are a common source and are controlled by the second switch control terminal ACDRV, when the voltage difference at the common gate and the voltage difference at the common source reach a preset value, the first transistor Q1 and the second transistor Q2 are turned on.

[0099] After the voltage start-up terminal AVCC takes power from the output terminal of the power supply circuit through the start-up circuit, the management chip is activated to enable the management chip to work normally; the first capacitor C1 and the second capacitor C2 are used for filtering; the voltage reference terminal VREF is provided with a 3.3V reference voltage by the LDO built into the management chip as the voltage detection reference inside the management chip; the current setting terminal ISET is used to set the theoretical charging current, and the third resistor R3 and the fourth resistor R4 are connected in series to form a voltage divider network, the third resistor R3 is located between the current setting terminal ISET and the voltage reference terminal VREF, and the fourth resistor R4 is connected to the current setting terminal ISET. By changing the value of the third resistor R3, the voltage divider ratio is affected, and the voltage divider difference from the reference voltage to the current setting terminal ISET is indirectly adjusted, thereby adjusting the target current value. The fifth resistor R5 connects the current setting terminal ISET and the ground. The voltage divider network of the fifth resistor R5 and the voltage reference terminal VREF forms a stable pull-down, ensuring that the current setting terminal ISET has a stable reference, preventing drift, keeping the voltage divider ratio accurate, and the current setting accurate.

[0100] The overcurrent protection terminal IACSET is used to detect the current of the input circuit of the management chip to protect the management chip; the overvoltage protection terminal OVPSET is used to sample the voltage of the input circuit of the management chip to protect the management chip; the two ends of the sixth resistor R6 are connected to the input current sampling terminal to form a sampling loop, and one end of the sixth resistor R6 is coupled to the drain of the second transistor Q2. The sixth resistor R6 is used as a sampling resistor. When current flows through, a voltage drop will be generated. This voltage difference reflects the current state flowing through the second transistor Q2, and further reflects the size of the input current; further, the other end of the sixth resistor R6 is coupled to the drive output terminal SW1 through the third capacitor C3, and the third capacitor C3 is used for filtering. When the first transistor Q1 and the second transistor Q2 are turned on, the output terminal SW1 is turned on, the first inductor is charged through the output terminal SW1, and the battery is charged through the positive output terminal VO+.

[0101] The two ends of the seventh resistor R7 are coupled to the output current sampling terminal to form a loop. The resistance value of the seventh resistor R7 is the same as the resistance value of the sixth resistor R6. When the current flows through the seventh resistor R7, a voltage drop proportional to the current is generated. This voltage difference directly reflects the magnitude of the output current. The management chip analyzes and adjusts the output current control strategy in real time according to the sampled output current value at the output current sampling terminal to ensure the stability of the output current and battery protection.

[0102] The feedback circuit is coupled between the positive output terminal VO+ and the negative output terminal VO−, and is used for obtaining the actual working state of the output terminal SW1 and feeding back the actual working state to the feedback terminal FB1.

[0103] Optionally, the startup circuit includes:

[0104] A first diode D1, wherein an anode of the first diode D1 is coupled to the output end of the power supply circuit, and a cathode of the first diode D1 is coupled to the voltage start-up end AVCC via an eighth resistor R8.

[0105] Specifically, in some embodiments, when the power supply circuit outputs a DC power supply, the first diode D1 is turned on and coupled to the voltage start terminal AVCC through the eighth resistor R8. The first diode D1 is used to rectify the DC voltage output by the power supply circuit, and the eighth resistor R8 is used for current limiting protection and stable startup of the management chip.

[0106] Optional, in Figure 1 In the embodiment, the overcurrent protection circuit includes: a ninth resistor R9 and a tenth resistor R10.

[0107] One end of the ninth resistor R9 is coupled to the over-current protection terminal IACSET, and the other end of the ninth resistor R9 is grounded.

[0108] One end of the tenth resistor R10 is coupled to the over-current protection terminal IACSET, and the other end of the tenth resistor R10 is coupled to the voltage reference terminal VREF via an eleventh resistor R11.

[0109] Specifically, in some embodiments, when the current is normal, there is almost no significant voltage drop on the ninth resistor R9, which does not affect the circuit. However, when overcurrent occurs, the abnormal increase in current will generate a large voltage drop on the ninth resistor R9, and this voltage drop serves as an overcurrent signal. The voltage division of the tenth resistor R10 and the eleventh resistor R11 matches the reference voltage set at the voltage reference terminal VREF. Once overcurrent occurs, an additional voltage drop is generated on the ninth resistor R9, the voltage at the overcurrent terminal changes, and the voltage division of the tenth resistor R10 changes accordingly.

[0110] The overcurrent protection terminal IACSET generates an overcurrent detection signal through the voltage difference between the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11. When the overcurrent detection signal is detected as overcurrent, a protection action is immediately triggered, such as cutting off the power supply or reducing the current output to prevent damage to circuit components.

[0111] Optional, in Figure 1 In the embodiment, the overvoltage protection circuit includes: an eleventh resistor R11 and a twelfth resistor R12.

[0112] One end of the eleventh resistor R11 is coupled to the output end of the power supply circuit, and the other end of the eleventh resistor R11 is grounded via a twelfth resistor R12.

[0113] A connection point between the eleventh resistor R11 and the twelfth resistor R12 is coupled to the overvoltage protection terminal OVPSET.

[0114] Specifically, in some embodiments, the eleventh resistor R11 is a sampling resistor, and the voltage at the input is monitored through the eleventh resistor R11 and the twelfth resistor R12; the voltage on the eleventh resistor R11 changes with the output voltage of the power supply circuit. When the voltage increases, the voltage drop on the eleventh resistor R11 increases. The twelfth resistor R12 and the eleventh resistor R11 form a voltage divider network. When overvoltage occurs, the current through the twelve resistors increases, and the voltage drop also increases, ensuring that the overvoltage protection mechanism responds sensitively. The contact point between the eleventh resistor R11 and the twelfth resistor is directly coupled to the overvoltage protection terminal OVPSET, and the voltage at this point is used as an overvoltage signal. When the voltage exceeds the preset period, the voltage at this point increases, indicating that the voltage at the power supply end is abnormal, and the overvoltage protection strategy of the management chip is activated.

[0115] Optional, in Figure 1 In an embodiment, the feedback circuit comprises:

[0116] A thirteenth resistor R13, one end of the thirteenth resistor R13 is coupled to the positive output terminal VO+, and the other end of the thirteenth resistor R13 is grounded and / or coupled to the negative output terminal VO- through a fourteenth resistor R14.

[0117] A connection point between the thirteenth resistor R13 and the fourteenth resistor R14 is coupled to the feedback terminal FB1 .

[0118] Specifically, in some embodiments, one end of the thirteenth resistor R13 is coupled to the positive output terminal VO+ of the circuit, that is, the voltage output point, and the other end is connected to the negative output terminal VO- or ground through the fourteenth resistor R14 to form a voltage divider loop, wherein the fourteenth resistor R14 plays a regulating role to control the strength of the feedback signal. The current change through the fourteenth resistor R14 affects the feedback signal strength, that is, the feedback amount, and adjusts the circuit dynamic response speed and accuracy. The feedback terminal FB1 will feedback the management chip when the voltage is before 10% and after 90% to use trickle charging.

[0119] Optionally, the management chip further includes: an output control terminal PMID, and the output control terminal PMID is grounded through a third capacitor C3 and / or a fourth capacitor C4.

[0120] The third capacitor C3 and the fourth capacitor C4 are connected in parallel.

[0121] Specifically, in some embodiments, the third capacitor C3 and the fourth capacitor C4 are connected in parallel and connected to the output control terminal PMID to form a low pass for filtering high-frequency noise to ensure the purity of the output voltage signal. When the battery suddenly changes or the power source fluctuates, the third capacitor C3 and the fourth capacitor C4 store and release energy to ease the replenishment of electricity, reduce transient voltage changes, and improve dynamic response speed and overall stability.

[0122] Optionally, the management chip further includes a time-out protection terminal TTC, an over-temperature protection terminal TS and a status indication terminal STAT.

[0123] The overtime protection terminal TTC is grounded via a fifth capacitor C5.

[0124] The over-temperature protection terminal TS is grounded via a fifteenth resistor R15.

[0125] The state indicating terminal STAT outputs an indication signal for indicating whether the state is in a charging state.

[0126] Specifically, in some embodiments, the overtime protection terminal TTC is used to avoid overtime charging by managing the built-in safety timer of the chip. The safety timer in the trickle charging stage is fixed at 30 minutes. In some embodiments, the fifth capacitor C5 is 100nF, at this time, the safety timer in the fast charging stage is 10 hours. The safety timer in the trickle charging stage is 30min. The overtime protection terminal TTC can also be used for the mode selection function. When the overtime protection terminal TTC is pulled to the ground terminal, the battery and fast charging safety timers are disabled. When the overtime protection terminal TTC is pulled to the voltage reference terminal VREF, the safety timer is disabled, but charging termination is allowed.

[0127] The fifteenth resistor R15 is a thermistor, which is used to detect the battery temperature and feed back to the over-temperature protection terminal TS to protect the management chip. When the management chip starts working, the temperature of the battery is continuously monitored through the over-temperature protection terminal TTC and compared with the voltage of the voltage reference terminal VREF. When the over-temperature protection terminal fails, the management chip controls the charging to be suspended and feeds back to the status indication terminal STAT. The status indication terminal STAT is connected to an external indicator light to indicate the charging status.

[0128] Optional, in Figure 1 In an embodiment, the input current sampling end includes an input current sampling positive input end APC and an input current sampling negative input end APN, the input current sampling positive input end APC is coupled to one end of the sixth resistor R6, and the input current sampling negative input end APN is coupled to the other end of the sixth resistor R6.

[0129] Specifically, in some embodiments, the sixth resistor R6 is a sampling resistor, and when current passes through the sixth resistor R6, a voltage drop proportional to the current is generated across the sixth resistor R6. The voltage drop is the feedback of the input current.

[0130] Optionally, the output current sampling terminal includes an output current sampling positive input terminal SRP and an output current sampling negative input terminal SRN, the output current sampling positive input terminal SRP is coupled to one end of the seventh resistor R7, and the output current sampling negative input terminal SRN is coupled to the other end of the seventh resistor R7. The ratio of the voltage difference between the current sampling positive input terminal and the output circuit sampling negative input terminal to the seventh resistor R7 is the actual charging current of the management chip.

[0131] Specifically, in some embodiments, the voltage of the output current sampling negative input terminal SRN is equal to the battery voltage, and the voltage difference between the output current sampling positive input terminal SRP and the output current sampling negative input terminal SRN divided by 16 is the actual charging current of the battery.

[0132] Optionally, the management chip further includes a management chip ground terminal PGND, the management chip ground terminal PGND is grounded, and an internal charging terminal VCC, the internal charging terminal VCC is used to provide power for the LDO, and the internal charging terminal VCC is grounded through a tenth capacitor C10.

[0133] The output terminal SW1 is grounded via the seventh capacitor C7 and the sixteenth resistor R16. The seventh resistor R7 and the sixteenth resistor R16 form a filter circuit.

[0134] The internal charging terminal VCC provides a driving voltage to the internal driving terminal BT to supply power to the sixth capacitor C6 to turn on the output terminal SW1.

[0135] An eighth capacitor C8 and a ninth capacitor C9 are connected in parallel between the positive output terminal VO+ and the negative output terminal VO- for filtering.

[0136] In yet another embodiment of the present disclosure, a charging base is provided, which includes the charge and discharge management circuit described in any one of the above items.

[0137] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the protection scope of the present disclosure.

Claims

1. A charge and discharge management circuit, characterized in that: include: Power supply circuit and management circuit; The input end of the power supply circuit is coupled to external alternating current, and the output end of the power supply circuit outputs direct current power; The input end of the management circuit is coupled to the output end of the power supply circuit, the output end of the management circuit is coupled to an external load, and the management circuit includes: a first transistor, wherein a drain of the first transistor is connected to the DC power supply; a second transistor, wherein a gate of the second transistor is coupled to a gate of the first transistor to form a common gate, and a source of the second transistor is coupled to a source of the first transistor to form a common source; A management chip, the management chip comprising a voltage start terminal, a first switch control terminal, a second switch control terminal, a voltage reference terminal, a current setting terminal, an overcurrent protection terminal, an overvoltage protection terminal, an output terminal, an input current sampling terminal, a driver output terminal, an output current sampling terminal and a feedback terminal; The voltage starting terminal is coupled to the DC power supply through a starting circuit; The first switch control terminal is coupled to the common source through a first resistor; the second switch control terminal is coupled to the common gate through a second resistor; The conduction of the first transistor and the second transistor is controlled by a voltage difference between the first switch control terminal and the second switch control terminal; The voltage reference terminal is coupled to the voltage start terminal via a first capacitor and a second capacitor, and the voltage reference terminal outputs a reference voltage; The current setting end is coupled to the voltage reference end via a third resistor and a fourth resistor, and the current setting end is grounded via a fifth resistor; The overcurrent protection terminal is coupled to the voltage reference terminal through an overcurrent protection circuit; The overvoltage protection terminal is coupled to the output terminal of the power supply circuit through an overvoltage protection circuit; Two ends of the input current sampling terminal are coupled to a sixth resistor, one end of the sixth resistor is coupled to the drain of the second transistor, and the other end of the sixth resistor is coupled to the driver output terminal through a third capacitor; The output end is coupled to the positive output end via the first inductor and the seventh resistor; Two ends of the output current sampling terminal are respectively coupled to two ends of the seventh resistor; The feedback end is coupled to a feedback circuit, and is coupled to the positive output end through the feedback circuit.

2. The charge and discharge management circuit according to claim 1, characterized in that: The startup circuit comprises: A first diode, wherein an anode of the first diode is coupled to the output end of the power supply circuit, and a cathode of the first diode is coupled to the voltage start end through an eighth resistor.

3. The charge and discharge management circuit according to claim 1, characterized in that: The overcurrent protection circuit comprises: a ninth resistor, one end of which is coupled to the overcurrent protection terminal, and the other end of which is grounded; A tenth resistor, one end of the tenth resistor is coupled to the overcurrent protection end, and the other end of the tenth resistor is coupled to the voltage reference end through an eleventh resistor.

4. The charge and discharge management circuit according to claim 1, characterized in that: The overvoltage protection circuit comprises: an eleventh resistor, one end of the eleventh resistor being coupled to the output end of the power supply circuit, and the other end of the eleventh resistor being grounded via a twelfth resistor; A connection point between the eleventh resistor and the twelfth resistor is coupled to the overvoltage protection terminal.

5. The charge and discharge management circuit according to claim 1, characterized in that: The feedback circuit comprises: a thirteenth resistor, one end of the thirteenth resistor being coupled to the positive output terminal, and the other end of the thirteenth resistor being grounded and / or coupled to the negative output terminal via a fourteenth resistor; A connection point between the thirteenth resistor and the fourteenth resistor is coupled to the feedback terminal.

6. The charge and discharge management circuit according to claim 1, characterized in that: The management chip further includes: an output control terminal, the output control terminal being grounded via a third capacitor and / or a fourth capacitor; The third capacitor is connected in parallel with the fourth capacitor.

7. The charge and discharge management circuit according to claim 1, characterized in that: The management chip also includes an out-of-time protection terminal, an over-temperature protection terminal and a status indication terminal; The overtime protection terminal is grounded via a fifth capacitor; The over-temperature protection terminal is grounded via a fifteenth resistor; The state indicating terminal outputs an indication signal for indicating whether the state is in a charging state.

8. The charge and discharge management circuit according to claim 1, characterized in that: The input current sampling end includes an input current sampling positive input end and an input current sampling negative input end. The input current sampling positive input end is coupled to one end of the sixth resistor, and the input current sampling negative input end is coupled to the other end of the sixth resistor.

9. The charge and discharge management circuit according to claim 1, characterized in that: The output current sampling end includes an output current sampling positive input end and an output current sampling negative input end, the output current sampling positive input end is coupled to one end of the seventh resistor, and the output current sampling negative input end is coupled to the other end of the seventh resistor; the ratio of the voltage difference between the current sampling positive input end and the output circuit sampling negative input end to the seventh resistor is the actual charging current of the management chip.

10. A charging base, characterized in that: Comprising a charge and discharge management circuit as described in any one of claims 1-9.

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