Semiconductor device testing device and semiconductor device
By connecting the bottom plate of the semiconductor device to the second test pad of the test board, stray inductance is reduced, and the problem of test data deviation in TO247-4 packaged devices is solved, improving the accuracy and testing of test data efficiency.
Patent Information
- Application Number
- CN202420010591.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-03
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-01-03
AI Technical Summary
When conducting dual-pulse testing of semiconductor devices, the devices packaged in TO247-4 are introduced with large stray inductors, which leads to deviations in the test data, affecting the accuracy of the test results.
Design a semiconductor device test device, by connecting the first pin of the device to be tested to the first test pad of the test board, connecting the bottom plate of the device to be tested to the second test pad of the test board, lowering the pin The stray inductance brought by the connection.
By reducing stray inductance, reducing the amplitude and ringing time of the test waveform, improving the accuracy and test efficiency of the test data.
Smart Images
Figure CN222482367U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of packaged device testing, and in particular to a semiconductor device testing apparatus and a semiconductor device. Background Art
[0002] At present, the third-generation semiconductor silicon carbide field effect transistor (SiC MOS) has become the mainstream choice for power devices. As the switching speed of field effect transistors increases, the parasitic inductance generated by the source bonding wires in the package has an increasingly serious adverse effect on the switching speed. The TO247-4 package can perform Kelvin connection on the signal source terminal of the gate drive, thereby improving the efficiency of the entire system and enabling the device to operate at a lower temperature.
[0003] In view of the switching speed of SiC MOS, especially the single chip in TO247-4 package, a large stray inductance will be introduced during the double pulse test, resulting in deviation in the test data. Therefore, in actual testing, it is necessary to ensure that the stray inductance of the test environment is low enough to eliminate the impact of this factor as much as possible. Utility Model Content
[0004] Based on this, it is necessary to provide a semiconductor device testing device and a semiconductor device to address the problems in the above-mentioned background technology, reduce the stray inductance caused by packaging, improve the accuracy of test data, and improve the yield of the device.
[0005] To achieve the above-mentioned purpose and other purposes, according to various embodiments of the present application, the first aspect of the present application provides a semiconductor device testing device, including a test board and a pulse device, the test board is used to perform electrical testing on the device under test; the test board includes a first test pad and a second test pad, the first test pad is used to connect the first pin of the device under test; the second test pad is used to connect the bottom plate of the device under test; the pulse device is connected to the test board, and is used to provide a pulse test signal to the device under test.
[0006] The semiconductor device test device in the above embodiment performs electrical testing on the device to be tested through a test board; the test board includes a first test pad and a second test pad, and the first pin of the device to be tested is connected through the first test pad; the bottom plate of the device to be tested is connected through the second test pad; and a pulse test signal is provided to the device to be tested through a pulse device connected to the test board. At present, the related semiconductor device test device inserts the pins of the packaged semiconductor device into the printed circuit board (PCB) by direct insertion to perform the test. The package stray inductance introduced during the test process only comes from the pins. The stray inductance introduced by the pins increases with the increase of the pins, resulting in deviations in the test data and affecting the test results of the packaged device. The semiconductor device test device in the embodiment of the present application reduces the stray inductance caused by the pin connection by connecting the first pin of the device to be tested to the first test pad of the test and connecting the bottom plate of the device to be tested to the second test pad of the test board, thereby reducing the amplitude and ringing time of the test waveform, improving the accuracy of the test data, and improving the test efficiency.
[0007] In some embodiments, the test board also includes a third test pad and a fourth test pad, the third test pad is used to connect the third pin of the device under test; the fourth test pad is used to connect the fourth pin of the device under test; the device under test is configured as: after the first pulse test signal controls the device under test to turn on, and before the second pulse test signal is input to the source of the device under test, it is in a closed state.
[0008] In some embodiments, the pulse device includes a first signal terminal and a second signal terminal. The first signal terminal is used to input a first pulse test signal to the source of the device under test to control the device under test to be turned on; the second signal terminal is used to input a second pulse test signal to the source of the device under test within a preset time to control the device under test to be turned on again.
[0009] In some embodiments, the semiconductor device testing apparatus further includes a display connected to the testing board for displaying the test result of the device.
[0010] In some embodiments, the semiconductor device testing apparatus further includes a monitoring device, which is connected to both the testing board and the display and is used to monitor whether the test result of the device is within a preset range.
[0011] The second aspect of the present application provides a semiconductor device, including a semiconductor chip, a base plate and a packaging shell; the base plate is used to connect to a second test pad of a test board; and the packaging shell is used to provide physical protection for the semiconductor chip.
[0012] In some embodiments, the semiconductor device uses TO247-4 packaging to package the semiconductor chip; wherein the source of the semiconductor chip is led out from the first pin of the package; the drain is led out from the package bottom plate, and the bottom plate is connected to the second pin; and the gate is led out from the third pin of the package.
[0013] In some embodiments, the base plate includes a heat sink connected to the second pin for dissipating heat generated by the semiconductor chip during operation.
[0014] In some embodiments, the heat dissipation plate includes heat dissipation holes, and the heat dissipation holes are used to disperse the heat generated inside the semiconductor device.
[0015] In some embodiments, a semiconductor device is tested using the semiconductor device testing apparatus in any of the above embodiments.
[0016] The semiconductor device in the above embodiment includes a semiconductor chip, a base plate and a package shell; the base plate is connected to the second test pad of the test board; the package shell provides physical protection for the semiconductor chip; the semiconductor device is connected to the test board for testing, wherein the second test pad of the test board is connected to the base plate of the semiconductor device; a pulse test signal is provided to the semiconductor device through a pulse device connected to the test board, and the first pulse test signal is input to the source of the device to be tested through the first signal end of the pulse device to control the semiconductor device to be turned on; the second pulse test signal is input to the source of the semiconductor device within a preset time through the second signal end of the pulse device to control the semiconductor device to be turned on again; the heat generated inside the package is dispersed through the heat sink in the base plate. At present, the relevant semiconductor devices directly insert each pin into the printed circuit board for testing, and the stray inductance introduced by the pin increases with the increase of the pin, resulting in deviation of the test data, affecting the test results of the packaged device. The semiconductor device in the embodiment of the present application reduces the stray inductance caused by the pin connection by connecting the base plate to the second test pad of the test board, reduces the amplitude and ringing time of the test waveform, improves the accuracy of the test data, and improves the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 A schematic diagram of a structural block diagram of a semiconductor device testing device provided in an embodiment of the present application;
[0019] Figure 2A schematic diagram of a structural block diagram of a semiconductor device testing device provided in another embodiment of the present application;
[0020] Figure 3 A schematic diagram of a structural block diagram of a semiconductor device testing device provided in yet another embodiment of the present application;
[0021] Figure 4 A schematic diagram of a structural block diagram of a semiconductor device testing device provided in another embodiment of the present application;
[0022] Figure 5 A schematic top view of a packaged semiconductor device provided in an embodiment of the present application;
[0023] Figure 6 A schematic diagram of a structural block diagram of a semiconductor device provided in an embodiment of the present application;
[0024] Figure 7 A cross-sectional schematic diagram of the connection between a semiconductor device and a test board provided in an embodiment of the present application;
[0025] Figure 8 A schematic diagram of a structural block diagram of a semiconductor device provided in another embodiment of the present application;
[0026] Fig. 9 A schematic diagram of a structural block diagram of a semiconductor device provided in yet another embodiment of the present application.
[0027] Description of reference numerals:
[0028] 100, semiconductor device testing device; 110, test board; 111, first test pad; 112, second test pad; 113, third test pad; 114, fourth test pad; 120, pulse device; 121, first signal terminal; 122, second signal terminal; 130, display; 140, monitoring device; 200, semiconductor device; 210, semiconductor chip; 220 / 22, base plate; 221, heat sink; 2211, heat dissipation hole; 230, package shell; 231 / 21, first pin; W, base plate width; I, base plate thickness; W', pin width; I', pin length; 20, device under test; 23, third pin; 24, fourth pin. DETAILED DESCRIPTION
[0029] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the application content of the present application more thorough and comprehensive.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0031] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0032] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be construed as being one in number.
[0033] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0034] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.
[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.
[0036] Power switching devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT) are widely used in power electronic equipment in new energy vehicles, industry, medical, transportation, consumer and other industries, directly affecting the cost and efficiency of these power electronic equipment.
[0037] Compared with traditional silicon MOSFET and silicon IGBT products, SiCMOSFET designed based on wide bandgap silicon carbide (SiC) materials has the characteristics of high withstand voltage, low on-resistance, and low switching loss, which can reduce device loss and product size, thereby improving system efficiency. In practical applications, the TO-247-4 package with auxiliary source pins is more suitable for new high-frequency devices such as SiC MOSFET. It can further reduce the switching loss of the device and is more conducive to the drive design of discrete devices.
[0038] At present, the double pulse test of TO247-4 packaged devices is mainly carried out using PCB test boards. The stray inductance introduced during the test is mainly introduced by the busbar capacitance, PCB circuits and device pins. The current mainstream test method is to use the device pins to directly insert into the PCB board for testing. The main package stray inductance Ls introduced by the device comes from the device pins, and the stray inductance Ls introduced by the pins will increase with the increase of the pin length, which will affect the test data.
[0039] Based on this, please refer to Figure 1 The embodiment of the present application provides a semiconductor device testing device 100, including a test board 110 and a pulse device 120. The test board 110 is used to perform electrical testing on the device under test 20; the test board 110 includes a first test pad 111 and a second test pad 112, the first test pad 111 is used to connect the first pin 21 of the device under test 20; the second test pad 112 is used to connect the bottom plate of the device under test 20; the pulse device 120 is connected to the test board 110, and is used to provide a pulse test signal to the device under test 20.
[0040] As an example, please refer to Figure 1, the semiconductor device testing device 100 performs electrical testing on the device under test 20 through the testing board 110; the testing board 110 includes a first testing pad 111 and a second testing pad 112, and the first pin 21 of the device under test 20 is connected through the first testing pad 111; the bottom plate 22 of the device under test 20 is connected through the second testing pad 112; and a pulse testing signal is provided to the device under test 20 through a pulse device 120 connected to the testing board 110. At present, the related semiconductor device testing device inserts the pins of the packaged semiconductor device into the printed circuit board by direct insertion to perform the test. During the test process, the package stray inductance introduced only comes from the pins. The stray inductance introduced by the pins increases with the increase of the pins, resulting in deviations in the test data and affecting the test results of the packaged device. The semiconductor device testing device 100 in the embodiment of the present application reduces the stray inductance caused by the pin connection, reduces the amplitude and ringing time of the test waveform, improves the accuracy of the test data, and improves the test efficiency by connecting the first pin 21 of the device under test 20 to the first test pad 111 of the test board 110 and connecting the base plate 22 of the device under test 20 to the second test pad 112 of the test board 110.
[0041] In some embodiments, please refer to Figure 2 The test board 110 also includes a third test pad 113 and a fourth test pad 114, the third test pad 113 is used to connect the third pin 23 of the device under test 20; the fourth test pad 114 is used to connect the fourth pin 24 of the device under test 20; the device under test 20 is configured as: after the first pulse test signal controls the device under test 20 to be turned on, before the second pulse test signal is input to the source of the device under test 20, it is in a closed state.
[0042] In some embodiments, the first pin may be a source pin; the second pin may be a drain pin, which is connected to the bottom plate of the device under test; the third pin may be a gate pin; and the fourth pin may be a Kelvin pin, through which the pin inductance on the gate control loop can be bypassed, thereby increasing the switching speed of the semiconductor device and reducing the switching energy.
[0043] In some embodiments, please refer to Figure 3 The pulse device 120 includes a first signal terminal 121 and a second signal terminal 122. The first signal terminal 121 is used to input a first pulse test signal to the source of the device under test 20 to control the device under test 20 to be turned on; the second signal terminal 122 is used to input a second pulse test signal to the source of the device under test 20 within a preset time to control the device under test 20 to be turned on again.
[0044] As an example, see Figure 4The semiconductor device testing apparatus 100 further includes a display 130 , which is connected to the testing board 110 and is used to display the testing result of the device.
[0045] As an example, please refer to Figure 4 The semiconductor device testing device 100 further includes a monitoring device 140 , which is connected to both the testing board 110 and the display 130 , and is used to monitor whether the test result of the device is within a preset range.
[0046] In some embodiments, please refer to Figure 5 , the stray inductance of the semiconductor device is calculated according to the following formula:
[0047] ; (1)
[0048] Wherein, Ls is the stray inductance, I is the thickness of the bottom plate (not shown), and W is the width of the bottom plate. Compared with the related semiconductor device test device, the pins of the device to be tested are inserted into the test board by direct insertion for testing. The semiconductor test device in the embodiment of the present application connects the bottom plate of the device to be tested to the test board, the width W' of the pin is smaller than the width W of the bottom plate, and the length I' of the pin is larger than the thickness I of the bottom plate. By increasing the width and reducing the length, the stray inductance caused by the package is reduced, and the reliability of the test data is improved.
[0049] As an example, see Figure 6-Figure 7 , a semiconductor device 200 is provided, including a semiconductor chip 210, a base plate 220 and a packaging shell 230; the base plate 220 is used to connect the second test pad 112 of the test board 110; the packaging shell 230 is used to provide physical protection for the semiconductor chip 210.
[0050] In some embodiments, the package shell may include a first pin, a second pin, a third pin and a fourth pin, wherein the first pin may be a source pin connected to the source of the semiconductor chip; the second pin may be a drain pin connected to the drain of the semiconductor chip, and the drain pin is connected to the base plate; the third pin may be a gate pin connected to the gate of the semiconductor chip; and the fourth pin may be a Kelvin pin, through which the pin inductance on the gate control loop can be bypassed, thereby increasing the switching speed of the semiconductor device and reducing the switching energy.
[0051] In some embodiments, please refer to Figure 7 The semiconductor device 200 uses a TO247-4 package to package the semiconductor chip 210; wherein the source of the semiconductor chip 210 is led out by the first package pin 231; the drain is led out by the package bottom plate, which is connected to the second pin; and the gate is led out by the third package pin (not shown). The first pin 231 is connected to the first test pad 111.
[0052] In some embodiments, please refer to Figure 8 The base plate 220 includes a heat sink 221, which is connected to the second pin and is used to dissipate the heat generated by the semiconductor chip when it is working.
[0053] In some embodiments, please refer to Fig. 9 The heat dissipation plate 221 includes heat dissipation holes 2211, and the heat dissipation holes 2211 are used to disperse the heat generated inside the semiconductor device.
[0054] In some embodiments, a semiconductor device is tested using the semiconductor device testing apparatus in any of the above embodiments.
[0055] As an example, see Figure 6-Figure 9 The semiconductor device 200 includes a semiconductor chip 210, a base plate 220 and a packaging shell 230; the base plate 220 is connected to the second test pad 112 of the test board 110; the packaging shell 230 provides physical protection for the semiconductor chip 210; the semiconductor device 200 is connected to the test board 110 for testing, wherein the second test pad 112 of the test board 110 is connected to the base plate 220 of the semiconductor device 200; a pulse test signal is provided to the semiconductor device 200 through a pulse device connected to the test board 110, and the first pulse test signal is input to the source of the semiconductor device 200 through the first signal terminal of the pulse device to control the semiconductor device 200 to be turned on; a second pulse test signal is input to the source of the semiconductor device 200 within a preset time through the second signal terminal of the pulse device, and the semiconductor device 200 is controlled to be turned on again; and the heat generated inside the package is dispersed through the heat sink 221 in the base plate 220. At present, for related semiconductor devices, each pin is directly inserted into the printed circuit board for testing. The stray inductance introduced by the pin increases with the increase of the pin, resulting in deviation of the test data and affecting the test results of the packaged device. The semiconductor device 200 in the embodiment of the present application reduces the stray inductance caused by the pin connection by connecting the bottom plate 220 to the second test pad 112 of the test board 110, reduces the amplitude and ringing time of the test waveform, improves the accuracy of the test data, and improves the test efficiency.
[0056] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0057] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0058] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A semiconductor device testing device, characterized in that: include: A test board, used for performing electrical testing on a device under test; the test board comprises a first test pad and a second test pad, the first test pad is used for connecting a first pin of the device under test; the second test pad is used for connecting a bottom plate of the device under test; A pulse device is connected to the test board and is used to provide a pulse test signal to the device under test, wherein the pulse test signal includes a first pulse test signal and a second pulse test signal, the first pulse test signal is used to input to the source of the device under test to control the device under test to be turned on, and the second pulse test signal is used to input to the source of the device under test to control the device under test to be turned on again.
2. The semiconductor device testing device according to claim 1, characterized in that: The test board also includes: A third test pad, used for connecting a third pin of the device under test; A fourth test pad, used for connecting a fourth pin of the device under test; The device under test is configured to be in a closed state after the first pulse test signal controls the device under test to be turned on and before the second pulse test signal is input to a source of the device under test.
3. The semiconductor device testing device according to claim 2, characterized in that: The pulse device comprises: A first signal terminal, used for inputting a first pulse test signal to a source of the device under test to control the device under test to be turned on; The second signal terminal is used to input a second pulse test signal to the source of the device under test within a preset time, so as to control the device under test to be turned on again.
4. The semiconductor device testing device according to claim 3, characterized in that: Also includes: A display is connected to the test board and is used to display the test result of the device.
5. The semiconductor device testing device according to claim 4, characterized in that: Also includes: A monitoring device is connected to the test board and the display, and is used to monitor whether the test result of the device is within a preset range.
6. A semiconductor device, characterized in that: The semiconductor device testing device according to any one of claims 1 to 5 is used for testing, comprising: Semiconductor chips; A base plate, used for connecting a second test pad of the semiconductor device testing device; The packaging shell is used to provide physical protection for the semiconductor chip.
7. The semiconductor device according to claim 6, characterized in that The semiconductor device uses TO247-4 packaging to package the semiconductor chip.
8. The semiconductor device according to claim 7, characterized in that The source of the semiconductor chip is led out from the first pin of the package; the drain is led out from the bottom plate of the package, and the bottom plate is connected to the second pin; and the gate is led out from the second pin of the package.
9. The semiconductor device according to claim 8, characterized in that The bottom plate comprises: A heat sink is connected to the second pin and is used to dissipate the heat generated by the semiconductor chip when it is working.
10. The semiconductor device according to claim 9, characterized in that The heat sink comprises: The heat dissipation holes are used to disperse the heat generated inside the semiconductor device.