In-memory computing circuit and device with redundancy design and electronic equipment

Abstract

The utility model discloses an in-memory computing circuit with redundancy design, an in-memory computing device and electronic equipment. The in-memory calculation circuit comprises a simulation storage and calculation module and a controller, wherein the simulation storage and calculation module comprises a plurality of simulation storage and calculation unit rows and at least one redundancy storage and calculation unit row; and the controller is respectively connected with the simulation storage and calculation unit row and the redundancy storage and calculation unit row. According to the invention, the mode of arranging the redundant storage and calculation unit rows in each simulation storage and calculation module is more flexible, the area cost is lower, the effect of replacing and avoiding error data when dead pixels exist in each simulation storage and calculation module is achieved, the time and cost of re-casting production can be saved, and the production efficiency is improved. And the area of the redundant replacement mode of the whole storage and calculation integrated chip architecture can be saved, and the repair rate of the dead pixels is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an in-memory computing circuit, device and electronic device with redundant design. Background Art

[0002] As Moore's Law gradually approaches its limit, the "storage wall" and "power consumption wall" problems of artificial intelligence (AI) chips based on the von Neumann architecture are becoming increasingly prominent, and the growth rate of chip computing power is becoming slower and slower. Against this background, the emerging chip architecture of computing-in-memory (CIM) is gradually emerging, providing the next generation of artificial intelligence chips with greater computing power and better energy efficiency. The computing-in-memory architecture can be understood as embedding computing power in the memory, performing two-dimensional and three-dimensional matrix multiplication / addition operations with a new computing architecture, rather than optimizing on traditional logic operation units or processes. This can essentially eliminate unnecessary data movement delays and power consumption, improve the computing efficiency of artificial intelligence by hundreds or thousands of times, reduce costs, and break the "storage wall" and "power consumption wall".

[0003] Storage and computing integration aims to overcome the "memory wall" problem by integrating storage and computing functions on the same chip. The basic idea is to move data calculations to the memory units that store data, thereby achieving in-situ computing and eliminating bandwidth limitations and data movement costs. This technology embeds computing power in the memory and adopts a new computing architecture to achieve matrix-vector multiplication and accumulation operations. The advantage of storage and computing integration technology is that it can reduce the additional energy consumption caused by data movement and improve the efficiency of parallel data processing. This technology is not only suitable for artificial intelligence computing, but can also be applied to sensor-storage-computing integrated chips and brain-like chips, representing the mainstream direction of big data computing in the future.

[0004] Regarding the implementation of computing in the integrated storage and computing chip architecture, there are two main existing implementation architectures: digital computing architecture and analog computing architecture. The digital computing architecture refers to the cumulative sum of the matrix-vector product obtained by cascading a multi-level addition tree through the product of the stored data in the in-memory computing unit matrix and the input vector data. The analog computing architecture refers to the cumulative sum of the stored data in the in-memory computing unit matrix and the input vector data, which is then converted into a digital signal by an analog-to-digital converter (ADC). Among them, the physical implementation of the analog in-memory computing circuit has a smaller chip area and lower computing power consumption than the physical implementation of the digital in-memory computing circuit.

[0005] When the existing traditional integrated storage and computing chip architecture adopts an analog computing architecture, as the chip area expands and more large-capacity storage and computing chips or storage and computing modules are used, the production yield of large-area repeated storage and computing units will decrease, which will affect the production yield of the entire chip, causing functional problems or the need for re-production. In order to improve the yield of large-area repeated storage and computing units, the integrated storage and computing chip architecture adopts a redundant design.

[0006] However, the existing chip redundancy design is to use a storage-computing module or a storage-computing chip as a backup redundant module, and place multiple redundant modules in the storage-computing chip architecture. When a module or a unit in the storage-computing chip architecture has a production yield problem, it is necessary to call an entire redundant module to replace it as a whole, that is, the entire storage-computing chip or module is used as the minimum backup redundant module. After placing a certain amount of this type of redundant modules, it will occupy more chip area and cost. Even if a bad point appears in a storage-computing unit, it is necessary to call the entire redundant module for replacement. Therefore, the entire storage-computing chip or module containing the redundant module has a large area and high cost, and the redundant design method is not flexible enough. Utility Model Content

[0007] The purpose of this application is to provide an in-memory computing circuit, device and electronic device with redundant design to at least solve the above technical problems. The preferred technical solutions among the many technical solutions provided by the utility model can produce many technical effects as described below.

[0008] To achieve the above-mentioned object, in a first aspect, the present application provides an in-memory computing circuit with a redundant design, the in-memory computing circuit comprising: a plurality of analog memory computing modules and a controller, the plurality of analog memory computing modules being arranged in a matrix;

[0009] The simulation storage and calculation module includes a plurality of simulation storage and calculation unit rows and at least one redundant storage and calculation unit row;

[0010] The controller is connected to the analog storage and computing unit row and the redundant storage and computing unit row respectively;

[0011] The controller is used to determine whether there is a bad pixel in the analog storage and computing cell row and the first storage and computing cell row where the bad pixel is located. If the first storage and computing cell row exists, the controller sends a control signal from the first storage and computing cell row to the redundant storage and computing cell row based on the first storage and computing cell row; the control signal is used to set the plate of the capacitor of the first storage and computing cell row to a high potential or a low potential so that the data in the first storage and computing cell row does not affect the potential on the plate of the capacitor, and to make the external data respectively connected to the first storage and computing cell row to the third storage and computing cell row be replaced row by row along the setting direction of the first storage and computing cell row to the redundant storage and computing cell row, and to replace the storage data expected to be written from the first storage and computing cell row to the third storage and computing cell row to be written from the second storage and computing cell row to the redundant storage and computing cell row row by row along the setting direction of the first storage and computing cell row to the redundant storage and computing cell row;

[0012] The second storage unit row to the redundant storage unit row respectively perform multiplication calculations based on the replaced storage data and the external data, and accumulate the results of the multiplication calculations from the second storage unit row to the redundant storage unit row based on the capacitor to obtain a simulated multiplication and accumulation result;

[0013] Among them, the second storage computing unit row is adjacent to the first storage computing unit row, the third storage computing unit row is adjacent to the redundant storage computing unit row, and the second storage computing unit row and the third storage computing unit row are located between the first storage computing unit row and the redundant storage computing unit row.

[0014] The present application also provides a processing device, comprising the in-memory computing circuit with redundant design as described in any one of the first aspects.

[0015] The present application also provides an electronic device, comprising the in-memory computing circuit with redundant design as described in any one of the first aspects.

[0016] Implementing one of the above technical solutions of this application has the following advantages or beneficial effects:

[0017] The in-memory computing circuit, device and electronic device with redundant design of the present application, the in-memory computing circuit includes several analog storage computing modules and controllers, each analog storage computing module includes at least one row of redundant storage computing unit rows, and there is no need to set up multiple redundant analog storage computing modules; the controller is connected to several analog storage computing unit rows and redundant storage computing unit rows in the analog storage computing module, and when any analog storage computing module determines that there is a first storage computing unit row where a bad point is located, the controller shields the data of the first storage computing unit row where the bad point is located, which can avoid the data of the bad point row; the redundant storage computing unit row in the analog storage computing module is used to replace the data of the first storage computing unit row, and the entire analog storage computing module does not need to be replaced as a whole. The replaced data is used for multiplication calculation and capacitance accumulation, which can avoid the influence of the bad point on the capacitance calculation, ensure the accuracy of the multiplication and accumulation results after the redundant storage computing unit row replaces the first storage computing unit row, and will not affect the use of the analog storage computing module. Moreover, the method of setting up redundant storage and computing unit rows in each analog storage and computing module is more flexible, and can consume less area and cost, so that bad points in each analog storage and computing module can be replaced and erroneous data can be avoided. This can not only save the time and cost of re-production, but also save the area of ​​the redundant replacement method of the overall storage and computing integrated chip architecture, and improve the repair rate of bad points. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. It is obvious that the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 It is a schematic diagram of the structure of an in-memory computing circuit with a redundant design according to an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of an in-memory computing circuit simulated in an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of a simulation storage and computing unit row in an embodiment of the present application;

[0022] Figure 4 A circuit diagram of a data converter according to an embodiment of the present application;

[0023] Figure 5 is a circuit diagram of a redundant data converter according to an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the architecture of the analog in-memory computing circuit according to an embodiment of the present application.

[0025] In the figure: 1. analog in-memory computing circuit; 11. analog memory computing module; 12. controller; 111. analog memory computing unit row; 112. redundant memory computing unit row; 113. first memory computing unit row; 1110. analog memory computing unit of bad point; 1111. analog memory computing unit; 1112. row data converter; 1113. row register; 1114. transmission gate. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present application clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the present application are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods, and devices that are consistent with some aspects disclosed in the present application as detailed in the attached claims, and other embodiments may also be used, or the embodiments listed herein may be modified in structure and function without departing from the scope and essence of the present application.

[0027] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0028] In order to illustrate the technical solution described in the present application, a specific embodiment is provided below, and only the parts related to the embodiment of the present application are shown.

[0029] Embodiment 1:

[0030] The in-memory computing circuit with redundant design can be a memory-computing integrated chip architecture, which can exist in the form of a chip or a common circuit module. In addition, the in-memory computing circuit with redundant design of the present application is an analog computing architecture. The analog computing architecture can improve energy efficiency, occupy less power consumption and circuit area, and can carry a variety of memories.

[0031] like Figure 1 As shown, the present application provides an in-memory computing circuit 1 with a redundant design, and the in-memory computing circuit 1 with a redundant design includes a plurality of analog storage computing modules 11 and a controller 12. The plurality of analog storage computing modules 11 are arranged in a matrix. Figure 1 In the example, the analog storage and computing modules 11 are arranged in a 4*3 matrix.

[0032] See also Figures 1 to 6 The analog storage and computing module 11 includes at least several rows of analog storage and computing unit rows 111 and at least one row of redundant storage and computing unit rows 112, and the controller 12 is respectively connected to the analog storage and computing unit rows 111 and the redundant storage and computing unit rows 112. The internal circuit structures and parameters of the analog storage and computing unit rows 111 and the redundant storage and computing unit rows 112 are basically similar. Each row of analog storage and computing unit rows 111 includes at least one analog storage and computing unit 1111, and similarly, the redundant storage and computing unit rows 112 include at least one analog storage and computing unit 1111.

[0033] In some embodiments, the redundant storage and computing unit row 112 is located in the top row or the bottom row of the analog storage and computing module 11. Taking the redundant storage and computing unit row 112 as a row as an example, the redundant storage and computing unit row 112 can be located in the outermost row of the analog storage and computing module 11, such as the first row or the last row. Figure 1 Counting from top to bottom along the first direction A1, the redundant storage and computing unit row 112 may be located at the last row of the analog storage and computing module 11, which is the bottom row. Figure 2 In the embodiment, the redundant storage and computing unit row 112 is located in the first row of the analog storage and computing module 11, which is the top row. Of course, one redundant storage and computing unit row 112 can also be located between any two analog storage and computing unit rows 111, which is not limited here. Moreover, the number of redundant storage and computing unit rows 112 can be more than one row, which can be set according to the empirical number of analog storage and computing unit rows 111 with bad points during production, such as 2 rows, 3 rows, etc., which is not limited here.

[0034] The setting of the redundant storage and computing unit row 112 makes the data of the first storage and computing unit row 113 where the bad point is located more flexible when replacing, and there is no need to simulate the overall replacement of the storage and computing module 11.

[0035] Furthermore, the redundant storage and computing unit row 112 is located at the top row or the bottom row of the analog storage and computing module 11 to facilitate production and manufacturing.

[0036] The controller 12 is used to determine whether there is a bad pixel in the analog storage unit row 111 and the specific analog storage unit row where the bad pixel is located (the analog storage unit row of the row is the first storage unit row 113); if the first storage unit row 113 exists, the controller 12 sends a control signal from the first storage unit row 113 to the redundant storage unit row 112 based on the first storage unit row 113, and the control signal is used to set the plate of the capacitor of the first storage unit row 113 to a high potential or a low potential, so that the data in the first storage unit row does not affect the capacitor. The electric potential on the electrode plate is affected, and it is used to replace the external data connected to the first storage computing unit row 113 to the third storage computing unit row, row by row, along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112, connected to the second storage computing unit row to the redundant storage computing unit row 112, and to replace the storage data expected to be written into the first storage computing unit row 113 to the third storage computing unit row, row by row, along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112.

[0037] Among them, the second storage computing unit row is adjacent to the first storage computing unit row 113, the third storage computing unit row is adjacent to the redundant storage computing unit row 112, and the second storage computing unit row and the third storage computing unit row are located between the first storage computing unit row 113 and the redundant storage computing unit row 112.

[0038] Specifically, when the in-memory computing circuit 1 with a redundant design is produced, it is necessary to test the storage and computing performance of each analog storage computing unit 1111 in the analog storage computing module 11 to detect whether each analog storage computing unit 1111 has a bad point. Figure 1 The 1110 in the figure represents a bad analog storage computing unit, and the bad node may affect the function or performance of the in-memory computing circuit 1 with redundant design.

[0039] In some embodiments, the controller 12 sends a control signal from the first storage computing unit row 113 to the redundant storage computing unit row 112 based on the first storage computing unit row 113, which may include:

[0040] The controller 12 obtains address information of the first storage and computing unit row 113, and sends a first control signal according to the address information of the first storage and computing unit row 113, wherein the first control signal enables the first storage and computing unit row 113 to perform data shielding;

[0041] Obtain the row address of each row from the first storage and computing unit row 113 to the redundant storage and computing unit row 112;

[0042] The controller 12 sends a second control signal to the second storage computing unit row to the redundant storage computing unit row 112 in sequence based on the row addresses of the first storage computing unit row 113 to the redundant storage computing unit row 112, and the second control signal enables the second storage computing unit row to the redundant storage computing unit row to perform the row-by-row replacement.

[0043] Specifically, the controller 12 knows in advance the addresses of each analog storage unit 1111 and the redundant storage unit, and therefore, the controller 12 knows in advance the addresses of each analog storage unit row 111 and the redundant storage unit row 112. During the test, if a bad pixel is found, the controller 12 determines the address information of the first storage unit row 113 where the bad pixel is located. According to the address information of the first storage unit row 113, the controller 12 sends a first control signal to the first storage unit row 113, and the first control signal causes the first storage unit row 113 to shield the data, so that the data of the first storage unit row 113 does not participate in the multiplication and accumulation related calculations, thereby not affecting the overall simulated multiplication and accumulation results of the analog storage module 11.

[0044] It is understandable that the present application is not limited to the calculation of capacitor charge, but may also be the calculation of capacitor current, which is not limited here.

[0045] The control signal is also used to replace the external data connected to the first storage computing unit row 113 to the third storage computing unit row, row by row, along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112, and connect them to the second storage computing unit row to the redundant storage computing unit row 112.

[0046] Specifically, the controller 12 also obtains the row addresses of each row from the first storage computing unit row 113 to the redundant storage computing unit row 112; based on the row addresses of the first storage computing unit row 113 to the redundant storage computing unit row 112, the controller 12 sequentially sends a second control signal to the second storage computing unit row to the redundant storage computing unit row 112, and the second control signal is used to make the second storage computing unit row to the redundant storage computing unit row 112 perform the row-by-row replacement. That is, when the second storage computing unit row to the redundant storage computing unit row 112 receives the second control signal, the external data connecting the first storage computing unit row 113 to the third storage computing unit row and the storage data expected to be written from the first storage computing unit row 113 to the third storage computing unit row are replaced row by row to the second storage computing unit row to the redundant storage computing unit row 112 according to the row address.

[0047] When replacing row by row, the controller 12 follows the setting direction from the first storage and computing unit row 113 to the redundant storage and computing unit row 112, for example, Figure 1In the A1 direction, the second storage unit line is the analog storage unit line 111 of the adjacent row starting from the first storage unit line 113, and the external data connected to the first storage unit line 113 is converted along the A1 direction to the row address of the second storage unit line, and so on, until it is replaced to the row address of the redundant storage unit line 112. The method of replacing the stored data is similar to the method of replacing the external data, and both are based on the row address for data replacement, which will not be repeated here.

[0048] In some embodiments, Figure 3 and Figure 4 As shown, the analog storage and computing unit row 111 includes a row data converter 1112, a row register 1113 and an analog storage and computing unit 1111. The row data converter 1112 includes a signal enable port E[N], an external connection port D[N] and a conversion selection port S[N], as well as a first connection terminal DO, a second connection terminal DO and a third connection terminal DS. N represents the number of rows.

[0049] The signal enable port E[N] of the row data converter 1112 and the output end of the analog storage and computing unit 1111 are both connected to the controller 12, the first connection end DO of the row data converter 1112 is connected to the input end of the row register 1113, and the output end of the row register 1113 is connected to the input end of the analog storage and computing unit 1111; the third connection end DS of the row data converter 1113 is connected to the second connection end DO of the row data converter 1113 of the analog storage and computing unit row 111 of the adjacent row.

[0050] The row register 1113 may be a D flip-flop, which uses the external input data D as a multiplier during calculation, and stores it stably within one clock cycle and transmits it to the analog storage and calculation unit 1111 for multiplication.

[0051] Furthermore, the controller 12 can connect the external data to the external connection port D[N] of the row data converter 1112 as a signal D for calculating the capacitive charge of the analog storage unit row 111 .

[0052] The multiplication calculation and charge sampling process of each row of analog storage units 1111 specifically includes: multiplying the input external data D with the storage data in the corresponding row of analog storage units 1111, and reflecting the product to the first plate P1 of the corresponding summing capacitor CP; after the voltage of the first plate P1 of the summing capacitor reaches, the sampling of the corresponding row charge is started, and the sampled charge is fed back to the second plate P2 of the summing capacitor; the second plate P2 of the summing capacitor accumulates the product charge to the signal line of the current row, and summarizes it to Figure 6 The main signal line SL in.

[0053] like Figure 4As shown, the row data converter 1112 includes a transmission gate 1114, a first inverter DC1, and a first MOS transistor NM1; the first inverter DC1 is connected to the signal enable port E; the external connection port D[N] is connected to two transmission gates 1114, one transmission gate 1114 is connected to the third connection terminal DS of the row data converter 1112 to connect the second connection terminal DO of the row data converter 1112 of the adjacent analog storage unit row 111, and the other transmission gate 1114 is connected to the first connection terminal DO, the second connection terminal DO and the drain of the first MOS transistor NM1 of the row data converter 1112, and the first connection terminal DO is connected to the input port of the row register 1113. The gate of the first MOS transistor NM1 is connected to the signal enable port E[N] of the row data converter 1112, and the source of the first MOS transistor NM1 is connected to the common ground terminal VSS. The first inverter DC1 is connected to the conversion selection port S[N], which is used to control the switch of the transmission gate 1114 to select the external data D to be output from the second connection terminal DO or the third connection terminal DS.

[0054] The first MOS transistor NM1 is an N-type MOS transistor. In the first inverter DC1, the signal SN is an inverted signal of the signal S via the first inverter DC1, and together with the signal S, controls the switches of the two transmission gates 1114 to select the transmission path of the external data D.

[0055] The controller 12 may input a first enable signal or a second enable signal to the signal enable port E[N] of the row data converter 1112. The first enable signal may be "1" and the second enable signal may be "0". When the controller 12 sets the signal enable port E[N] of the row data converter 1112 to "1", the row data converter 1112 converts the first enable signal "1" into the second enable signal "0" and then outputs it to the row register 1113. The row data converter 1112 may be configured as follows: Figure 4 As shown, when it is necessary to shield the data of the first storage and computing unit row 113, when the first control signal of the controller 12 sets the signal enable port E[N] to "1", the first MOS tube NM1 is turned on, and the controller 12 inputs the first selection signal "1" to the conversion selection port S[N]. After the cooperation of the transmission gate 1114 and the first inverter DC1, the first connection terminal DO of the row data converter 1112 outputs "0", which is a shielding signal. After the shielding signal is transmitted to the analog storage and computing unit 1111, no matter whether the stored erroneous data is '1' or '0', it is shielded by the shielding signal, and does not change the charge of the capacitor Cp, and does not affect the multiplication and accumulation related calculation results.

[0056] In some embodiments, the plate of the capacitor CP of the first storage and computing unit row 113 can be set to a high potential or a low potential that does not affect the charge CP calculation, so that the data in the first storage and computing unit row 113 does not affect the potential of the plate, thereby achieving data shielding of the first storage and computing unit row 113.

[0057] On the contrary, for the analog storage and computing unit row that does not need to replace data and mask data, when the controller 12 sets the signal enable port E[N] to "0", the first MOS tube NM1 is turned off, and the controller 12 inputs the first selection signal "0" to the conversion selection port S[N]. After the cooperation of the transmission gate 1114 and the first inverter DC1, the first connection terminal DO of the row data converter 1112 outputs "1". After the control signal is transmitted to the analog storage and computing unit 1111, the data will not be masked, and the change in the charge of the capacitor Cp can be calculated.

[0058] The row data converters 1112 of each adjacent row are interconnected by connecting the previous adjacent row or the next adjacent row to the first connecting terminal DO via the second connecting port DS.

[0059] The controller 12 can input a first selection signal or a second selection signal to the conversion selection port S[N] of the row data converter 1112. The first selection signal can be "1" and the second selection signal can be "0". When the controller 12 sets the conversion selection port S[N] of the row data converter 1112 to "1", it indicates that the analog storage unit row 111 needs address replacement; conversely, when the controller 12 sets the conversion selection port S[N] of the row data converter 1112 to "0", it indicates that the analog storage unit row 111 does not need address replacement.

[0060] Furthermore, signal S is a first selection signal. When the redundant design is enabled, starting from the address of the row where the bad pixel occurs, if the redundant storage and computing unit row 112 is located at the top of the analog storage and computing module 11, it is replaced row by row in the second direction A2, and the first selection signal S of all rows from the first storage and computing unit row 113 to the third storage and computing unit row needs to be set to "1". On the contrary, if the redundant storage and computing unit row 112 is located at the bottom of the analog storage and computing module 11, it is replaced row by row in the first direction A1, and the first selection signal S of all rows from the first storage and computing unit row 113 to the third storage and computing unit row is set to "1". The first selection signal S is "1" to represent that the row performs an upward (second direction A2) or downward (first direction A1) address conversion on the input signal D, and transmits it to the second connection port DS. The signal S is "0" to represent that the row does not perform an address conversion on the input signal D, and directly transmits it to the first connection terminal DO.

[0061] In some embodiments, in order to shield the first storage and computing unit row 113 where bad pixels are generated, the controller 12 is used to determine whether there are bad pixels in the analog storage and computing unit row 111 and the first storage and computing unit row 113 where the bad pixels are located. The controller 12 inputs a first enable signal "1" to the signal enable port E[N] of the row data converter 1112 of the first storage and computing unit row 113 so that the row data converter 1112 generates a shielding signal, and the shielding signal is used to shield the storage data and the external data written into the analog storage and computing unit 1111 of the first storage and computing unit row 113.

[0062] The row data converter 1112 of the first storage and calculation unit row 113 is used to receive the first enable signal "1" through the signal enable port E[N], convert the first enable signal "1" into a mask signal "0" and output it to the row register 1113 of the first storage and calculation unit row 113;

[0063] The row register 1113 of the first storage and calculation unit row 113 is used to output the shielding signal "0" to the analog storage and calculation unit 1110 of the bad pixel of the first storage and calculation unit row 113;

[0064] The analog storage and computing unit 1110 of the bad point is used to shield the storage data connected to the first storage and computing unit row 113 and the external data expected to be written into the analog storage and computing unit 1110 of the bad point based on the shielding signal "0".

[0065] By shielding the data of the first storage computing unit row 113 where the bad point is located, the product of the storage data connected to the first storage computing unit row 113 and the external data of the analog storage computing unit 1110 expected to be written into the bad point will not produce a change in the capacitive charge of the first storage computing unit row 113, thereby not affecting the simulated multiplication and accumulation result of the analog storage computing module 11 that generates the bad point, and thus will not affect the overall simulated multiplication and accumulation result of the in-memory computing circuit 1 with redundant design.

[0066] In some embodiments, in order to replace the external data respectively connected to the first storage computing unit row 113 to the third storage computing unit row 112 row by row along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112, and to replace the storage data expected to be written into the first storage computing unit row 113 to the third storage computing unit row by row along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112, the controller 12 is also used to connect the external data D to the external connection port D[N] of the row data converter 1112 of the first storage computing unit row 113 to the third storage computing unit row, and input the first selection signal "1" to the conversion selection port S[N] of the row data converter 1112 of the first storage computing unit row 113 to the third storage computing unit row.

[0067] The row data converter 1112 of the first storage computing unit row 113 to the third storage computing unit row is further used to replace the external data D respectively inputted from the external connection ports D[N] of the first storage computing unit row 113 to the third storage computing unit row to the external output port DO of the row data converter 1112 of the second storage computing unit row to the redundant storage computing unit row 112 row by row along the setting direction of the first storage computing unit row 113 to the redundant storage computing unit row 112, such as the A1 direction, based on the first selection signal "1";

[0068] The row registers 1113 from the second storage and computing unit row to the redundant storage and computing unit row 112 respectively receive the replaced external data D output by the external output port DO of the corresponding row data converter 1112, and send the replaced external data D to the corresponding analog storage and computing unit 1111.

[0069] The controller 12 is also used to replace the storage data expected to be written into the first storage computing unit row 113 to the third storage computing unit row in the analog storage computing unit 1111 from the second storage computing unit row to the redundant storage computing unit row 112 row by row along the setting direction from the first storage computing unit row 113 to the redundant storage computing unit row 112, such as the A1 direction.

[0070] In some embodiments, the redundant storage and computing unit row 112 includes: a redundant data converter, a redundant register, and a redundant storage and computing unit (not shown). The redundant data converter is similar to the row data converter 1112, the redundant register is the same as the row register 1113, and the redundant storage and computing unit is the same as the analog storage and computing unit 1111.

[0071] The first connection terminal DO of the redundant data converter is connected to the third connection terminal DS of the row data converter 1112 of the third storage and computing unit row, the second connection terminal DO of the redundant data converter is connected to the input port of the redundant register, and the output port of the redundant register is connected to the input port of the redundant storage and computing unit.

[0072] The signal enable port E[N] of the redundant data converter is connected to the controller 12, and is used to receive a third enable signal "1" sent by the controller 12, and the third enable signal is used to enable the redundant data converter to receive the external data D sent by the row data converter 1112 of the third storage and computing unit row, and receive the storage data D that the controller 12 is expected to write into the third storage and computing unit row;

[0073] The signal enable port E[N] of the redundant data converter is also used to receive a fourth enable signal “0” sent by the controller 12 , and the fourth enable signal is used to prevent the redundant data converter from receiving the external data D and the storage data.

[0074] In some embodiments, Figure 5As shown, Figure 5 The circuit diagram of the redundant data converter is shown in FIG. The redundant data converter includes a second inverter DC2 and a second MOS transistor NM2, the input end of the second inverter DC2 is connected to the signal enable port E[N] of the redundant data converter, the output end EN of the second inverter DC2 is connected to the gate of the second MOS transistor NM2, the first connection end DO of the redundant data converter is connected to the drain of the second MOS transistor NM2 and the second connection end DO of the redundant data converter, and the source of the second MOS transistor NM2 is connected to the common ground end VSS. The second MOS transistor NM2 can be an N-type MOS transistor.

[0075] Specifically, the third enable signal can be "1" and the fourth enable signal can be "0". The first connection terminal DO on the left side of the redundant data converter is connected to the third connection port DS of the external adjacent conventional row redundant data converter, and is responsible for transposing the input multiplier of the adjacent row into the redundant storage unit row 112 through the DS-DO data path. The second connection terminal DO of the right port is responsible for transmitting the transposed data to the analog storage unit 1111. When the controller 12 enables the redundant storage unit row 112, the input signal E to the signal enable port E[N] is the third enable signal "1", and the reverse signal EN is obtained through the second inverter DC2 in the redundant data converter, then EN is "0", and the second MOS tube is cut off and not conducting. When the controller 12 does not enable the redundant storage unit row 112, the signal E input to the signal enable port E[N] is the fourth enable signal "0", and the reverse signal EN is obtained through the second inverter DC2, then EN is '1', the second MOS tube NM2 is turned on, and the output signal DO of the row redundant data converter is '0', so that when the redundant storage unit row 112 is not enabled, the added redundant storage row will not affect the calculation result.

[0076] In some embodiments, the controller 12 is also used to connect external data D to the external connection port D[N] of the row data converter 1112 of each analog storage and computing unit row 111 of the N rows of analog storage and computing unit rows, input a second selection signal "0" to the conversion selection port S[N] of the row data converter 1112 of each analog storage and computing unit row 111 of the N rows of analog storage and computing unit rows, and input a second enable signal "0" to the signal enable port E[N] of the row data converter 1112 of each analog storage and computing unit row 111 of the N rows of analog storage and computing unit rows; the second enable signal is used to cut off the first MOS tube NM1 in the row data converter 1112, so that the row data converter 1112 transmits the external data D to the corresponding row register 1113 based on the second selection signal "0" to input the corresponding analog storage and computing unit 1111.

[0077] Among them, the N rows of analog storage and computing unit rows refer to all analog storage and computing unit rows 111 in the analog storage and computing module 11 except the first storage and computing unit row 113 to the redundant storage and computing unit row 112.

[0078] Furthermore, if Figure 6 As shown, Figure 6 This is a schematic diagram of an embodiment of a simulation storage and computing module 11, wherein the simulation storage and computing module 11 includes [N+1] rows of simulation storage and computing unit rows 111 and one row of redundant storage and computing unit rows 112, wherein the [0]th row to the [N]th row are all simulation storage and computing unit rows 111, and the [R]th row is a redundant storage and computing unit row 112.

[0079] If it is detected that the [F]th row has storage bad points due to production yield, the controller 12 determines that the [F]th analog storage unit row 111 is the first storage unit row 113, the [F+1]th row is the second storage unit row, and the [N]th row is the third storage unit row.

[0080] There are no bad pixels in the analog storage and computing unit rows 111 from row [0] to row [F-1]. Therefore, the conversion selection port S[N] of the row data converter 1112 in the analog storage and computing unit rows 111 from row [0] to row [F-1] inputs the second selection signal "0", that is, the analog storage and computing unit rows 111 from row [0] to row [F-1] do not need to perform data conversion operations. At the same time, the second enable signal "0" is input to the signal enable port E[N] of the row data converter 1112 in the analog storage unit row 111 of the [0]th row to the [F-1]th row, that is, the signals E[0] to E[F-1] are all set to the low potential '0', that is, the data row-by-row conversion operation is not performed, and the input data D[0] to D[F-1] of the analog storage unit row 111 of the [0]th row to the [F-1]th row are directly transmitted to the corresponding first connection terminal DO through the internal selection transmission gate 1114. Please refer to the arrow from D to DO in [F-1]th row. Head, indicating that D[F-1] in [F-1] is directly transmitted to the first connection terminal DO inside the row (row [F-1]) through the internal selection transmission gate 1114, and is sent to the analog storage unit 1111 for multiplication with the stored data. The product is output to the first plate point P1 of the corresponding capacitor Cp, and is fed back to the second plate point P2 of the corresponding capacitor Cp through the change of the capacitor charge, so as to obtain the corresponding accumulation of charges Q[0]~Q[F-1], and the simulated multiplication and accumulation results are summarized to the summing data line SL connected to the P2 points of all the row capacitors Cp in the column.

[0081] For the analog storage unit row 111 of the [F]th row where a bad pixel exists, the controller 12 inputs the first enable signal "1" to the signal enable port E[F] of the row data converter 1112 of the [F]th row, that is, sets the signal E[F] to the high level "1", and the product potential of the [F]th row at the point P2 of the corresponding capacitor CP is shielded to a potential that does not affect the calculation result. At the same time, the controller 12 inputs the first selection signal of the high level "1" to the conversion selection ports S[F] to S[N] of the row data converter 1112 of the [F]th row to the [N]th row, and starts to perform upward transposition input on the input external data D[F] to D[N] row by row, that is, D[F] is transmitted to the second connection terminal DO of the adjacent row D[F+1] via the third connection terminal DS of the row, and is transmitted to the analog storage unit 1111 of the row via the register 1113 of the [F+1]th row for comparison with the data stored in the [F]th row. Multiplication calculation, that is, the calculation of the original bad point [F] row is performed for the [F+1]th row of the second storage unit line, and the product is output to the P1 point of the corresponding capacitor Cp, and the change of the capacitor charge is fed back to the P2 point of the corresponding capacitor Cp to obtain the corresponding charge Q[F+1], and it is summarized to the summing data line SL connected to the P2 point of all row capacitors Cp in the column to achieve accumulation. Similarly, the accumulation of charges Q[F+2]~Q[N] can also be obtained on the SL data line, thereby obtaining the accumulation of charges Q[F+1]~Q[N].

[0082] See again Figure 6 , when a bad pixel appears in the [F]th row, the [R]th row is a redundant storage unit row 112, and the controller 12 inputs a third enable signal to the signal enable port E[R] of the redundant data converter, that is, E[R] is set to a high level '1', and the external data D[N] input to the highest row [N]th row is converted by the row data converter 1112, and is transmitted from the output port DS of the row data converter 1112 of the [N]th row to the input terminal D of the [R]th row, which can be referred to Figure 6 As indicated by the arrow in the middle cross row, the data is transmitted to the analog storage unit of the row through the register of the [R]th row for multiplication with the data stored in the [R]th row, that is, the calculation of the original [N]th row is performed on the [R]th row, and the product is output to the P1 point of the corresponding capacitor Cp, and fed back to the P2 point of the corresponding capacitor Cp through the change of the capacitor charge to obtain the corresponding charge Q[R], and the charge Q[R] is obtained, and is aggregated to the summing data line SL connected to the P2 point of all row capacitors Cp in the column for accumulation, and the result of the multiplication calculation from the second storage unit row to the Rth row of the redundant storage unit row 112 is accumulated based on the capacitor to obtain the simulated multiplication and accumulation result.

[0083] In summary, on the summation data line SL, the charge accumulation calculation of the products after all row multiplications is completed, which is the simulated multiplication and accumulation result of the entire analog storage and computing module 11, that is, Q[SL]=Q[0]+Q[1]+…+Q[F-1]+Q[F]++Q[F+1]+…+Q[N]+Q[R], where the charge Q[F] corresponding to the first storage and computing unit row 113 of the bad point row is 0, which does not affect the calculation result.

[0084] In the embodiment of the present application, the in-memory computing circuit 1 includes a plurality of analog storage computing modules 11 and a controller 12, each of which includes at least one row of redundant storage computing unit rows 112, and there is no need to set up a plurality of redundant analog storage computing modules 11; the controller 12 is connected to a plurality of analog storage computing unit rows 111 and redundant storage computing unit rows 112 in the analog storage computing module 11, and when the controller 12 determines that there is a first storage computing unit row 113 where a bad point is located in any analog storage computing module 11, the controller 12 shields the data of the first storage computing unit row 113 where the bad point is located, thereby avoiding the data of the bad point row; the redundant storage computing unit row 112 in the analog storage computing module 11 is used to replace the data of the first storage computing unit row 113, and the entire analog storage computing module 11 does not need to be replaced as a whole. The replaced data is used for multiplication calculation and capacitance accumulation, which can avoid the influence of the bad point on the capacitance calculation, and ensure the accuracy of the multiplication and accumulation results after the redundant storage computing unit row 112 replaces the first storage computing unit row 113, and will not affect the use of the analog storage computing module 11. Moreover, the redundant storage and computing unit rows 112 set in each analog storage and computing module 11 are more flexible and can save a smaller area cost, so that bad points in each analog storage and computing module 11 can be replaced and erroneous data can be avoided. This can not only save the time and cost of re-production, but also save the area of ​​the redundant replacement method of the overall storage and computing integrated chip architecture, thereby improving the repair rate of bad points.

[0085] Embodiment 2:

[0086] An analog in-memory computing method is applied to the analog in-memory computing circuit with redundant design of embodiment 1, wherein the analog in-memory computing circuit with redundant design 1 comprises a plurality of analog storage computing modules 11 and a controller 12, wherein the plurality of analog storage computing modules 11 are arranged in a matrix, the analog storage computing modules 11 comprise a plurality of analog storage computing unit rows 111 and at least one row of redundant storage computing unit rows 112, and the controller 12 is respectively connected to the analog storage computing unit rows 111 and the redundant storage computing unit rows 112. The method is executed by the controller 12, and comprises steps S101 to S103:

[0087] S101: Determine whether there is a bad pixel in the analog storage and computing unit row of the analog storage and computing module and the first storage and computing unit row where the bad pixel is located;

[0088] S102: If the first storage computing unit row exists, a control signal is sent from the first storage computing unit row to the redundant storage computing unit row based on the first storage computing unit row, wherein the control signal is used to perform shielding processing on the data of the first storage computing unit row, and to replace the external data respectively connected to the first storage computing unit row to the third storage computing unit row with the data connected to the second storage computing unit row to the redundant storage computing unit row row by row along the setting direction from the first storage computing unit row to the redundant storage computing unit row, and to replace the storage data expected to be written from the first storage computing unit row to the third storage computing unit row with the data written from the second storage computing unit row to the redundant storage computing unit row row by row along the setting direction from the first storage computing unit row to the redundant storage computing unit row;

[0089] S103: obtaining the multiplication calculation results of each analog storage unit row and redundant storage unit row in the analog storage module, and accumulating the multiplication calculation results in the analog storage module based on the capacitor to obtain the simulated multiplication and accumulation result; the multiplication calculation result from the second storage unit row to the redundant storage unit row is that the second storage unit row to the redundant storage unit row performs multiplication calculation based on the replaced storage data and the external data respectively;

[0090] Among them, the second storage computing unit row is adjacent to the first storage computing unit row, the third storage computing unit row is adjacent to the redundant storage computing unit row, and the second storage computing unit row and the third storage computing unit row are located between the first storage computing unit row and the redundant storage computing unit row.

[0091] Since the implementation of the method is described in detail in Example 1, it will not be repeated here.

[0092] The in-memory calculation method of the embodiment of the present application, the in-memory calculation circuit 1 includes a plurality of analog storage and calculation modules 11 and a controller 12, each of the analog storage and calculation modules 11 includes at least one row of redundant storage and calculation unit rows 112, and there is no need to set up a plurality of redundant analog storage and calculation modules 11; the controller 12 is connected to a plurality of analog storage and calculation unit rows 111 and redundant storage and calculation unit rows 112 in the analog storage and calculation module 11, and when any analog storage and calculation module 11 determines that there is a first storage and calculation unit row 113 where a bad pixel is located, the controller 12 shields the data of the first storage and calculation unit row 113 where the bad pixel is located, thereby avoiding the data of the bad pixel row; the redundant storage and calculation unit row 112 in the analog storage and calculation module 11 is used to replace the data of the first storage and calculation unit row 113, and there is no need to replace the entire analog storage and calculation module 11 as a whole. The replaced data is used for multiplication calculation and capacitance accumulation, which can avoid the influence of the bad pixel on the capacitance calculation, ensure the accuracy of the multiplication and accumulation results after the redundant storage and calculation unit row 112 replaces the first storage and calculation unit row 113, and will not affect the use of the analog storage and calculation module 11. Moreover, the redundant storage and computing unit rows 112 set in each analog storage and computing module 11 are more flexible and can save a smaller area cost, so that bad points in each analog storage and computing module 11 can be replaced and erroneous data can be avoided. This can not only save the time and cost of re-production, but also save the area of ​​the redundant replacement method of the overall storage and computing integrated chip architecture, thereby improving the repair rate of bad points.

[0093] Embodiment three:

[0094] A processing device includes the in-memory computing circuit with redundant design in the first embodiment. Through the in-memory computing circuit with redundant design in the first embodiment, the in-memory computing circuit 1 of the present application includes a plurality of analog storage computing modules 11 and a controller 12, each of which includes at least one row of redundant storage computing unit rows 112, and it is not necessary to set up a plurality of redundant analog storage computing modules 11; the controller 12 is connected to a plurality of analog storage computing unit rows 111 and redundant storage computing unit rows 112 in the analog storage computing module 11, and the controller 12 determines the first storage computing unit row 113 where a bad point is located in any analog storage computing module 11 When the data of the first storage and calculation unit row 113 where the bad point is located is shielded, the data of the bad point row can be avoided; the redundant storage and calculation unit row 112 in the analog storage and calculation module 11 is used to replace the data of the first storage and calculation unit row 113, and the entire analog storage and calculation module 11 does not need to be replaced as a whole. The replaced data is used for multiplication calculation and capacitance accumulation, which can avoid the influence of the bad point on the capacitance calculation, ensure the accuracy of the multiplication and accumulation results after the redundant storage and calculation unit row 112 replaces the first storage and calculation unit row 113, and will not affect the use of the analog storage and calculation module 11. In addition, the method of setting the redundant storage and calculation unit row 112 in each analog storage and calculation module 11 is more flexible, and can cost less area cost, so that the bad points in each analog storage and calculation module 11 can be replaced and erroneous data can be avoided, which can not only save the time and cost of re-production, but also save the area of ​​the redundant replacement method of the overall storage and calculation integrated chip architecture, and improve the repair rate of the bad points.

[0095] It is worth noting that the above-mentioned analog storage and calculation module can exist in the form of a module or in the form of a chip, that is, the above-mentioned analog storage and calculation module can be a small chip. The analog in-memory calculation circuit provided by the utility model can exist in a modular form or in the form of a chip.

[0096] The processing device of the present invention may be a chip, or an IP core (a circuit module with independent functions, which can be applied in other chip design projects containing the circuit module). The processing device provided by the present invention may be, for example, a neural network accelerator (i.e., NPU), or a speech recognition device containing a neural network accelerator, a video processing device containing a neural network accelerator, a large model processing device, and other devices. When the processing device is a chip, each module in the chip may be implemented in whole or in part by software, hardware, and a combination thereof. The above modules may be embedded in or independent of the processor in the computing device in the form of hardware, or may be stored in the memory in the computing device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0097] The utility model can be applied to fields requiring high-precision, high-reliability, low-power consumption, and low-area-cost computing power, such as artificial intelligence and metaverse that are suitable for analog in-memory computing chips, artificial intelligence training or reasoning chip products, autonomous driving chips, VR chips, robot built-in chips, wearable smart chips, and deep learning applications of parallel computing.

[0098] Embodiment 4:

[0099] An electronic device includes the in-memory computing circuit with redundant design in the first embodiment. The electronic device provided by the utility model can be applied to a series of electronic devices such as computing centers, computing devices, edge computing, autonomous driving, AR, VR, laser radar, and smart phones, tablet computers, wearable electronic equipment, smart home electronic products, industrial or medical or battery-powered devices.

[0100] The above is only the preferred embodiment of the present application. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application belong to the protection scope of the present application.

Claims

1. An in-memory computing circuit with redundant design, characterized in that: The in-memory computing circuit comprises: a plurality of analog storage computing modules and a controller, the analog storage computing modules comprising a plurality of analog storage computing unit rows and at least one redundant storage computing unit row, the plurality of analog storage computing modules being arranged in a matrix; The controller is connected to the analog storage and computing unit row and the redundant storage and computing unit row respectively; The controller is used to determine whether there is a bad pixel in the analog storage and computing cell row and the first storage and computing cell row where the bad pixel is located. If the first storage and computing cell row exists, the controller sends a control signal from the first storage and computing cell row to the redundant storage and computing cell row based on the first storage and computing cell row; the control signal is used to set the plate of the capacitor of the first storage and computing cell row to a high potential or a low potential so that the data in the first storage and computing cell row does not affect the potential on the plate of the capacitor, and to make the external data respectively connected to the first storage and computing cell row to the third storage and computing cell row be replaced row by row along the setting direction of the first storage and computing cell row to the redundant storage and computing cell row, and to replace the storage data expected to be written from the first storage and computing cell row to the third storage and computing cell row to be written from the second storage and computing cell row to the redundant storage and computing cell row row by row along the setting direction of the first storage and computing cell row to the redundant storage and computing cell row; The second storage unit row to the redundant storage unit row respectively perform multiplication calculations based on the replaced storage data and the external data, and accumulate the results of the multiplication calculations from the second storage unit row to the redundant storage unit row based on the capacitor to obtain a simulated multiplication and accumulation result; Among them, the second storage computing unit row is adjacent to the first storage computing unit row, the third storage computing unit row is adjacent to the redundant storage computing unit row, and the second storage computing unit row and the third storage computing unit row are located between the first storage computing unit row and the redundant storage computing unit row.

2. The in-memory computing circuit with redundant design according to claim 1, characterized in that: The redundant storage and computing unit row is located in the top row or the bottom row of the analog storage and computing module.

3. The in-memory computing circuit with redundant design according to claim 1, characterized in that: The analog storage and calculation unit row includes a row data converter, a row register and an analog storage and calculation unit, the signal enable port of the row data converter and the output end of the analog storage and calculation unit are both connected to the controller, the first connection end of the row data converter is connected to the input end of the row register, and the output end of the row register is connected to the input end of the analog storage and calculation unit; the third connection end of the row data converter is connected to the second connection end of the row data converter of the analog storage and calculation unit row of an adjacent row; The controller is used to determine whether there is a bad pixel in the analog storage and computing unit row and the first storage and computing unit row where the bad pixel is located, and if the first storage and computing unit row exists, input a first enable signal to the signal enable port of the row data converter to enable the row data converter to generate a shielding signal, wherein the shielding signal is used to shield the storage data and / or the external data written into the analog storage and computing unit; The row data converter is used for receiving the first enable signal through the signal enable port, converting the first enable signal into the shielding signal and outputting the converted signal to the row register; The row register is used to output the shielding signal to the analog storage and calculation unit; The analog storage and computing unit is used to shield external data connected to the first storage and computing unit row and storage data expected to be written into the first storage and computing unit row based on the shielding signal.

4. The in-memory computing circuit with redundant design according to claim 3, characterized in that: The row data converter also includes an external connection port and a conversion selection port; The controller is further used to connect the external data to the external connection port of the row data converter from the first storage and computing unit row to the third storage and computing unit row, and input a first selection signal to the conversion selection port of the row data converter from the first storage and computing unit row to the third storage and computing unit row; The row data converter from the first storage computing unit row to the third storage computing unit row is further used to replace the external data respectively connected to the external connection ports from the first storage computing unit row to the third storage computing unit row, row by row, along the setting direction from the first storage computing unit row to the redundant storage computing unit row, to the external output port of the row data converter from the second storage computing unit row to the redundant storage computing unit row based on the first selection signal; The row registers from the second storage and computing unit row to the redundant storage and computing unit row respectively receive the replaced external data output by the external output port of the corresponding row data converter, and send the replaced external data to the corresponding analog storage and computing unit.

5. The in-memory computing circuit with redundant design according to claim 4, characterized in that: The row data converter includes a transmission gate, a first inverter, and a first MOS transistor; the first inverter is connected to the signal enable port; the external connection port is connected to two transmission gates, one transmission gate is connected to the third connection end of the row data converter to connect to the second connection end of the row data converter of the adjacent analog storage unit row, and the other transmission gate is connected to the drain of the first MOS transistor, the first connection end and the second connection end of the row data converter, the first connection end of the row data converter is connected to the input end of the row register, the gate of the first MOS transistor is connected to the signal enable port of the row data converter, and the source of the first MOS transistor is connected to the common ground end; the first inverter is connected to the conversion selection port, which is used to control the switch of the transmission gate to select the external data to be output from the first connection end or the second connection end; If the signal enable port of the row data converter receives the first enable signal and the conversion selection port of the row data converter receives the first selection signal, the first MOS tube is turned on, so that the first connection end of the row data converter generates the shielding signal, and the external data is transmitted from the third connection end of the row data converter to the second connection end of the row data converter of the adjacent analog storage and computing unit row in sequence.

6. The in-memory computing circuit with redundant design according to any one of claims 3, 4 or 5, characterized in that: The redundant storage and computing unit row includes: a redundant data converter, a redundant register and a redundant storage and computing unit; The first connection end of the redundant data converter is connected to the third connection end of the row data converter of the third storage and calculation unit row, the second connection end of the redundant data converter is connected to the input port of the redundant register, and the output port of the redundant register is connected to the input port of the redundant storage and calculation unit; The signal enable port of the redundant data converter is connected to the controller and is used to receive a third enable signal sent by the controller; the third enable signal is used to enable the redundant data converter to receive external data sent by the row data converter of the third storage and computing unit row, and receive storage data that the controller is expected to write into the third storage and computing unit row; The signal enable port of the redundant data converter is further used to receive a fourth enable signal sent by the controller, and the fourth enable signal is used to prevent the redundant data converter from receiving the external data and the storage data.

7. The in-memory computing circuit with redundant design according to claim 6, characterized in that: The redundant data converter comprises a second inverter and a second MOS transistor, the input end of the second inverter is connected to the signal enable port of the redundant data converter, the output end of the second inverter is connected to the gate of the second MOS transistor, the first connection end of the redundant data converter is connected to the drain of the second MOS transistor and the second connection end of the redundant data converter, and the source of the second MOS transistor is connected to a common ground end.

8. The in-memory computing circuit with redundant design according to claim 1, characterized in that: The controller sends a control signal from the first storage computing unit row to the redundant storage computing unit row based on the first storage computing unit row, including: The controller acquires address information of the first storage and computing unit row, and sends a first control signal according to the address information of the first storage and computing unit row, wherein the first control signal enables the first storage and computing unit row to perform data shielding; Obtaining row addresses from the first storage and computing unit row to the redundant storage and computing unit row; The controller sends a second control signal to the second storage computing unit row to the redundant storage computing unit row in sequence based on the row addresses of each row from the first storage computing unit row to the redundant storage computing unit row, and the second control signal enables the second storage computing unit row to perform the row-by-row replacement from the second storage computing unit row to the redundant storage computing unit row.

9. A processing device, characterized in that: An in-memory computing circuit with redundant design comprising any one of claims 1-8.

10. An electronic device, characterized in that: An in-memory computing circuit with redundant design comprising any one of claims 1-8.

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