Self-adaptive gain adjusting circuit and switcher

Abstract

The utility model discloses a self-adaptive gain adjusting circuit and a switcher, the circuit comprises a first switching processing module, a second switching processing module and a signal output module, the first switching processing module is used for receiving a first input signal transmitted by a first signal input module, and the second switching processing module is used for receiving a second input signal transmitted by a second signal input module; the first switching processing module is used for receiving a first input signal, executing a first target processing operation on the first input signal to obtain a first target signal and transmitting the first target signal to the second switching processing module; the second switching processing module is used for receiving a second input signal transmitted by the second signal input module, executing a second target processing operation on the first target signal and the second input signal, obtaining a second target signal and transmitting the second target signal to the signal output module; and the signal output module is used for transmitting the second target signal to preset target equipment. Therefore, according to the utility model, the gain can be adaptively adjusted so as to improve the quality of the output signal, thereby being beneficial to improving the user experience.

Description

Technical Field

[0001] The utility model relates to the technical field of switches, and in particular to a circuit and a switch for adaptively adjusting gain. Background Art

[0002] With the continuous development of science and technology, digital electronic devices have become an indispensable part of modern life, and most of the current digital electronic devices use the HDMI interface as the main audio and video signal transmission interface. Various signal source output devices and display devices need to be connected via HDMI cables to transmit high-quality and stable audio and video signals.

[0003] At present, there are two signal processing modes in the chip of the hard-cut solution of the multi-channel HDMI switch: no signal gain and fixed signal gain. The defects of no signal gain are that the input and output line distances will be limited, and the output video signal quality is relatively weak. The defects of fixed signal gain are that the output video signal is relatively stable only when the input and output line distances are long. If the input or output line distance is relatively short, the output signal may be unstable, such as screen flickering, no picture, and other abnormalities. This will not only lead to low quality of the output video and audio, but also reduce the user experience. It can be seen that it is particularly important to provide a new audio separation circuit to improve the quality of the output signal and thus meet the user's requirements for video and audio quality and improve the user experience. Utility Model Content

[0004] The utility model provides a circuit and a switch for adaptively adjusting gain, which can adaptively adjust the gain to improve the quality of the output signal, thereby helping to improve the user experience.

[0005] In order to solve the above technical problems, the utility model discloses in a first aspect that the circuit for adaptively adjusting gain includes a first switching processing module, a second switching processing module, and a signal output module, wherein:

[0006] The first end of the first switching processing module is used to electrically connect to the first signal input module, the second end of the first switching processing module is electrically connected to the first end of the second switching processing module, the second end of the second switching processing module is used to electrically connect to the second signal input module, and the third end of the second switching processing module is electrically connected to the first end of the signal output module;

[0007] The first switching processing module is used to receive the first input signal transmitted by the first signal input module, perform a first target processing operation on the first input signal, obtain a first target signal and transmit the first target signal to the second switching processing module;

[0008] The second switching processing module is used to receive the second input signal transmitted by the second signal input module, and perform a second target processing operation on the first target signal and the second input signal to obtain a second target signal and transmit the second target signal to the signal output module;

[0009] The signal output module is used to transmit the received second target signal to a preset target device.

[0010] As an optional implementation, in the first aspect of the utility model, the circuit for adaptively adjusting gain further includes a target control module, wherein:

[0011] The first end of the target control module is electrically connected to the third end of the first switching processing module, and the second end of the target control module is electrically connected to the fourth end of the second switching processing module;

[0012] The target control module is used to determine a signal type corresponding to the first target signal and a signal type corresponding to the second target signal.

[0013] As an optional implementation, in the first aspect of the utility model, the first switching processing module includes a first target chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first AUDIO circuit, wherein:

[0014] The first end of the first target chip is used to electrically connect to the first signal input module, the second end of the first target chip is electrically connected to the first end of the second switching processing module, the third end of the first target chip is electrically connected to the first end of the target control module, the fourth end of the first target chip is electrically connected to the first end of the first JTAG circuit, the fifth end of the first target chip is electrically connected to the first end of the first I2C circuit, the sixth end of the first target chip is electrically connected to the first end of the first QSPI circuit, and the seventh end of the first target chip is electrically connected to the first end of the first AUDIO circuit.

[0015] As an optional implementation, in the first aspect of the utility model, the second switching processing module includes a second target chip, a second JTAG circuit, a second I2C circuit, and a second QSPI circuit, wherein:

[0016] The first end of the second target chip is electrically connected to the second end of the first switching processing module, the second end of the second target chip is used to electrically connect to the second signal input module, the third end of the second target chip is used to electrically connect to the signal output module, the fourth end of the second target chip is electrically connected to the first end of the second JTAG circuit, the fifth end of the second target chip is electrically connected to the first end of the second I2C circuit, and the sixth end of the second target chip is electrically connected to the first end of the second QSPI circuit.

[0017] As an optional implementation, in the first aspect of the utility model, the second switching processing module further includes a P_MODE circuit, wherein:

[0018] The first terminal of the P_MODE circuit is electrically connected to the seventh terminal of the second target chip.

[0019] As an optional implementation, in the first aspect of the utility model, the circuit for adaptively adjusting gain further includes the first signal input module and the second signal input module, wherein the number of the first signal input module is at least one and the number of the second signal input module is at least one.

[0020] As an optional implementation, in the first aspect of the utility model, the first signal input module includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

[0021] The first end of the target input chip is electrically connected to the first end of the first switching processing module, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

[0022] As an optional implementation, in the first aspect of the utility model, the circuit for adaptively adjusting gain further includes the signal output module; wherein the signal output module includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, wherein:

[0023] The third end of the second switching processing module is electrically connected to the first end of the target output chip, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output circuit is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output circuit is electrically connected to the first end of the current limiting protection circuit.

[0024] As an optional implementation, in the first aspect of the utility model, the target control module includes a control chip and a CEC circuit, wherein:

[0025] The first end of the control chip is electrically connected to the third end of the first switching processing module, the second end of the control chip is electrically connected to the fourth end of the second switching processing module, and the third end of the control chip is electrically connected to the first end of the CEC circuit.

[0026] The second aspect of the utility model discloses a switch, which includes an input port for receiving an HDMI signal, and includes a circuit for adaptively adjusting gain as described in any one of the first aspect of the utility model, and includes an output port for outputting the second output signal.

[0027] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0028] The utility model provides a circuit and a switch for adaptively adjusting gain, the circuit comprising a first switching processing module, a second switching processing module, and a signal output module, wherein the first switching processing module is used to receive a first input signal transmitted by a first signal input module, and perform a first target processing operation on the first input signal, obtain a first target signal and transmit the first target signal to the second switching processing module; the second switching processing module is used to receive a second input signal transmitted by a second signal input module, and perform a second target processing operation on the first target signal and the second input signal, obtain a second target signal and transmit the second target signal to the signal output module; the signal output module is used to transmit the second target signal to a preset target device. It can be seen that the utility model can adaptively adjust the gain to improve the quality of the output signal, thereby helping to improve the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a structural schematic diagram of a circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0031] Figure 2 It is a structural schematic diagram of another circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0032] Figure 3 It is a structural schematic diagram of an LED selection circuit disclosed in an embodiment of the utility model;

[0033] Figure 4 It is a structural schematic diagram of a key selection circuit disclosed in an embodiment of the utility model;

[0034] Figure 5 It is a structural schematic diagram of a first target chip disclosed in the utility model;

[0035] Figure 6 It is a structural schematic diagram of a first JTAG circuit disclosed in the utility model;

[0036] Figure 7 It is a structural schematic diagram of a first I2C circuit disclosed in the utility model;

[0037] Figure 8 It is a structural schematic diagram of a first QSPI circuit disclosed in the utility model;

[0038] Fig. 9 It is a structural schematic diagram of a first AUDIO circuit disclosed in the utility model;

[0039] Fig.10 It is a structural schematic diagram of a second target chip disclosed in the utility model;

[0040] Fig.11 It is a structural schematic diagram of a second JTAG circuit disclosed in the utility model;

[0041] Fig.12 It is a structural schematic diagram of a second I2C circuit disclosed in the utility model;

[0042] Fig.13 It is a structural schematic diagram of a second QSPI circuit disclosed in the utility model;

[0043] Fig.14 It is a structural schematic diagram of a P_MODE circuit disclosed by the utility model;

[0044] Fig.15 It is a structural schematic diagram of another circuit for adaptively adjusting gain disclosed in the utility model;

[0045] Fig.16 It is a structural schematic diagram of a target input chip disclosed in the utility model;

[0046] Fig.17 It is a structural schematic diagram of an input ESD processing circuit disclosed by the utility model;

[0047] Fig.18It is a structural schematic diagram of an input DDC processing circuit disclosed in the utility model;

[0048] Fig.19 It is a structural schematic diagram of an input HPD processing circuit disclosed in the utility model;

[0049] Fig. 20 It is a structural schematic diagram of a target output chip disclosed in the utility model;

[0050] Fig.21 It is a structural schematic diagram of an output ESD processing circuit disclosed by the utility model;

[0051] Fig. 22 It is a structural schematic diagram of an output DDC processing circuit disclosed by the utility model;

[0052] Fig.23 It is a structural schematic diagram of an output HPD processing circuit disclosed in the utility model;

[0053] Fig.24 It is a structural schematic diagram of a current limiting protection circuit disclosed by the utility model;

[0054] Fig.25 This is a structural schematic diagram of a control chip disclosed in the utility model;

[0055] Fig.26 It is a structural schematic diagram of a CEC circuit disclosed by the utility model;

[0056] Fig. 27 It is a structural schematic diagram of a switch disclosed by the utility model. DETAILED DESCRIPTION

[0057] For better understanding and implementation, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] It should be noted that, unless otherwise clearly specified and limited, the term "electrical connection" in the specification and claims of the utility model and the above-mentioned drawings should be understood in a broad sense. For example, it can be a fixed electrical connection, a detachable electrical connection, or an integral electrical connection; it can be a mechanical electrical connection, an electrical electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. The terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For those of ordinary skill in the art, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0059] The utility model discloses a circuit for adaptively adjusting gain, including a first switching processing module, a second switching processing module, and a signal output module, wherein: the first end of the first switching processing module is used to electrically connect to the first signal input module, the second end of the first switching processing module is electrically connected to the first end of the second switching processing module, the second end of the second switching processing module is used to electrically connect to the second signal input module, and the third end of the second switching processing module is used to electrically connect to the signal output module; the first switching processing module is used to receive the first input signal transmitted by the first signal input module, and perform a first target processing operation on the first input signal, obtain the first target signal and transmit the first target signal to the second switching processing module; the second switching processing module is used to receive the second input signal transmitted by the second signal input module, and perform a second target processing operation on the first target signal and the second input signal, obtain the second target signal and transmit the second target signal to the signal output module; the signal output module is used to transmit the second target signal to a preset target device, and can adaptively adjust the gain to improve the quality of the output signal, thereby helping to improve the user experience. The following are detailed descriptions.

[0060] Embodiment 1

[0061] See also Figure 1 , Figure 1 The circuit for adaptively adjusting gain disclosed in the embodiment of the utility model can not only adaptively adjust the gain to improve the quality of the output signal, but also help improve the user experience, which is not limited by the embodiment of the utility model. Figure 1 As shown, the circuit for adaptively adjusting gain includes a first switching processing module 101, a second switching processing module 102, and a signal output module 103, wherein:

[0062] The first end of the first switching processing module 101 is used to electrically connect to the first signal input module, the second end of the first switching processing module 101 is electrically connected to the first end of the second switching processing module 102, the second end of the second switching processing module 102 is used to electrically connect to the second signal input module, and the third end of the second switching processing module 102 is electrically connected to the first end of the signal output module 103;

[0063] The first switching processing module 101 is used to receive the first input signal transmitted by the first signal input module, perform a first target processing operation on the first input signal, obtain a first target signal and transmit the first target signal to the second switching processing module 102;

[0064] The second switching processing module 102 is used to receive the second input signal transmitted by the second signal input module, and perform a second target processing operation on the first target signal and the second input signal to obtain a second target signal and transmit the second target signal to the signal output module 103;

[0065] The signal output module 103 is used to transmit the received second target signal to a preset target device.

[0066] In this optional embodiment, the first switching processing module 101 may optionally include a two-input and one-output video switching processing module, wherein the two-input and one-output video switching processing module may include a GSV6702 chip with equalizer gain control and adaptive gain adjustment, and the first switching processing module 101 may be used to connect two HDMI input signals, that is, the first input signal received by the first switching processing module 101 may include two HDMI input signals, and the first target processing operation is performed on the collected two HDMI input signals to obtain the first target signal. Further, the first target processing operation may include a gain adjustment operation.

[0067] In this optional embodiment, optionally, the second switching processing module 102 may include a four-input and one-output video switching processing module, wherein the four-input and one-output video switching processing module may include a GSV6705 chip with equalizer gain control and adaptive gain adjustment, and the second switching processing module 102 may be used to connect four HDMI input signals, and the second switching processing module 102 may be used to connect four HDMI input signals, that is, the second input signal received by the second switching processing module 102 may include four HDMI input signals, and the second target processing operation is performed on the collected four HDMI input signals to obtain the second target signal. Further, the second target processing operation may include a gain adjustment operation.

[0068] In this optional embodiment, optionally, the signal output module 103 is used to transmit the second target signal to a preset target device, wherein the preset target device may include a smart phone, a smart tablet, a smart computer, a smart laptop, a smart watch, etc., which are devices that can be used to display video signals and can be used to play voice signals.

[0069] In this optional embodiment, further optionally, the second target output signal may include an 8K video signal.

[0070] It can be seen that the implementation Figure 1 The described circuit for adaptively adjusting gain receives the first input signal transmitted by the first signal input module through the first switching processing module 101 and performs the first target processing operation to obtain the first target signal and transmits it to the second switching processing module 102. The second switching processing module 102 performs the second target processing operation on the first target signal and the collected second input signal to obtain the second target signal and transmits it to the target output module and outputs it to the corresponding device. The first switching processing module 101 and the second switching processing module 102 can collect five HDMI input signals and perform corresponding target processing operations in a targeted manner, so as to obtain the first target signal and then obtain the second target signal, and can realize the processing of multiple HD signals through two switching processing modules. The MI input signal performs corresponding adaptive gain adjustment operations to achieve adaptive gain adjustment. Compared with the defects of weak output signal quality and inability to adaptively adjust in the prior art, it can be beneficial to improve the intelligence and efficiency of gain adjustment operations on multiple HDMI input signals, and can perform corresponding target operations on multiple HDMI input signals through first target processing and second target processing to obtain 8K video signals, which can be beneficial to improve the quality and clarity of the output video signal. Through signal optimization and integration, it can help to improve the quality and stability of the signal, provide a more reliable data basis for subsequent transmission and application, and further help to improve the clarity and user experience of use and viewing.

[0071] In an optional embodiment, if Figure 2 As shown, Figure 2 Another circuit for adaptively adjusting gain disclosed in an embodiment of the utility model further includes a target control module 104, wherein:

[0072] A first end of the target control module 104 is electrically connected to a third end of the first switching processing module 101 , and a second end of the target control module 104 is electrically connected to a fourth end of the second switching processing module 102 ;

[0073] The target control module 104 is used to determine the signal type corresponding to the first target signal and the signal type corresponding to the second target signal.

[0074] In this optional embodiment, optionally, the target control module 104 may include an MCU control chip.

[0075] In this optional embodiment, optionally, the target control module 104 and the first switching processing module 101 can be electrically connected by an IIC bus connection; the target control module 104 and the second switching processing module 102 can be electrically connected by an IIC bus connection. Among them, IIC, also known as Inter-Integrated Circuit, is a two-wire serial bus developed by Philips for connecting microcontrollers and their peripherals. It is a synchronous, half-duplex, bidirectional two-wire serial bus consisting of two buses: a serial clock line SCL and a serial data line SDA. The SCL line is responsible for generating synchronous clock pulses, while the SDA line is responsible for transmitting serial data between devices.

[0076] In this optional embodiment, further optionally, the third end of the target control module 104 is electrically connected to the first end of the LED selection circuit, and the second end of the LED selection circuit is electrically connected to the first end of the key selection circuit, wherein:

[0077] A key selection circuit, used for receiving key instructions and transmitting the key instructions to the LED selection circuit;

[0078] The LED selection circuit is used to determine the target LED according to the key instruction, wherein the target LED is used to instruct the target control module 104 to determine the signal type corresponding to the first target signal and the signal type corresponding to the second target signal.

[0079] In this optional embodiment, optionally, as Figure 3 As shown, Figure 3 The utility model discloses a schematic diagram of a structure of an LED selection circuit, wherein the components included in the LED selection circuit and the connection method between the components can be as follows Figure 3 as shown; Figure 4 As shown, Figure 4 The utility model discloses a key selection circuit structure diagram, wherein the key selection circuit includes components and the connection between the components can be as follows Figure 4 shown.

[0080] In this optional embodiment, optionally, for example, when the key instruction output by the user to the key selection circuit includes a key for determining that the LED light corresponding to HDMIIN1 is lit, the target control module 104 determines that the signal type of the output signal corresponding to the first switching processing module 101 and the second switching processing module 102 includes an 8K resolution signal type.

[0081] In this optional embodiment, further optionally, the signal type corresponding to the first target signal and the signal type corresponding to the second target signal may include one or more of a resolution signal type, an output audio signal type, and a video format type.

[0082] It can be seen that the implementation of this optional embodiment can connect the target control module 104 with the first switching processing module 101 and the second switching processing module 102 and determine the signal type corresponding to the first target signal and the signal type corresponding to the second target signal. The target control module 104 automatically identifies and judges the signal type, which is beneficial to improving the intelligence of the operation and the intelligence of the process of determining the signal type, reducing the need for human intervention, thereby improving the level of automation and intelligence. The target control module 104 accurately judges the signal type, which can avoid system errors or failures caused by signal type mismatch or misjudgment, and is beneficial to stability and reliability, so as to improve the quality and clarity of the output video signal. By optimizing and integrating the signal, it can help to improve the quality and stability of the signal, and further help to improve the clarity and user experience of use and viewing.

[0083] In another optional embodiment, the first switching processing module 101 includes a first target chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first AUDIO circuit, wherein:

[0084] The first end of the first target chip is used to electrically connect to the first signal input module, the second end of the first target chip is electrically connected to the first end of the second switching processing module 102, the third end of the first target chip is electrically connected to the first end of the target control module 104, the fourth end of the first target chip is electrically connected to the first end of the first JTAG circuit, the fifth end of the first target chip is electrically connected to the first end of the first I2C circuit, the sixth end of the first target chip is electrically connected to the first end of the first QSPI circuit, and the seventh end of the first target chip is electrically connected to the first end of the first AUDIO circuit.

[0085] In this optional embodiment, optionally, as Figure 5 As shown, Figure 5 is a schematic diagram of the structure of the first target chip disclosed in the utility model, wherein the components included in the first target chip and the connection method between the components can be as follows Figure 5 As shown;

[0086] Further, such as Figure 6 As shown, Figure 6is a schematic diagram of the structure of a first JTAG circuit disclosed in the utility model, wherein the components included in the first JTAG circuit and the connection method between the components can be as follows Figure 6 As shown;

[0087] Further, such as Figure 7 As shown, Figure 7 is a schematic diagram of the structure of a first I2C circuit disclosed in the utility model, wherein the components included in the first I2C circuit and the connection method between the components can be as follows Figure 7 As shown;

[0088] Further, such as Figure 8 As shown, Figure 8 : is a schematic diagram of the structure of a first QSPI circuit disclosed in the utility model, wherein the components included in the first QSPI circuit and the connection method between the components can be as follows: Figure 8 As shown;

[0089] Further, such as Fig. 9 As shown, Fig. 9 : is a schematic diagram of the structure of a first AUDIO circuit disclosed in the utility model, wherein the components included in the first AUDIO circuit and the connection method between the components can be as follows Fig. 9 shown.

[0090] In this optional embodiment, optionally, the first signal input module may include two HDMI signal input modules, wherein the two HDMI signal input modules may include HDMIIN1 and HDMIIN2, and the first target chip can be used for the two HDMI signal input modules to perform a first target processing operation to obtain a first target signal.

[0091] In this optional embodiment, optionally, the first target chip may include a GSV6702 chip, wherein the GSV6702 is a two-input and one-output HDMI2.1 repeater, which integrates an enhanced microcontroller based on RISC-V and is suitable for various application scenarios requiring high-quality HDMI signal processing and transmission.

[0092] In this optional embodiment, optionally, the first JTAG circuit includes a JTAG circuit, wherein the JTAG circuit is a standard test access and boundary scan circuit designed by the Joint Test Action Group. The JTAG circuit is composed of a series of hardware components, such as test data input (TDI), test data output (TDO), etc., which are connected and communicated through the JTAG interface. The main functions of the JTAG circuit include chip-level testing, boundary scanning, copyright protection, integrated circuit debugging and troubleshooting, and configuration and programming. By inserting an interface on the chip pin, JTAG can detect and diagnose chip errors, support functional testing, boundary scanning testing, and code coverage testing, and ensure the normal operation and quality control of the chip. Further, all operations of the JTAG circuit must be synchronized with the JTAG clock signal (TCK). The test controller can send test data to the test target through the JTAG interface and receive response data from the test target to verify the function and performance of the circuit. In the debug mode, the test controller can also read and modify the internal state and registers of the test target.

[0093] In this optional embodiment, optionally, the first I2C circuit includes an I2C circuit, wherein the I2C circuit, whose full name is Inter-Integrated Circuit (interconnected integrated circuit) circuit, is a hardware circuit used for short-distance data transmission between integrated circuits, and is mainly composed of two lines, SDA (data bus) and SCL (clock bus). Through these two lines, the master device can communicate with the slave device bidirectionally.

[0094] In this optional embodiment, optionally, the first QSPI circuit includes a QSPI circuit, wherein QSPI is the abbreviation of QueuedSPI, and the QSPI circuit is a dedicated communication interface circuit for connecting single, dual or quad (data lines) SPI Flash storage media; the biggest feature of the QSPI circuit is that an 80-byte RAM is used to replace the SPI's transmit and receive data registers. The 80-byte RAM is divided into three parts: a 16-word transmit RAM, a 16-word receive RAM, and a 16-byte command RAM. These three parts together form a transmission queue with 16 QSPI transmission control groups, each QSPI transmission control group containing a command RAM, a transmit RAM, and a receive RAM. The data length, chip select, and other information of each QSPI transmission can be determined separately by the command RAM of the corresponding QSPI transmission control group.

[0095] In this optional embodiment, optionally, the first AUDIO circuit includes an AUDIO circuit, wherein the AUDIO circuit is mainly used to process audio signals to ensure that the audio signals can be transmitted and played clearly and accurately, and the main function of the AUDIO circuit is to amplify and process the sound signals, wherein the process of AUDIO amplifying and processing the sound signals may include one or more of filtering processing, equalization processing, and reverberation processing.

[0096] It can be seen that the implementation of this optional embodiment can process the HDMI input signal corresponding to the first signal input module through the first target chip and output it to the second switching processing module 102, and through the coordinated operation of the first JTAG circuit, the first I2C circuit, the first QSPI circuit and the first AUDIO circuit, it can integrate two HDMI signal input modules to simultaneously receive and process HDMI signals from different sources, which is conducive to improving application flexibility and application scope, so that the circuit can adapt to a variety of input scenarios and multiple HDMI input signals. By integrating the two HDMI signal input modules and the corresponding processing functions in the first target chip, the design and wiring of the entire system can be simplified, which is conducive to reducing hardware complexity and cost, while improving reliability and stability. By supporting two HDMI signal inputs, the system can process and display multiple video streams at the same time, providing users with richer content and a better viewing experience, which is also conducive to improving the clarity and user experience of use and viewing.

[0097] In yet another optional embodiment, the second switching processing module 102 includes a second target chip, a second JTAG circuit, a second I2C circuit, and a second QSPI circuit, wherein:

[0098] The first end of the second target chip is electrically connected to the second end of the first switching processing module 101, the second end of the second target chip is used to electrically connect to the second signal input module, the third end of the second target chip is used to electrically connect to the signal output module 103, the fourth end of the second target chip is electrically connected to the first end of the second JTAG circuit, the fifth end of the second target chip is electrically connected to the first end of the second I2C circuit, and the sixth end of the second target chip is electrically connected to the first end of the second QSPI circuit.

[0099] In this optional embodiment, optionally, as Fig.10 As shown, Fig.10 is a schematic diagram of the structure of a second target chip disclosed in the utility model, wherein the components included in the second target chip and the connection method between the components can be as follows Fig.10 As shown;

[0100] Further, such as Fig.11 As shown, Fig.11The utility model discloses a second JTAG circuit structure diagram, wherein the second JTAG circuit includes components and the connection between the components can be as follows Fig.11 As shown;

[0101] Further, such as Fig.12 As shown, Fig.12 : is a schematic diagram of the structure of a second I2C circuit disclosed in the utility model, wherein the components included in the second I2C circuit and the connection method between the components can be as follows Fig.12 As shown;

[0102] Further, such as Fig.13 As shown, Fig.13 : is a schematic diagram of the structure of a second QSPI circuit disclosed in the utility model, wherein the components included in the second QSPI circuit and the connection method between the components can be as follows: Fig.13 shown.

[0103] In this optional embodiment, optionally, the second signal input module may include a three-way HDMI signal input module, wherein the three-way HDMI signal input module may include HDMIIN3, HDMIIN4 and HDMIIN5, and further, the HDMI input signal received by the second target chip may include an HDMI signal corresponding to HDMIIN3, an HDMI signal corresponding to HDMIIN4, an HDMI signal corresponding to HDMIIN5 and the first target signal, and the second target chip can be used to perform a second target processing operation on the three-way HDMI input signals and the first target signal to obtain a second target signal.

[0104] In this optional embodiment, optionally, the second target chip includes a GSV6705 chip, which is a high-performance, low-power four-input and one-output HDMI 2.1 repeater, wherein the GSV6705 chip integrates an enhanced microcontroller based on RISC-V, and the HDMI receiver and HDMI transmitter of the GSV6705 support up to 48Gbps (FRL, 12G / 4Lane); further, the four input ports of the GSV6705 can be configured as HDMI2.1 / HDMI2.0 / HDMI 1.4 respectively to meet different interface requirements.

[0105] In this optional embodiment, optionally, the second JTAG circuit includes a JTAG circuit; the second I2C circuit includes an I2C circuit; and the second QSPI circuit includes a QSPI circuit.

[0106] In this optional embodiment, optionally, the second signal input module may include a three-way HDMI signal input module, wherein the three-way HDMI signal input module may include HDMIIN3, HDMIIN4 and HDMIIN5, and further, the HDMI input signal received by the second target chip may include an HDMI signal corresponding to HDMIIN3, an HDMI signal corresponding to HDMIIN4, an HDMI signal corresponding to HDMIIN5 and the first target signal, and the second target chip can be used to perform a second target processing operation on the three-way HDMI input signals and the first target signal to obtain a second target signal.

[0107] It can be seen that the implementation of this optional embodiment can process the HDMI input signal corresponding to the second signal input module and the first target signal through the second target chip and output them to the signal output module 103, and through the coordinated operation of the second JTAG circuit, the second I2C circuit, and the second QSPI circuit, it is possible to integrate four HDMI input signals through the second target chip and perform corresponding second target processing operations, and it is possible to simultaneously receive and process multiple HDMI input signals, which is conducive to improving the efficiency and intelligence of performing the second target processing operation on the HDMI input signal, and is conducive to improving the efficiency and intelligence of obtaining the second target signal, and is conducive to improving the overall processing ability of the HDMI input signal. It has the power to integrate signals from different sources and integrate them into the second target chip to perform processing operations, which simplifies the process of processing HDMI input signals. The second target chip can process multiple HDMI signals and the first target signal, which can adapt to different application scenarios and needs. Whether it is necessary to display multiple video streams at the same time or to synthesize and analyze multiple signals, the requirements can be met by adjusting the processing strategy of the second target chip. By supporting multiple HDMI signal inputs, the system can process and display multiple video streams at the same time, providing users with richer content and a better viewing experience, which is also beneficial to improving the clarity and user experience of use and viewing.

[0108] In yet another optional embodiment, the second switching processing module 102 further includes a P_MODE circuit, wherein:

[0109] The first terminal of the P_MODE circuit is electrically connected to the seventh terminal of the second target chip.

[0110] In this optional embodiment, optionally, as Fig.14 As shown, Fig.14 : is a schematic diagram of a P_MODE circuit disclosed in the utility model, wherein the components included in the P_MODE circuit and the connection method between the components can be as follows Fig.14 shown.

[0111] In this optional embodiment, optionally, the P_MODE circuit is a P_MODE circuit, wherein this is a circuit with a specific working mode. According to different P_MODE settings, the P_MODE circuit will enter different working states. For example, when the working mode corresponding to P_MODE is 0, the P_MODE circuit is in an internal startup state; and when the working mode corresponding to P_MODE is 1, the P_MODE circuit enters a QSPI circuit startup state.

[0112] In this optional embodiment, optionally, for example, the P_MODE circuit can be a P_MODE circuit, wherein, if the working mode corresponding to P_MODE is 0, the state corresponding to the P_MODE circuit is an internal startup state; if the working mode corresponding to P_MODE is 1, the state corresponding to the P_MODE circuit is a QSPI circuit startup state.

[0113] It can be seen that the implementation of this optional embodiment can connect the P_MODE circuit to the second target chip, switch different working modes through the P_MODE circuit, and make the P_MODE circuit applicable to a variety of application scenarios to meet different communication and data processing requirements. By integrating the startup function of the QSPI circuit in the P_MODE circuit, the P_MODE circuit not only supports internal startup, but also can interact with the QSPI circuit to expand the functional scope, which is conducive to the realization of more complex communication and data transmission tasks. The P_MODE circuit has multiple working modes and can realize more functions without adding hardware components, reducing the overall cost and improving the efficiency and intelligence of operation. It can also adapt to specific application scenarios through the P_MODE circuit in different working modes. For example, in the internal startup mode, the MODE circuit can focus on initialization and configuration tasks; while in the QSPI circuit startup mode, it can efficiently exchange and communicate data with the QSPI circuit, which is conducive to improving the intelligence of circuit operation, and thus is conducive to improving the comfort and experience of users, and is also conducive to improving the matching degree between the output signal and user needs.

[0114] In yet another optional embodiment, Fig.15 As shown, Fig.15 It is a structural diagram of another circuit for adaptively adjusting gain disclosed in the utility model, the circuit also includes a first signal input module 105 and a second signal input module 106, wherein the number of the first signal input module 105 is at least one, and the number of the second signal input module 106 is at least one.

[0115] In this optional embodiment, optionally, the number of the first signal input modules 105 may be two, and the number of the second signal input modules 106 may be three.

[0116] In this optional embodiment, further optionally, the first signal input module 105 is used to receive two HDMI input signals and transmit the two HDMI input signals to the first switching processing module 101 so as to perform a first target processing operation on the two HDMI input signals through the first switching processing module 101 to obtain a first target signal, and transmit the first target signal to the second switching processing module 102, and the first target signal includes an HDMI signal; the second signal input module 106 is used to receive three HDMI input signals, and transmit the three HDMI input signals to the second switching processing module 102 so as to perform a second target processing operation on the second target signal and the three HDMI input signals through the second switching processing module 102 to obtain a second target signal transmitted to a preset target device.

[0117] It can be seen that the implementation of this optional embodiment can collect multiple HDMI input signals through the first signal input module 105 and the second signal input module 106, and can simultaneously receive and process HDMI input signals from different sources through the first signal input module 105 and the second signal input module 106, which is conducive to improving application flexibility and application scope, so that the circuit can adapt to a variety of input scenarios and multiple HDMI input signals. By integrating multiple HDMI signal input modules and corresponding processing functions, the design and wiring of the entire system can be simplified, which is conducive to reducing hardware complexity and cost, while improving reliability and stability. By supporting multiple HDMI signal inputs, the system can process and display multiple video streams at the same time, providing users with richer content and a better viewing experience, which is also conducive to improving the clarity and user experience of use and viewing.

[0118] In yet another optional embodiment, the first signal input module 105 includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

[0119] The first end of the target input chip is electrically connected to the first end of the first switching processing module 101, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

[0120] In this optional embodiment, optionally, the components and connection relationship included in the second signal input module 106 are the same as those of the first signal input module 105 .

[0121] In this optional embodiment, optionally, as Fig.16 As shown, Fig.16 is a schematic diagram of the structure of a target input chip disclosed in the utility model, wherein the components included in the target input chip and the connection method between the components can be as follows Fig.16 As shown;

[0122] Further, such as Fig.17 As shown, Fig.17 The utility model discloses a schematic diagram of the structure of an input ESD processing circuit, wherein the components included in the input ESD processing circuit and the connection method between the components can be as follows: Fig.17 As shown;

[0123] Further, such as Fig.18 As shown, Fig.18 The utility model discloses a structural diagram of an input DDC processing circuit, wherein the components included in the input DDC processing circuit and the connection method between the components can be as follows Fig.18 As shown;

[0124] Further, such as Fig.19 As shown, Fig.19 The utility model discloses a schematic diagram of the structure of an input HPD processing circuit, wherein the components included in the input HPD processing circuit and the connection method between the components can be as follows: Fig.19 shown.

[0125] In this optional embodiment, optionally, the target input chip may be a HDMI_A_SMD chip; further, the target input chip may be a HDMI_RX_23P_SMT_0228 chip.

[0126] In this optional embodiment, the input ESD processing circuit optionally includes an ESD protection circuit, wherein the ESD protection circuit is a circuit design for protecting electronic components from external electrostatic discharge damage. Electrostatic discharge refers to a short-term high-voltage discharge phenomenon caused by an imbalance of charge, which can cause irreversible damage to sensitive electronic devices. The design goal of the ESD protection circuit is to guide the energy of external electrostatic discharge to a safe place to prevent it from causing damage to electronic equipment.

[0127] In this optional embodiment, optionally, the input DDC processing circuit includes a DDC processing circuit, wherein the DDC processing circuit is the abbreviation of a digital downconverter processing circuit, which is used in a communication system to mix with a sinusoidal signal (local oscillator) generated by a local oscillator, thereby changing the frequency band in which the signal is located. Specifically, increasing the frequency is up-conversion, and reducing the frequency is down-conversion. Wherein, the DDC processing circuit includes at least one pull-up resistor, wherein the pull-up resistor is a resistor device, and its main function is to pull a certain signal pin to a high level so that the signal remains in a high level state. The pull-up resistor is usually used together with the pull-down resistor to control the signal transmission and logic function of the circuit. Further, the input signal of the video input chip is maintained at a high level of the signal by the pull-up resistor, which can avoid the signal from having a bad level, can be conducive to improving the accuracy and reliability of the input signal, and can improve the driving ability of the video input chip.

[0128] In this optional embodiment, the input HPD processing circuit optionally includes an HPD input level conversion circuit, wherein the HPD input level conversion circuit is a circuit specifically used to process HPD (high voltage discharge) signals, and its main function is to convert the level of the input HPD signal into a range suitable for subsequent circuit processing. For example, if the voltage corresponding to the device connected to the video input chip is 5V, and the operating voltage corresponding to the video input chip is 3.3V, then the voltage corresponding to the device connected to the video input chip does not match the voltage corresponding to the video input chip, then the HPD conversion submodule performs a level conversion operation, converting the voltage corresponding to the device connected to the video input chip of 5V to the voltage corresponding to the video input chip of 3.3V, so as to ensure the normal operation of the chip and prevent the chip from being damaged by high voltage.

[0129] In this optional embodiment, optionally, for example, an HDMI input signal is collected through a target input chip, and an electrostatic protection operation is performed on the target input chip through an input ESD processing circuit to prevent external static electricity from entering the target input chip and causing damage to the target input chip, and the driving capability of the target input chip is improved through an input DDC processing circuit, and a level conversion operation is performed through an input HPD processing circuit, which can effectively protect the target input chip from being damaged by external high voltage.

[0130] It can be seen that the implementation of this optional embodiment can collect the HDMI input signal through the target input chip in the first signal input module 105, and improve the driving ability of the target input chip through the input DDC processing circuit, and eliminate the influence of the outside world on the target input chip through the input ESD processing circuit, and perform the level conversion operation through the input HPD processing circuit, and can effectively improve the driving ability of the target input chip through the input DDC processing submodule, which is conducive to improving the stability and high quality of the HDMI input signal during the data transmission process, and when transmitting over long distances or in complex environments, it can reduce signal attenuation and distortion, thereby improving the performance of the overall system, and through the input ESD processing The processing circuit can effectively absorb and disperse the energy of electrostatic discharge, protect the target input chip from damage, and improve the stability and reliability of the equipment. The input HPD processing circuit can help ensure that the signals between different modules can be correctly matched and transmitted, avoiding signal distortion or errors caused by level mismatch. Among them, level conversion is a key step in circuit design, which can make the entire system more flexible and compatible, thereby helping to improve the flexibility and compatibility of the target input chip, thereby achieving the improvement and protection of the target input chip performance, and at the same time improving the stability and reliability of the entire system, which is conducive to improving the accuracy, reliability and intelligence of realizing adaptive gain adjustment.

[0131] In another optional embodiment, the circuit for adaptively adjusting gain further includes a signal output module 103; wherein the signal output module 103 includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, wherein:

[0132] The third end of the second switching processing module 102 is electrically connected to the first end of the target output chip, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output circuit is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output circuit is electrically connected to the first end of the current limiting protection circuit.

[0133] In this optional embodiment, optionally, as Fig. 20 As shown, Fig. 20 is a schematic diagram of the structure of a target output chip disclosed in the utility model, wherein the components included in the target output chip and the connection method between the components can be as follows Fig. 20 As shown;

[0134] Further, such as Fig.21 As shown, Fig.21The utility model discloses a schematic diagram of the structure of an output ESD processing circuit, wherein the components included in the output ESD processing circuit and the connection method between the components can be as follows Fig.21 As shown;

[0135] Further, such as Fig. 22 As shown, Fig. 22 The utility model discloses a structural diagram of an output DDC processing circuit, wherein the components included in the output DDC processing circuit and the connection method between the components can be as follows Fig. 22 As shown;

[0136] Further, such as Fig.23 As shown, Fig.23 The utility model discloses a schematic diagram of the structure of an output HPD processing circuit, wherein the components included in the output HPD processing circuit and the connection method between the components can be as follows: Fig.23 As shown;

[0137] Further, such as Fig.24 As shown, Fig.24 The utility model discloses a structural diagram of a current limiting protection circuit, wherein the components included in the current limiting protection circuit and the connection method between the components can be as follows Fig.24 shown.

[0138] In this optional embodiment, optionally, the current limiting protection circuit includes a current limiting short circuit protection circuit, wherein the current limiting short circuit protection circuit is an electronic protection circuit, wherein it is intended to limit current and provide protection in the event of a short circuit. Further, the basic principle of the current limiting short circuit protection circuit is to monitor the magnitude of the current and trigger protection measures when the current exceeds a certain threshold. Furthermore, specific protection measures may include one or more of cutting off power supply, reducing output voltage, and limiting current to prevent excessive current caused by a short circuit from damaging the circuit.

[0139] In this optional embodiment, optionally, the target output chip may be a HDMI_A_SMD chip; further, the target output chip may be a HDMI_RX_23P_SMT_0228 chip.

[0140] In this optional embodiment, optionally, the second target signal is transmitted to a preset target device through the target output chip, and the driving capability of the target output chip is improved through the output DDC processing circuit, and a level conversion operation is performed on the level signal corresponding to the output DDC processing circuit and the level signal corresponding to the output ESD processing circuit according to the output HPD processing circuit, so that the levels between the electronic components are balanced with each other, which can effectively protect the target output chip from being damaged by external high voltage, and can also prevent short circuits and burning of the target output chip through current limiting protection circuits.

[0141] It can be seen that the implementation of this optional embodiment can transmit the second target signal to the preset target device through the target output chip, and improve the driving ability of the target output chip through the output DDC processing circuit, and perform level conversion operations on the level signal corresponding to the output DDC processing circuit and the level signal corresponding to the output HPD processing circuit through the output HPD processing current, and eliminate the influence of static electricity on the target output chip through the output ESD processing circuit, and prevent the target output chip from short-circuiting and burning the chip through the current limiting protection circuit. The driving ability of the target output chip can be significantly improved through the output DDC processing circuit, which is conducive to making the video signal more stable and more efficiently transmitted to the target device, and the output HPD processing circuit not only realizes the conversion of the output level signal of the output DDC processing circuit, but also processes the level signal of the output ESD processing circuit, so that the signal is ensured through double level conversion. The accuracy and completeness of the system enable the entire system to adapt to a variety of different devices or interfaces, greatly improving compatibility. The output ESD processing circuit provides effective electrostatic protection for the target output chip to prevent external static electricity from having a negative impact on the video output chip. Once a short circuit is detected through the current limiting protection circuit, the circuit can quickly cut off or limit the current to avoid irreversible damage to the chip and other related components. This not only optimizes the transmission and processing of HDMI signals, but also strengthens the system's protection mechanism, so that it can operate stably and safely in the face of various challenges, and then can also achieve the performance improvement and protection of the target output chip, while also improving the stability and reliability of the entire system, which is conducive to improving the accuracy, reliability and intelligence of achieving adaptive gain adjustment.

[0142] In yet another optional embodiment, the target control module 104 includes a control chip and a CEC circuit, wherein:

[0143] The first end of the control chip is electrically connected to the third end of the first switching processing module 101 , the second end of the control chip is electrically connected to the fourth end of the second switching processing module 102 , and the third end of the control chip is electrically connected to the first end of the CEC circuit.

[0144] In this optional embodiment, optionally, as Fig.25 As shown, Fig.25 is a schematic diagram of the structure of a control chip disclosed in the utility model, wherein the components included in the control chip and the connection method between the components can be as follows Fig.25 As shown;

[0145] Further, such as Fig.26 As shown, Fig.26 The utility model discloses a CEC circuit structure diagram, wherein the components included in the CEC circuit and the connection between the components can be as follows Fig.26 shown.

[0146] In this optional embodiment, optionally, the control chip may include a GD32F330CBT6 chip.

[0147] In this optional embodiment, optionally, the CEC circuit is mainly related to the communication and control between HDMI interface devices. It is a bidirectional data signal with a high level of 3.3V. When the level of the HDMI source controller chip is inconsistent with this level, a level conversion is required, which can be achieved by a level conversion chip or using an NMOS level conversion circuit. At the same time, the CEC signal is usually an open-drain output in the HDMI source controller chip, so a pull-up resistor is required; further, the CEC bus can transmit addresses, commands, data, etc. on one cable, thereby realizing control of all devices connected to the HDMI interface.

[0148] It can be seen that the implementation of this optional embodiment can quickly respond to and accurately control the working state of each module or circuit through the control chip and the CEC circuit. Since the CEC circuit is mainly used for control and communication between HDMI devices, this connection method enables the control chip to obtain and process the signal transmitted by the CEC circuit in real time, and realizes rapid response and accurate control of the HDMI device. Through modular design, the system can more flexibly respond to different application requirements. When a new function or module needs to be added, it is only necessary to electrically connect the new module to the control chip accordingly to realize the upgrade and expansion of the system. In addition, this connection method between the control chip and the first switching processing module 101, the second switching processing module 102 and the CEC circuit not only realizes modular communication and control, improves the response speed and control accuracy of the system, but also enhances the flexibility and scalability of the system, improves the reliability of the system, makes the entire system more efficient, stable, reliable and flexible, and can meet various complex application requirements, and further can realize the improvement and protection of the performance of the target output chip, and also improves the stability and reliability of the entire system, and further realizes the improvement and protection of the performance of the target output chip, and also improves the stability and reliability of the entire system, and further helps to improve the accuracy, reliability and intelligence of realizing adaptive gain adjustment.

[0149] Embodiment 2

[0150] See also Fig. 27 , Fig. 27 : is a schematic diagram of the structure of a switch disclosed in an embodiment of the utility model, and the electronic product includes a circuit for adaptively adjusting gain as in any one of the embodiments. And the adaptive gain adjustment function that can be achieved by the electronic product includes but is not limited to being able to adaptively adjust the gain to improve the quality of the output signal, thereby helping to improve the user experience. It should be noted that for a detailed description of the switch, please refer to the specific description of the relevant content in the embodiment one, and this embodiment will not be repeated.

[0151] It can be seen that implementation Fig. 27 The electronic product described can adaptively adjust the gain to improve the quality of the output signal, thereby helping to improve the user experience.

[0152] The above is a detailed introduction to the circuit and switch for adaptively adjusting gain disclosed in the embodiment of the utility model. Specific embodiments are used in this article to illustrate the principle and implementation method of the utility model, but the above preferred embodiments are not used to limit the utility model. The description of the above embodiments is only used to help understand the method of the utility model and its core idea. At the same time, for general technical personnel in this field, according to the idea of ​​the utility model, without departing from the spirit and scope of the utility model, there will be changes in the specific implementation method and application scope. Therefore, the scope of protection of the utility model is defined by the claims.

Claims

1. A circuit for adaptively adjusting gain, characterized in that: The circuit for adaptively adjusting gain includes a first switching processing module, a second switching processing module, and a signal output module, wherein: The first end of the first switching processing module is used to electrically connect to the first signal input module, the second end of the first switching processing module is electrically connected to the first end of the second switching processing module, the second end of the second switching processing module is used to electrically connect to the second signal input module, and the third end of the second switching processing module is electrically connected to the first end of the signal output module; The first switching processing module is configured to receive the first input signal transmitted by the first signal input module, perform a first target processing operation on the first input signal, obtain a first target signal, and transmit the first target signal to the second switching processing module; The second switching processing module is configured to receive the second input signal transmitted by the second signal input module, and perform a processing operation on the first target signal and the second input signal to transmit to a second target, obtain a second target signal, and transmit the second target signal to the signal output module; The signal output module is used to transmit the received second target signal to a preset target device.

2. The circuit for adaptively adjusting gain according to claim 1, characterized in that: The circuit for adaptively adjusting gain further includes a target control module, wherein: The first end of the target control module is electrically connected to the third end of the first switching processing module, and the second end of the target control module is electrically connected to the fourth end of the second switching processing module; The target control module is configured to determine a signal type corresponding to the first target signal and a signal type corresponding to the second target signal.

3. The circuit for adaptively adjusting gain according to claim 2, characterized in that: The first switching processing module includes a first target chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first AUDIO circuit, wherein: The first end of the first target chip is used to electrically connect to the first signal input module, the second end of the first target chip is electrically connected to the first end of the second switching processing module, the third end of the first target chip is electrically connected to the first end of the target control module, the fourth end of the first target chip is electrically connected to the first end of the first JTAG circuit, the fifth end of the first target chip is electrically connected to the first end of the first I2C circuit, the sixth end of the first target chip is electrically connected to the first end of the first QSPI circuit, and the seventh end of the first target chip is electrically connected to the first end of the first AUDIO circuit.

4. The circuit for adaptively adjusting gain according to claim 2, wherein: The second switching processing module includes a second target chip, a second JTAG circuit, a second I2C circuit, and a second QSPI circuit, wherein: The first end of the second target chip is electrically connected to the second end of the first switching processing module, the second end of the second target chip is used to electrically connect to the second signal input module, the third end of the second target chip is used to electrically connect to the signal output module, the fourth end of the second target chip is electrically connected to the first end of the second JTAG circuit, the fifth end of the second target chip is electrically connected to the first end of the second I2C circuit, and the sixth end of the second target chip is electrically connected to the first end of the second QSPI circuit.

5. The circuit for adaptively adjusting gain according to claim 4, characterized in that: The second switching processing module further includes a P_MODE circuit, wherein: The first terminal of the P_MODE circuit is electrically connected to the seventh terminal of the second target chip.

6. The circuit for adaptively adjusting gain according to claim 1, characterized in that: The circuit for adaptively adjusting gain further includes the first signal input module and the second signal input module, wherein the number of the first signal input module is at least one and the number of the second signal input module is at least one.

7. The circuit for adaptively adjusting gain according to claim 6, characterized in that: The first signal input module includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein: The first end of the target input chip is electrically connected to the first end of the first switching processing module, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

8. The circuit for adaptively adjusting gain according to claim 1, characterized in that: The circuit for adaptively adjusting gain further includes the signal output module; wherein the signal output module includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, wherein: The third end of the second switching processing module is electrically connected to the first end of the target output chip, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output circuit is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output circuit is electrically connected to the first end of the current limiting protection circuit.

9. The circuit for adaptively adjusting gain according to claim 2, characterized in that: The target control module includes a control chip and a CEC circuit, wherein: The first end of the control chip is electrically connected to the third end of the first switching processing module, the second end of the control chip is electrically connected to the fourth end of the second switching processing module, and the third end of the control chip is electrically connected to the first end of the CEC circuit.

10. A switch, comprising an input port for receiving an HDMI signal, the circuit for adaptively adjusting gain according to any one of claims 1 to 9, and an output port for outputting a second output signal.

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