Array substrate

Abstract

The utility model discloses an array substrate which comprises a substrate body, a plurality of data lines, a plurality of scanning lines and a plurality of thin film transistors, and the data lines are arranged on the substrate body and extend in the column direction; the scanning lines are arranged on the substrate and extend in the row direction, and the scanning lines and the data lines define a plurality of pixel areas arranged in an array mode; the plurality of thin film transistor arrays are arranged on the substrate, and thin film transistors are electrically connected with the data lines; at least part of the thin film transistor is overlapped with the data line in the direction perpendicular to the plane where the substrate is located. The utility model aims to improve the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate. Background Art

[0002] In a traditional array substrate, a thin film transistor is arranged as a pixel switch in a pixel area surrounded by a data line and a scan line. Since the thin film transistor has a certain size, when the thin film transistor is arranged in the pixel area, the ratio of the effective light emitting area of ​​the pixel to the overall area of ​​the pixel will decrease, so that the aperture ratio of the array substrate is reduced, resulting in a decrease in the display effect of the display panel.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0004] The purpose of the present application is to provide an array substrate to improve the display effect.

[0005] To solve the above problems, the technical solution of this application is as follows:

[0006] In a first aspect, the present application proposes an array substrate, comprising:

[0007] substrate;

[0008] A plurality of data lines are provided on the substrate and extend along a column direction;

[0009] A plurality of scan lines are arranged on the substrate and extend along the row direction, wherein the scan lines and the data lines enclose a plurality of pixel areas arranged in an array; and

[0010] A plurality of thin film transistors are arranged in an array on the substrate, and the thin film transistors are electrically connected to the data lines;

[0011] Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the thin film transistor overlaps with the data line.

[0012] In one embodiment of the present application, the thin film transistor includes:

[0013] A gate, disposed on the substrate and electrically connected to the scan line;

[0014] A first insulating layer, disposed on the substrate and covering the gate;

[0015] a semiconductor layer, disposed on the first insulating layer, the semiconductor layer being electrically connected to the data line; and

[0016] A drain electrode, disposed on the upper surface of the semiconductor layer and electrically connected to the semiconductor layer;

[0017] Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the semiconductor layer overlaps with the gate, and at least a portion of the semiconductor layer overlaps with the data line.

[0018] In one embodiment of the present application, a portion of the data line is disposed on the upper surface of the semiconductor layer, and the data line is disposed in the same layer as the drain electrode.

[0019] In one embodiment of the present application, the semiconductor layer includes:

[0020] a channel portion, wherein the channel portion is disposed on the first insulating layer;

[0021] A first doping portion is provided on an upper surface of the channel portion; and

[0022] A second doping portion is disposed on the upper surface of the channel portion and is spaced apart from the first doping portion;

[0023] Wherein, the drain electrode is disposed on the upper surface of the first doped portion, and a portion of the data line is disposed on the upper surface of the second doped portion;

[0024] In a direction perpendicular to a plane where the substrate is located, at least a portion of the channel portion overlaps with the gate, and at least a portion of the channel portion overlaps with the data line.

[0025] In one embodiment of the present application, the thin film transistor includes:

[0026] A gate, disposed on the substrate and electrically connected to the scan line;

[0027] A first insulating layer, disposed on the substrate and covering the gate;

[0028] A semiconductor layer, disposed on the first insulating layer, wherein the semiconductor layer is electrically connected to the data line;

[0029] A drain electrode, disposed on the first insulating layer and electrically connected to the semiconductor layer;

[0030] Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the semiconductor layer overlaps with the gate, and at least a portion of the semiconductor layer overlaps with the data line.

[0031] In one embodiment of the present application, a portion of the data line is disposed on the upper surface of the semiconductor layer, and the data line and the drain electrode are disposed in a different layer.

[0032] In one embodiment of the present application, the semiconductor layer includes:

[0033] a channel portion, wherein the channel portion is disposed on the first insulating layer;

[0034] a first doping portion, disposed on the first insulating layer and connected to the channel portion; and

[0035] A second doping portion, disposed on an upper surface of the channel portion;

[0036] Wherein, the drain electrode is disposed on the upper surface of the first doped portion, and a portion of the data line is disposed on the upper surface of the second doped portion;

[0037] In a direction perpendicular to a plane where the substrate is located, at least a portion of the channel portion overlaps with the gate, and at least a portion of the channel portion overlaps with the data line.

[0038] In an embodiment of the present application, at least a portion of an orthographic projection of the drain on the substrate is located outside a range of an orthographic projection of the gate on the substrate.

[0039] In one embodiment of the present application, one of the data lines is electrically connected to a plurality of the thin film transistors;

[0040] Wherein, in a direction perpendicular to the plane where the substrate is located, one of the data lines overlaps at least partially with a plurality of the thin film transistors.

[0041] In an embodiment of the present application, the source of the thin film transistor includes a portion where the data line overlaps the semiconductor layer.

[0042] In the second aspect, the present application proposes a display panel, comprising an array substrate, wherein the array substrate comprises: a substrate; a plurality of data lines, arranged on the substrate and extending in a column direction; a plurality of scan lines, arranged on the substrate and extending in a row direction, the scan lines and the data lines forming a plurality of array-arranged pixel areas; a plurality of thin film transistors, array-arranged on the substrate, the thin film transistors being electrically connected to the data lines; wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the thin film transistors overlaps with the data lines.

[0043] In the present application, the thin film transistor and the data line at least partially overlap in a direction perpendicular to the plane where the substrate is located, thereby reducing the occupied area of ​​the thin film transistor in the pixel area, increasing the ratio of the effective light-emitting area of ​​the pixel to the overall area of ​​the pixel, and increasing the aperture ratio of the array substrate, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a top view of an embodiment of an array substrate of the present application;

[0045] Figure 2 yes Figure 1 The enlarged view of point A in the middle;

[0046] Figure 3 yes Figure 2 A schematic diagram of a sectional line DD' of the array substrate shown;

[0047] Figure 4 is a top view of another embodiment of the array substrate of the present application;

[0048] Figure 5 yes Figure 4 The enlarged view of point B in the middle;

[0049] Figure 6 yes Figure 5 A schematic diagram of the EE' section line of the array substrate shown;

[0050] Figure 7 is a top view of a conventional array substrate;

[0051] Figure 8 yes Figure 7 Enlarged view of point C in the middle. DETAILED DESCRIPTION

[0052] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0053] The present application proposes a display panel, which may be an LCD, an OLED, or an MLED. The display panel includes an array substrate 100 .

[0054] See also Figure 1 and Figure 4 , the present application proposes an array substrate 100, comprising:

[0055] Substrate 10;

[0056] A plurality of data lines 20 are provided on the substrate 10 and extend along a column direction;

[0057] A plurality of scan lines 30 are disposed on the substrate 10 and extend along a row direction, wherein the scan lines 30 and the data lines 20 form a plurality of pixel areas PA arranged in an array; and

[0058] A plurality of thin film transistors 40 are arrayed on the substrate 10, and the thin film transistors 40 are electrically connected to the data lines 20;

[0059] In a direction perpendicular to the plane where the substrate 10 is located, at least a portion of the thin film transistor 40 overlaps with the data line 20 .

[0060] In the present application, the thin film transistor 40 and the data line 20 at least partially overlap in a direction perpendicular to the plane where the substrate 10 is located, thereby reducing the occupied area of ​​the thin film transistor 40 in the pixel area PA, increasing the ratio of the effective light-emitting area of ​​the pixel to the overall area of ​​the pixel, and improving the aperture ratio of the array substrate 100, thereby improving the display effect of the display panel.

[0061] In the present application, the row direction intersects or is perpendicular to the column direction. A plurality of data lines 20 are arranged along the row direction, and a plurality of scan lines 30 are arranged along the column direction. Two adjacent data lines 20 and two adjacent scan lines 30 form a pixel area PA, and a plurality of array substrates 100 have a plurality of pixel areas PA arranged in an array.

[0062] See also Figure 7 and Figure 8 In the conventional array substrate 100, the thin film transistor 40 does not overlap with the data line 20 in the direction perpendicular to the plane where the substrate 10 is located, resulting in a large area occupied by the thin film transistor 40 in the pixel area PA. Since the thin film transistor 40 is opaque, when the thin film transistor 40 is set in the area occupied by the pixel area PA, the effective light emitting area of ​​the pixel is reduced, while the overall area of ​​the pixel area PA remains unchanged, so that the ratio of the effective light emitting area of ​​the pixel to the overall area of ​​the pixel is reduced, and the aperture ratio of the array substrate 100 is reduced, resulting in a decrease in the display effect of the display panel.

[0063] See also Figure 1 and Figure 4 In the array substrate 100 of the present application, at least part of the thin film transistor 40 overlaps with the data line 20 in a direction perpendicular to the plane where the substrate 10 is located. When the overlapping area between the thin film transistor 40 and the data line 20 is relatively increased, the occupied area of ​​the thin film transistor 40 in the pixel area PA is relatively reduced, the effective light emitting area of ​​the pixel is increased, and the overall area of ​​the pixel area PA remains unchanged, so that the ratio of the effective light emitting area of ​​the pixel to the overall area of ​​the pixel is increased, the aperture ratio of the array substrate 100 is increased, and the display effect of the display panel is improved.

[0064] In one embodiment of the present application, the thin film transistor 40 includes:

[0065] A gate 41 is disposed on the substrate 10 and electrically connected to the scanning line 30;

[0066] A first insulating layer 42 is disposed on the substrate 10 and covers the gate 41;

[0067] a semiconductor layer 43 disposed on the first insulating layer 42, wherein the semiconductor layer 43 is electrically connected to the data line 20; and

[0068] a drain electrode 44, disposed on the upper surface of the semiconductor layer 43 and electrically connected to the semiconductor layer 43;

[0069] In a direction perpendicular to the plane where the substrate 10 is located, at least a portion of the semiconductor layer 43 overlaps with the gate 41 , and at least a portion of the semiconductor layer 43 overlaps with the data line 20 .

[0070] See also Figure 1 , Figure 2 and Figure 3 In this embodiment, the array substrate 100 includes a first metal layer, wherein the first metal layer includes a scanning line 30 and a gate 41 that are arranged in the same layer and connected to each other, a first insulating layer 42 covers the upper surface of the gate 41, and a semiconductor layer 43 is arranged on the first insulating layer 42.

[0071] In one embodiment, the array substrate 100 includes a second metal layer, the second metal layer is disposed on the semiconductor layer 43, and the second metal layer includes a source electrode and a drain electrode 44 disposed in the same layer, wherein the source electrode and the drain electrode 44 are disposed at intervals on the upper surface of the semiconductor layer 43, the source electrode overlaps the semiconductor layer 43, and the drain electrode 44 overlaps the semiconductor layer 43. The array substrate 100 also includes a third metal layer, the third metal layer includes a plurality of data lines 20 disposed in the same layer, the data line 20 is located above the source electrode and is electrically connected to the source electrode. In a direction perpendicular to the plane where the substrate 10 is located, the data line 20 at least partially overlaps the source electrode.

[0072] See also Figure 3 In another embodiment, the array substrate 100 includes a second metal layer, the second metal layer is disposed on the semiconductor layer 43, and the second metal layer includes a drain electrode 44 and a data line 20 disposed in the same layer, wherein the drain electrode 44 and the data line 20 are spaced apart on the upper surface of the semiconductor layer 43, the drain electrode 44 overlaps the semiconductor layer 43, and the data line 20 overlaps the semiconductor layer 43. In this embodiment, the portion of the data line 20 located on the thin film transistor 40 serves as the source of the thin film transistor 40.

[0073] See also Figure 2When the data line 20 serves as the source of the thin film transistor 40, in order to reduce the leakage current of the thin film transistor 40, in a direction perpendicular to the plane where the substrate 10 is located, the distance between the drain electrode 44 and the data line 20 is in the range of 3μm to 5μm, wherein the distance between the drain electrode 44 and the data line 20 is one of 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, 4.0μm, 4.1μm, 4.2μm, 4.3μm, 4.4μm, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm, and 5μm.

[0074] In an embodiment of the present application, the array substrate 100 further includes a passivation layer 50 , and the passivation layer 50 covers the drain electrode 44 , the semiconductor layer 43 and the data line 20 .

[0075] In an embodiment of the present application, a portion of the data line 20 is disposed on the upper surface of the semiconductor layer 43 , and the data line 20 and the drain electrode 44 are disposed in the same layer.

[0076] See also Figure 3 In this embodiment, the array substrate 100 includes a second metal layer, which is disposed on the semiconductor layer 43. The second metal layer includes a drain electrode 44 and a data line 20 disposed on the same layer, wherein the drain electrode 44 and the data line 20 are spaced apart on the upper surface of the semiconductor layer 43, the drain electrode 44 overlaps the semiconductor layer 43, and the data line 20 overlaps the semiconductor layer 43. In this embodiment, the portion of the data line 20 located on the thin film transistor 40 serves as the source of the thin film transistor 40.

[0077] In one embodiment of the present application, the semiconductor layer 43 includes:

[0078] a channel portion 431 , wherein the channel portion 431 is disposed on the first insulating layer 42 ;

[0079] a first doping portion 432 disposed on an upper surface of the channel portion 431; and

[0080] The second doping portion 433 is disposed on the upper surface of the channel portion 431 and is spaced apart from the first doping portion 432 ;

[0081] The drain electrode 44 is disposed on the upper surface of the first doped portion 432 , and a portion of the data line 20 is disposed on the upper surface of the second doped portion 433 ;

[0082] In a direction perpendicular to the plane where the substrate 10 is located, at least a portion of the channel portion 431 overlaps with the gate 41 , and at least a portion of the channel portion 431 overlaps with the data line 20 .

[0083] See also Figure 3 The material of the semiconductor layer 43 includes amorphous silicon (a-Si). In order to improve the ohmic contact resistance between the semiconductor layer 43 and the drain electrode 44 and the data line 20, a phosphorus (P)-containing gas is introduced during the process of manufacturing the semiconductor layer 43 to make the portion of the semiconductor layer 43 in contact with the drain electrode 44 and the data line 20 conductive, and to form a first doping portion 432 and a second doping portion 433 respectively, so that the drain electrode 44 is in ohmic contact with the first doping portion 432, and the data line 20 is in ohmic contact with the second doping portion 433, thereby improving the electron mobility and on-state current of the semiconductor layer 43 to improve the display effect.

[0084] In one embodiment of the present application, the thin film transistor 40 includes:

[0085] A gate 41 is disposed on the substrate 10 and electrically connected to the scanning line 30;

[0086] A first insulating layer 42 is disposed on the substrate 10 and covers the gate 41;

[0087] A semiconductor layer 43 is disposed on the first insulating layer 42 , and the semiconductor layer 43 is electrically connected to the data line 20 ;

[0088] A drain electrode 44 is disposed on the first insulating layer 42 and electrically connected to the semiconductor layer 43;

[0089] In a direction perpendicular to the plane where the substrate 10 is located, at least a portion of the semiconductor layer 43 overlaps with the gate 41 , and at least a portion of the semiconductor layer 43 overlaps with the data line 20 .

[0090] See also Figure 4 , Figure 5 and Figure 6 In this embodiment, the array substrate 100 includes a first metal layer, wherein the first metal layer includes a scanning line 30 and a gate 41 that are arranged in the same layer and connected to each other, a first insulating layer 42 covers the upper surface of the gate 41, and a semiconductor layer 43 is arranged on the first insulating layer 42.

[0091] In one embodiment, the array substrate 100 includes a second metal layer, which is disposed on the first insulating layer 42 and disposed in the same layer as the semiconductor layer 43. The second metal layer includes a drain electrode 44, which overlaps the side surface of the semiconductor layer 43. The array substrate 100 also includes a third metal layer, which is disposed on the upper surface of the semiconductor layer 43, and the third metal layer includes a source electrode, which overlaps the upper surface of the semiconductor layer 43. The array substrate 100 also includes a fourth metal layer including a plurality of data lines 20 disposed in the same layer, the data line 20 is located above the source electrode, and is electrically connected to the source electrode. In a direction perpendicular to the plane where the substrate 10 is located, the data line 20 at least partially overlaps the source electrode.

[0092] See also Figure 6 In another embodiment, the array substrate 100 includes a second metal layer, which is disposed on the first insulating layer 42 and is disposed in the same layer as the semiconductor layer 43. The second metal layer includes a drain electrode 44, which overlaps the side of the semiconductor layer 43. The array substrate 100 also includes a third metal layer, which is disposed on the upper surface of the semiconductor layer 43, and the third metal layer includes a data line 20, which overlaps the semiconductor layer 43. In this embodiment, the portion of the data line 20 located on the semiconductor layer 43 serves as the source of the thin film transistor 40.

[0093] Preferably, in a direction perpendicular to the plane where the substrate 10 is located, the drain 44 and the gate 41 do not overlap, so as to reduce the parasitic resistance generated by the overlap of the drain 44 and the gate 41 .

[0094] Preferably, the orthographic projection of the drain 44 on the substrate 10 is outside the range of the orthographic projection of the gate 41 on the substrate 10 , and the orthographic projection of the drain 44 on the substrate 10 is outside the range of the orthographic projection of the channel portion 431 on the substrate 10 .

[0095] In an embodiment of the present application, a portion of the data line 20 is disposed on the upper surface of the semiconductor layer 43 , and the data line 20 and the drain electrode 44 are disposed in different layers.

[0096] See also Figure 6 , the array substrate 100 includes a second metal layer, which is disposed on the first insulating layer 42 and is disposed in the same layer as the semiconductor layer 43. The second metal layer includes a drain electrode 44, which overlaps the side of the semiconductor layer 43. The array substrate 100 also includes a third metal layer, which is disposed on the upper surface of the semiconductor layer 43, and the third metal layer includes a data line 20, which overlaps the semiconductor layer 43. In this embodiment, the portion of the data line 20 located on the semiconductor layer 43 serves as the source of the thin film transistor 40.

[0097] In one embodiment of the present application, the semiconductor layer 43 includes:

[0098] a channel portion 431 , wherein the channel portion 431 is disposed on the first insulating layer 42 ;

[0099] A first doping portion 432 is disposed on the first insulating layer 42 and connected to the channel portion 431; and

[0100] a second doping portion 433 disposed on an upper surface of the channel portion 431;

[0101] The drain electrode 44 is disposed on the upper surface of the first doped portion 432 , and a portion of the data line 20 is disposed on the upper surface of the second doped portion 433 ;

[0102] In a direction perpendicular to the plane where the substrate 10 is located, at least a portion of the channel portion 431 overlaps with the gate 41 , and at least a portion of the channel portion 431 overlaps with the data line 20 .

[0103] See also Figure 6 The material of the semiconductor layer 43 includes amorphous silicon (a-Si). In order to improve the ohmic contact resistance between the semiconductor layer 43 and the drain electrode 44 and the data line 20, a phosphorus (P)-containing gas is introduced during the process of manufacturing the semiconductor layer 43 to make the portion of the semiconductor layer 43 in contact with the drain electrode 44 and the data line 20 conductive, and to form a first doping portion 432 and a second doping portion 433 respectively, so that the drain electrode 44 is in ohmic contact with the first doping portion 432, and the data line 20 is in ohmic contact with the second doping portion 433, thereby improving the electron mobility and on-state current of the semiconductor layer 43 to improve the display effect.

[0104] The first doping portion 432 is disposed on the first insulating layer 42 , the drain electrode 44 is disposed on the first doping portion 432 , and the drain electrode 44 overlaps the first doping portion 432 . The second doping portion 433 is disposed on the upper surface of the channel portion 431 , and the data line 20 overlaps the second doping portion 433 .

[0105] In an embodiment of the present application, at least a portion of the orthographic projection of the drain 44 on the substrate 10 is located outside the range of the orthographic projection of the gate 41 on the substrate 10 .

[0106] See also Figure 6 In a direction perpendicular to the plane where the substrate 10 is located, when the orthographic projection of the drain 44 on the substrate 10 is entirely outside the range of the orthographic projection of the gate 41 on the substrate 10, the drain 44 and the gate 41 do not overlap. At this time, the parasitic resistance generated by the drain 44 and the gate 41 is minimal, thereby increasing the on-state current of the thin film transistor 40.

[0107] When the orthographic projection of the drain 44 on the substrate 10 is outside the range of the orthographic projection of the gate 41 on the substrate 10, a portion of the drain 44 overlaps with the gate 41. At this time, the parasitic resistance generated by the drain 44 and the gate 41 is small, which relatively improves the on-state current of the thin film transistor 40.

[0108] In one embodiment of the present application, at least a portion of the orthographic projection of the gate 41 on the substrate 10 is located outside the range of the orthographic projection of the data line 20 on the substrate 10 to reduce the parasitic resistance generated by the gate 41 and the data line 20 and increase the on-state current of the thin film transistor 40.

[0109] In one embodiment of the present application, one data line 20 is electrically connected to a plurality of thin film transistors 40;

[0110] In a direction perpendicular to the plane where the substrate 10 is located, one of the data lines 20 overlaps at least partially with a plurality of the thin film transistors 40 .

[0111] See also Figure 1 and Figure 4 The data lines 20 extending along the column direction overlap at least partially with the plurality of thin film transistors 40 , thereby increasing the aperture ratio of the plurality of pixel areas PA to improve the display effect.

[0112] In an embodiment of the present application, the source of the thin film transistor 40 includes a portion where the data line 20 overlaps with the semiconductor layer 43 .

[0113] See also Figure 3 The semiconductor layer 43 includes a channel portion 431, a first doped portion 432 and a second doped portion 433. A portion of the data line 20 is arranged on the upper surface of the second doped portion 433. In a direction perpendicular to the substrate 10, a portion of the data line 20 arranged on the upper surface of the second doped portion 433 overlaps with the semiconductor layer 43, and this portion of the data line 20 serves as the source of the thin film transistor 40.

[0114] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of data lines are provided on the substrate and extend along a column direction; A plurality of scanning lines are arranged on the substrate and extend along the row direction, wherein the scanning lines and the data lines enclose a plurality of pixel areas arranged in an array; and A plurality of thin film transistors are arranged in an array on the substrate, and the thin film transistors are electrically connected to the data lines; Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the thin film transistor overlaps with the data line.

2. The array substrate according to claim 1, characterized in that: The thin film transistor comprises: A gate, disposed on the substrate and electrically connected to the scan line; A first insulating layer, disposed on the substrate and covering the gate; a semiconductor layer, disposed on the first insulating layer, the semiconductor layer being electrically connected to the data line; and A drain electrode, disposed on the upper surface of the semiconductor layer and electrically connected to the semiconductor layer; Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the semiconductor layer overlaps with the gate, and at least a portion of the semiconductor layer overlaps with the data line.

3. The array substrate according to claim 2, characterized in that: A portion of the data line is disposed on the upper surface of the semiconductor layer, and the data line is disposed in the same layer as the drain electrode.

4. The array substrate according to claim 3, characterized in that: The semiconductor layer comprises: a channel portion, wherein the channel portion is disposed on the first insulating layer; A first doping portion is provided on an upper surface of the channel portion; and A second doping portion is disposed on the upper surface of the channel portion and is spaced apart from the first doping portion; Wherein, the drain electrode is disposed on the upper surface of the first doped portion, and a portion of the data line is disposed on the upper surface of the second doped portion; In a direction perpendicular to a plane where the substrate is located, at least a portion of the channel portion overlaps with the gate, and at least a portion of the channel portion overlaps with the data line.

5. The array substrate according to claim 1, wherein: The thin film transistor comprises: A gate, disposed on the substrate and electrically connected to the scan line; A first insulating layer, disposed on the substrate and covering the gate; A semiconductor layer, disposed on the first insulating layer, wherein the semiconductor layer is electrically connected to the data line; A drain electrode, disposed on the first insulating layer and electrically connected to the semiconductor layer; Wherein, in a direction perpendicular to the plane where the substrate is located, at least a portion of the semiconductor layer overlaps with the gate, and at least a portion of the semiconductor layer overlaps with the data line.

6. The array substrate according to claim 5, characterized in that: A portion of the data line is disposed on the upper surface of the semiconductor layer, and the data line and the drain electrode are disposed in different layers.

7. The array substrate according to claim 6, characterized in that: The semiconductor layer comprises: a channel portion, wherein the channel portion is disposed on the first insulating layer; a first doping portion, disposed on the first insulating layer and connected to the channel portion; and A second doping portion, disposed on an upper surface of the channel portion; Wherein, the drain electrode is disposed on the upper surface of the first doped portion, and a portion of the data line is disposed on the upper surface of the second doped portion; In a direction perpendicular to a plane where the substrate is located, at least a portion of the channel portion overlaps with the gate, and at least a portion of the channel portion overlaps with the data line.

8. The array substrate according to claim 7, characterized in that: At least a portion of an orthographic projection of the drain on the substrate is located outside a range of an orthographic projection of the gate on the substrate.

9. The array substrate according to claim 1, wherein: One of the data lines is electrically connected to a plurality of the thin film transistors; Wherein, in a direction perpendicular to the plane where the substrate is located, one of the data lines overlaps at least partially with a plurality of the thin film transistors.

10. The array substrate according to claim 2, wherein: The source electrode of the thin film transistor includes a portion where the data line overlaps the semiconductor layer.

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