ECM motor with novel gear input circuit

Abstract

The utility model discloses an ECM motor with a novel gear input circuit, comprising a motor and a motor controller, the motor comprises a stator assembly and a rotor assembly, the motor controller comprises a microprocessor MCU and a novel gear input circuit, the novel gear input circuit comprises a plurality of switches, a multipath parallel voltage division circuit and an in-phase summation operational amplifier circuit, the plurality of switches are respectively connected in series with the multi-path parallel voltage division circuits and are used for controlling the connection or disconnection of the voltage division circuits, and the output ends of the multi-path parallel voltage division circuits are gathered to the input pin of the in-phase summation operational amplifier circuit for in-phase summation amplification processing. The output end of the in-phase summation operational amplifier circuit is connected with an IO port with an A / D conversion function of the microprocessor MCU, and the microprocessor MCU reads numbers of the IO port with the A / D conversion function to obtain corresponding gear parameters. The device occupies few IO ports of the microprocessor MCU, so that the chip purchase cost is reduced, and the scheme modularization is facilitated.

Description

Technical Field

[0001] The utility model relates to an ECM motor with a novel gear input circuit. Background Art

[0002] Electronically commutated motors, or ECM motors for short, use electronic switches to change DC to AC to drive motors. They have been widely used in various industries, such as brushless DC motors and permanent magnet synchronous motors. Some ECM motor application areas require multiple gears, such as speed adjustment. There may be multiple gears, such as 500 rpm, 550 rpm...1200 rpm. A gear is set up for every 50 rpm increase. With the increase in customer application scenarios and the increase in inconsistent requirements between different customers, a gear input circuit that can meet the requirements of different customers is needed. Figure 1 This is the circuit diagram of the traditional gear input circuit. By turning the DIP switch, you can select different gear speeds or different motor parameters. You can use one controller to be compatible with the requirements of different customers. And customers can use one controller to adapt to their different products.

[0003] Figure 1 The working principle of the circuit is: by turning the dial switch S1 to control the connection or disconnection of multiple independent circuits to obtain high and low level signals, the IO port of the microprocessor MCU has a signal, and the four ports IO1-IO4 have high and low level states.

[0004] By detecting the level status of IO1-IO4 through the microprocessor MCU, different motor parameters or motor speed or others can be selected.

[0005] Assume that IO1 is at a high level: that is, S1 1-8 is in the off state, and the controller selects parameter variable X1 = 1

[0006] Assume that IO2 is at a high level: that is, S1 2-7 is in the off state, and the controller selects parameter variable X2 = 2

[0007] Assume that IO3 is at a high level: that is, S1 3-6 is in the off state, and the controller selects parameter variable X3 = 4

[0008] Assume that IO4 is at a high level: that is, S1 4-5 is in the off state, and the controller selects parameter variable X4 = 8

[0009] Assume that IO1 is at a low level: that is, S11-8 is in the on state, and the controller selects parameter variable X1 = 0

[0010] Assume that IO2 is at a low level: that is, S1 2-7 is in the on state, and the controller selects parameter variable X2 = 0

[0011] Assume that IO3 is at a low level: that is, S1 3-6 is in the on state, and the controller selects parameter variable X3 = 0

[0012] Assume that IO4 is at a low level: that is, S1 4-5 is in the on state, and the controller selects parameter variable X4 = 0

[0013] X=X1+X2+X3+X4

[0014] From the above analysis, it can be seen that when 4 DIP switches are selected and 4 IO ports of the microprocessor MCU are used, the value range of X is 0-15, a total of 16 states. It is not difficult to deduce that this solution will have 2N states when N DIP switches and N IO ports of the microprocessor MCU are used. Therefore, when this solution is selected, a motor controller can adapt to 2N different requirements.

[0015] It can be analyzed that it has certain shortcomings:

[0016] 1. It occupies too many IO ports of the microprocessor MCU, occupying the microprocessor MCU resources, forcing the designer to choose a microprocessor chip with more IO ports, increasing costs.

[0017] Second: When more states need to be designed, the only option is to increase the number of IO ports of the selected microprocessor MCU, which is not conducive to the modularization of the solution. Summary of the invention

[0018] The utility model aims to provide an ECM motor with a novel gear input circuit, so as to solve the technical problems in the prior art that the gear input circuit of the ECM motor occupies more IO port resources of the microprocessor MCU and cannot be modularized.

[0019] The technical solution of the utility model is achieved in this way:

[0020] An ECM motor with a novel gear input circuit comprises a motor and a motor controller, wherein the motor comprises a stator assembly and a rotor assembly, and the motor controller comprises a microprocessor MCU and a novel gear input circuit, wherein the novel gear input circuit comprises a plurality of switches, a multi-channel parallel voltage divider circuit and a common-phase summing operational amplifier circuit, wherein the plurality of switches are respectively connected in series to the multi-channel parallel voltage divider circuit for controlling the voltage divider circuit to be connected or disconnected, wherein the output end of the multi-channel parallel voltage divider circuit is aggregated to the input pin of the common-phase summing operational amplifier circuit for common-phase summing amplification processing, wherein the output end of the common-phase summing operational amplifier circuit is connected to an IO port with an A / D conversion function of the microprocessor MCU, and the microprocessor MCU reads the digital of the IO port with the A / D conversion function, thereby obtaining the corresponding gear parameter.

[0021] The above-mentioned multiple switches are a dip switch.

[0022] Each of the above-mentioned voltage divider circuits includes a resistor R1 and a resistor R2. The resistors R1 and R2 are connected in series with a switch K, and their two ends are connected to a power supply Vcc and a ground GND respectively. The resistors R1 and R2 are connected as the output end of each voltage divider circuit.

[0023] The above-mentioned multi-channel parallel voltage divider circuit refers to a voltage divider circuit with 3 channels, 4 channels, 5 channels or 6 channels in parallel.

[0024] The above-mentioned gear parameters are gear parameters of rotation speed, or gear parameters of torque.

[0025] The above-mentioned in-phase summing amplifier circuit includes an operational amplifier U1, a resistor R26, a resistor R27, a resistor R25 and a plurality of resistors R20.

[0026] The above-mentioned motor controller also includes an inverter circuit and a rotor position detection circuit.

[0027] Compared with the prior art, the utility model has the following advantages:

[0028] 1. Using only one IO port can achieve better results than the original solution, with more gear states for selection, improving the functionality of the product.

[0029] 2. Only one IO port is used, which reduces the cost of unnecessary selection of a microprocessor MCU with more IO ports.

[0030] 3. Modular design is possible, and this circuit can be used when adding or reducing gear state selections, without the need to use the IO port of the microprocessor MCU.

[0031] 4. Other advantages of the utility model are described in detail in the embodiment section of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a circuit diagram of a gear input circuit of a motor in the prior art;

[0033] Figure 2 A three-dimensional diagram of the ECM motor provided by the utility model;

[0034] Figure 3 An exploded view of the ECM motor provided by the utility model;

[0035] Figure 4 A structural cross-sectional view of the ECM motor provided by the utility model;

[0036] Figure 5A circuit block diagram of a motor controller for an ECM motor provided by the utility model;

[0037] Figure 6 A block diagram of a novel gear input circuit provided by the utility model;

[0038] Figure 7 for Figure 6 The corresponding circuit diagram. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0040] Embodiment 1:

[0041] like Figures 2 to 7 As shown, this embodiment provides an ECM motor with a new gear input circuit, including a motor 1 and a motor controller 2, wherein the motor 1 includes a housing component 11, a stator component 12 and a rotor component 13, and the motor controller 2 includes a microprocessor MCU and a new gear input circuit, characterized in that: the new gear input circuit includes multiple switches, a multi-way parallel voltage divider circuit and a common-phase summing operational amplifier circuit, and the multiple switches are respectively connected in series to the multi-way parallel voltage divider circuit to control each voltage divider circuit to be connected or disconnected, the output end of the multi-way parallel voltage divider circuit is aggregated to the input pin of the common-phase summing operational amplifier circuit to perform common-phase summing amplification processing, and the output end of the common-phase summing operational amplifier circuit is connected to an IO port with an A / D conversion function of the microprocessor MCU, and the microprocessor MCU reads the digital of the IO port with the A / D conversion function to obtain the corresponding gear parameter.

[0042] The above-mentioned multiple switches are a DIP switch with a simple structure and good integration, that is, multiple switches are integrated to form a DIP switch S2.

[0043] Each of the above-mentioned voltage-dividing circuits includes a resistor R5 and a resistor R6. The resistors R5 and R6 are connected in series with a switch, and their two ends are connected to a power supply Vcc and a ground GND respectively. The resistors R5 and R6 are connected as the output end of each voltage-dividing circuit.

[0044] The above-mentioned multi-channel parallel voltage divider circuit refers to a voltage divider circuit with 3 channels, 4 channels, 5 channels or 6 channels in parallel.

[0045] The above-mentioned gear parameters are gear parameters of rotation speed, or gear parameters of torque.

[0046] The above-mentioned in-phase summing operational amplifier circuit includes an operational amplifier U1, a resistor R26, a resistor R27, a resistor R28, a resistor R25 and a plurality of resistors R20.

[0047] The above-mentioned motor controller also includes an inverter circuit and a rotor position detection circuit.

[0048] like Figure 7 As shown, in the solution of the utility model, by connecting multiple switches (i.e., the dial switch S2), a multi-channel parallel voltage divider circuit and a common-phase summing amplifier circuit, it is possible to use only one IO port of the microprocessor MCU (which needs to have an ADC detection function, i.e., an analog-to-digital conversion function), and achieve the same effect as the original solution, and one IO port can theoretically adapt to more than 16 states.

[0049] By designing different voltage division values ​​for the multi-channel parallel voltage division circuit when the four channel switches of the DIP switch S2 are turned on, and then adding the different voltage division values ​​through the in-phase summing operational amplifier circuit, the IO port input end of the microprocessor MCU can obtain 16 different voltage values.

[0050] Assume that the voltage value of channels 1-8 of the DIP switch S2 divided by R1 R8 is V1.

[0051] Assume that the voltage value of channel 2-7 of the DIP switch S2 divided by R2 R7 is V2.

[0052] Assume that the voltage value of channel 3-6 of DIP switch S2 divided by R3 R6 is V3.

[0053] Assume that the voltage value of channel 4-5 of the DIP switch S2 divided by R4 and R5 is V4.

[0054] It can be obtained that when the four channels of the DIP switch S2 are turned on, the voltage values ​​of V1-V4 are as follows:

[0055] V1=VCC*R1 / (R1+R8)

[0056] V2=VCC*R2 / (R2+R7)

[0057] V3=VCC*R3 / (R3+R6)

[0058] V4=VCC*R4 / (R4+R5)

[0059] Assume that the voltage value finally input to the microprocessor MCU is Vmcu.

[0060] Assume that the amplification factors of the four channels of the in-phase summing amplifier circuit are K1-K4.

[0061] The actual amplification factor of the four channels of the in-phase summing amplifier circuit is:

[0062] The following analysis assumes that K1-K4=1 for ease of analysis:

[0063] When the four dials of the dial switch S2 are not turned on, V1-V4=0. Vmcu=V1+V2+V3+V4=0V.

[0064] When channels 1-8 of the DIP switch S2 are turned on and the other channels are not turned on, Vmcu=V1+0+0+0=V1.

[0065] The remaining states can be obtained as above:

[0066] The dip switch S2 only conducts 2-7, Vmcu = V2.

[0067] The dip switch S2 only conducts 3-6, Vmcu = V3.

[0068] The dip switch S2 only conducts 4-5, Vmcu=V4.

[0069] When the DIP switch S2 is turned on, Vmcu has the following six states:

[0070] V1+V2

[0071] V1+V3

[0072] V1+V4

[0073] V2+V3

[0074] V2+V4

[0075] V3+V4

[0076] When the DIP switch S2 is turned on, Vmcu has the following states:

[0077] V1+V2+V3

[0078] V1+V2+V4

[0079] V1+V3+V4

[0080] V2+V3+V4

[0081] When the DIP switch S2 is turned on, Vmcu is in one of the following states:

[0082] V1+V2+V3+V4

[0083] From the above analysis, it can be seen that the DIP switch S2 of this solution can be designed to provide 16 voltage values ​​to the MCU when using 4 switches. In order to ensure that the 16 voltages are not repeated and the voltage differences between them are close, the voltage difference between each state is VCC / 15.

[0084] The advantages of this solution are;

[0085] (1) Using only one IO port of the microprocessor MCU can achieve better results than the original solution, with more states available for selection, thus improving the functionality of the product.

[0086] (2) Only one IO port of the microprocessor MCU is used, which reduces the cost of unnecessary selection of a microprocessor MCU with more IO ports.

[0087] (3) The circuit can be designed in a modular way. This circuit can be used when adding or reducing state selections, without the need to use the IO port of the microprocessor MCU.

[0088] For example, when the multi-way parallel voltage divider circuit is a 5-way voltage divider circuit, the dip switch S2 uses 5 switches to obtain more than 32 states that are input to an IO port of the microprocessor MCU.

[0089] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited thereto. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention are equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. An ECM motor with a new gear input circuit, comprising a motor and a motor controller, wherein the motor comprises a stator assembly and a rotor assembly, and the motor controller comprises a microprocessor MCU and a new gear input circuit, characterized in that The novel gear input circuit includes multiple switches, a multi-channel parallel voltage divider circuit and a common-phase summing operational amplifier circuit. The multiple switches are respectively connected in series to the multi-channel parallel voltage divider circuit to control the voltage divider circuit to be connected or disconnected. The output ends of the multi-channel parallel voltage divider circuit are summarized to the input pins of the common-phase summing operational amplifier circuit for common-phase summing amplification processing. The output end of the common-phase summing operational amplifier circuit is connected to an IO port with A / D conversion function of the microprocessor MCU. The microprocessor MCU reads the digital of the IO port with A / D conversion function to obtain the corresponding gear parameter.

2. The ECM motor with a novel gear input circuit according to claim 1, characterized in that: Multiple switches are a dip switch.

3. An ECM motor with a novel gear input circuit according to claim 1 or 2, characterized in that: Each voltage divider circuit includes a resistor R5 and a resistor R6. The resistors R5 and R6 are connected in series with a switch, and their two ends are connected to a power supply Vcc and a ground GND respectively. The resistors R5 and R6 are connected as the output end of each voltage divider circuit.

4. The ECM motor with a novel gear input circuit according to claim 3 is characterized in that: A multi-channel parallel voltage divider circuit refers to a voltage divider circuit with 3, 4, 5 or 6 channels in parallel.

5. The ECM motor with a novel gear input circuit according to claim 4, characterized in that: The gear parameter is a gear parameter of rotational speed, or a gear parameter of torque.

6. The ECM motor with a novel gear input circuit according to claim 5, characterized in that: The in-phase summing operational amplifier circuit includes an operational amplifier U1, a resistor R26, a resistor R27, a resistor R28, a resistor R25 and a plurality of resistors R20.

7. The ECM motor with a novel gear input circuit according to claim 5, characterized in that: The motor controller also includes an inverter circuit and a rotor position detection circuit.

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