Charging and discharging circuit, display screen and electronic equipment

Abstract

The utility model discloses a charging and discharging circuit, a display screen and electronic equipment, and belongs to the technical field of display. The charging and discharging circuit comprises at least one load capacitor, at least one preprocessing circuit, a current mirror circuit, a compensation circuit and at least one switching circuit. Each preprocessing circuit is correspondingly connected with a load capacitor, the preprocessing circuit can adjust the voltage of the corresponding load capacitor to a reference voltage, the current mirroring circuit can mirror a reference current source and output the reference current source through at least one branch, and each output branch is connected between the preprocessing circuit and the load capacitor through a switching circuit. The compensation circuit can compensate the charging or discharging time of the load capacitor, and the switching circuit can control the charging or discharging time of the load capacitor. According to the array substrate, all column load capacitors can be charged or discharged in a short time, meanwhile, charging and discharging are compensated, the difference between different pixel columns can be compensated, and the image display quality is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, in particular to a charging and discharging circuit, a display screen having the charging and discharging circuit, and an electronic device having the display screen. Background Art

[0002] At present, display screens are increasingly used as human-computer interaction interfaces, and their application fields include but are not limited to smartphones, tablet computers, laptops, televisions, desktop monitors, etc. In a display screen, each pixel unit corresponds to a pixel circuit, and the pixel circuit is configured at the intersection of the scan lines arranged in the row direction to supply control signals and the data lines arranged in the column direction to supply data signals, so as to drive the corresponding pixel unit to display images. During the image display process, the capacitor in the pixel circuit needs to be charged so that the capacitor can control the light-emitting element to emit light during the light-emitting stage.

[0003] With the continuous development of display technology, the resolution and refresh rate of display screens are also constantly improving. For example, some display screens have a resolution of 4K and a refresh rate of 120Hz, etc. However, with the continuous improvement of the resolution and refresh rate of display screens, the number of pixel units has increased dramatically. Some display screens need to charge the capacitors of the pixel circuits corresponding to all pixel units in a time as short as a few microseconds. How to charge the capacitors in all pixel circuits in a short time so that the voltage of the capacitors meets the actual use requirements is an urgent problem to be solved.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a charging and discharging circuit, which can charge or discharge the capacitors in all column pixel circuits in a short time, so that the voltage of the capacitors meets the actual use requirements.

[0006] Another object of the present invention is to provide a display screen and an electronic device, which can charge or discharge the capacitors in all column pixel circuits in a short time so that the voltage of the capacitors meets the actual use requirements.

[0007] To achieve the above object, an embodiment of the present invention provides a charge and discharge circuit, comprising:

[0008] at least one load capacitor;

[0009] at least one preprocessing circuit, each of the preprocessing circuits corresponds to one of the load capacitors, the preprocessing circuit is connected to the corresponding load capacitor to form a connection point, and the preprocessing circuit is used to adjust the voltage of the corresponding load capacitor to a reference voltage value;

[0010] A current mirror circuit, the current mirror circuit is used to mirror a reference current source and output it through at least one output branch, each of the output branches corresponds to one of the connection points;

[0011] At least one switch circuit, each of the switch circuits corresponds to an output branch, each of the output branches is connected to the corresponding connection point through the corresponding switch circuit, and the switch circuit is used to control the charging or discharging time of the load capacitor.

[0012] In one or more embodiments of the present invention, each of the pre-processing circuits is controlled by a same control signal to adjust the voltage of the corresponding load capacitor to a reference voltage value.

[0013] In one or more embodiments of the present invention, each switch circuit is controlled to be turned on or off by a different control signal.

[0014] In one or more embodiments of the present invention, the preprocessing circuit includes

[0015] Reference voltage source;

[0016] The first MOS tube has a source terminal connected to a reference voltage source, a drain terminal connected to the load capacitor to form the connection point, and a gate terminal connected to a control signal.

[0017] In one or more embodiments of the present invention, the current mirror circuit includes

[0018] The second MOS tube has a drain terminal connected to a reference current source, a source terminal connected to a voltage source or ground, and a gate terminal connected to a drain terminal;

[0019] At least one third MOS tube, the drain terminal of each third MOS tube is used as an output branch, the source terminal is commonly connected to a voltage source or ground, and the gate terminal is connected to the gate terminal of the second MOS tube.

[0020] In one or more embodiments of the present invention, the second MOS tube and the third MOS tube are PMOS tubes or NMOS tubes.

[0021] In one or more embodiments of the present invention, the switch circuit includes

[0022] The fourth MOS tube has a source terminal connected to the output branch, a drain terminal connected to the connection point, and a gate terminal connected to the control signal.

[0023] In one or more embodiments of the present invention, the compensation circuit includes

[0024] Detection resistor;

[0025] A plurality of calibration circuits, each calibration circuit corresponds to a pixel column, and each calibration circuit is connected to a voltage source or ground through a detection resistor to form a detection point, and each calibration circuit is used to receive pixel data and convert the corresponding pixel data into a reference current and a calibration current and input them into the detection resistor;

[0026] At least one detection circuit is used to obtain a reference voltage and a calibration voltage at a detection point according to a reference current and a calibration current, respectively, and adjust pixel data according to the reference voltage and the calibration voltage.

[0027] In one or more embodiments of the present invention, all pixel columns share a detection circuit.

[0028] In one or more embodiments of the present invention, the calibration circuit includes

[0029] A fifth MOS tube, connected in series with the detection resistor between the voltage source and the ground;

[0030] A first switch, one end of which is connected to a reference voltage, and an opposite end of which is connected to a gate terminal of a fifth MOS tube;

[0031] A second switch, one end of which is connected to the data voltage of the pixel column, and the opposite end of which is connected to the gate end of the fifth MOS tube;

[0032] A third switch, one end of which is connected to a voltage source, and an opposite end of which is connected to a gate terminal of a fifth MOS tube;

[0033] The switch control circuit is connected to the first switch, the second switch and the third switch, and is used to control the first switch, the second switch and the third switch to be closed or opened according to the pixel data.

[0034] In one or more embodiments of the present invention, the switch control circuit is a logic circuit composed of gate-level circuits, with inputs of calibration_mode0, calibration_mode1 and data[M], and outputs of Q1, Q2, and Q3, wherein Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch, wherein calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

[0035] In one or more embodiments of the present invention, the switch circuit controls the charging or discharging time of the load capacitor including:

[0036] During charging or discharging, the M-bit counter increases from 0 to 2. M -1 counts the charging or discharging time, and when the counter counts from zero to the grayscale value corresponding to a column of pixels, the switch circuit corresponding to the column of pixels is disconnected, M is the color depth of the display, and M is an integer greater than 0.

[0037] In one or more embodiments of the present invention, the current of each output branch is the same as or proportional to a reference current source.

[0038] An embodiment of the present invention provides a display screen, comprising the above-mentioned charging and discharging circuit.

[0039] An embodiment of the present invention provides an electronic device, including the display screen mentioned above.

[0040] Compared with the prior art, the present invention can quickly charge or discharge the capacitors of all pixel circuits in each column, so that the voltage value of the capacitor meets the actual use requirements, and the capacitors of the pixel circuits in each column are independently controlled by constant current during charging or discharging, which can avoid interference between columns. At the same time, by compensating for charging and discharging, the differences between different pixel columns can be compensated, thereby improving the image display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of a charging and discharging circuit structure according to an embodiment of the present invention;

[0042] Figure 2 is a circuit diagram of a charge and discharge circuit according to an embodiment of the present invention;

[0043] Figure 3 is a circuit diagram of a charge and discharge circuit according to another embodiment of the present invention;

[0044] Figure 4 is a circuit diagram of a charge and discharge time control circuit according to an embodiment of the present invention;

[0045] Figure 5 is a schematic diagram of the structure of a compensation circuit according to an embodiment of the present invention;

[0046] Figure 6 is a circuit diagram of a compensation circuit according to an embodiment of the present invention;

[0047] Figure 7 is a compensation circuit diagram according to another embodiment of the present invention;

[0048] Figure 8 is a schematic diagram of a ramp voltage according to an embodiment of the present invention;

[0049] Fig. 9is a schematic diagram of a ramp voltage according to another embodiment of the present invention. DETAILED DESCRIPTION

[0050] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0051] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0052] like Figures 1 to 4 As shown, a charging and discharging circuit according to a preferred embodiment of the present invention can quickly charge or discharge the capacitors of all pixel circuits in each column so that the voltage of the capacitors meets the actual use requirements, and the capacitors of the pixel circuits in each column are independent of each other and do not interfere with each other during charging or discharging.

[0053] Specifically, combined Figure 1 to Figure 7 As shown, the charge and discharge circuit includes at least one load capacitor, at least one pre-processing circuit 10, a current mirror circuit 20, a compensation circuit, and at least one switch circuit 30. The load capacitor is used to store charge, and the load capacitor here is the equivalent load capacitor of all pixel circuits in each column, so the number of load capacitors can be determined according to the number of columns.

[0054] The preprocessing circuit 10 corresponds to the load capacitor one by one, that is, each preprocessing circuit 10 corresponds to a load capacitor, and the preprocessing circuit 10 is connected to the corresponding load capacitor to form a connection point A. The preprocessing circuit 10 can adjust the voltage value of the load capacitor to a preset value, such as by charging the load capacitor to adjust the voltage value of the load capacitor to a preset value, or by discharging the load capacitor to adjust the voltage value of the load capacitor to a preset value, which can be selected according to actual needs.

[0055] The current mirror circuit 20 is used to mirror the reference current source and output it through at least one output branch to provide a current proportional to the reference current source. The output branch here corresponds to the connection point A one-to-one, or the output branch corresponds to the load capacitor one-to-one. At the same time, the proportionality here includes but is not limited to 1:1, which can be adjusted according to actual needs.

[0056] The compensation circuit is used to compensate for the charging or discharging time of the capacitor of each pixel column to compensate for the difference between different pixel columns and improve the display effect.

[0057] The switch circuit 30 corresponds to the output branch one by one, and each output branch is connected to the corresponding connection point A through the corresponding switch circuit 30, that is, the switch circuit 30 is connected between the connection point A and the output branch, and the switch circuit 30 can control the charging or discharging time of the load capacitor so that the voltage value of the load capacitor reaches the actual required voltage value. The charging or discharging time here refers to the time it takes for the load capacitor to reach the actual required voltage value from the current voltage value.

[0058] In a specific implementation, the preprocessing circuit 10 first charges or discharges the corresponding load capacitor to make its voltage value reach a preset value, and the switch circuit 30 is in a disconnected state during the process of the preprocessing circuit 10 charging or discharging the load capacitor.

[0059] When the voltage value of the load capacitor reaches the preset value, the current mirror circuit 20 starts to work, mirroring the reference current source and outputting a current proportional to the reference current source through the output branch. At the same time, the switch circuit 30 is in a closed state. At this time, due to the existence of the current in the output branch, the voltage value of the load capacitor continuously decreases or increases from the preset value, that is, the load capacitor is discharged or charged.

[0060] When the charge or discharge time of the load capacitor is reached, the switch circuit 30 is in the disconnected state, and there is no current in the loop, so the voltage of the load capacitor no longer drops or rises. At this time, the voltage value of the load capacitor is the required voltage value.

[0061] Combination Figure 2 and Figure 3 As shown, the preprocessing circuit 10 includes a reference voltage source and a first MOS transistor. The gate terminal of the first MOS transistor is connected to the control signal, the source terminal is connected to the reference voltage source, and the drain terminal is connected to the corresponding load capacitor to form a connection point A. In a specific implementation, the control signal controls the first MOS transistor to be turned on, and the reference voltage source is electrically connected to the load capacitor, so that the voltage value of the load capacitor can be adjusted to the same voltage value as the reference voltage source by charging or discharging.

[0062] In this embodiment, all pre-processing circuits 10 are controlled by the same control signal, so that the pre-processing circuit 10 adjusts the voltage value of the corresponding load capacitor to a preset value, such as Figure 2 As shown, the gate terminals of all first MOS transistors are controlled by the control signal S0. Of course, in other embodiments, they can also be controlled individually, which can be selected according to actual needs.

[0063] Combination Figure 2 and Figure 3As shown, the current mirror circuit 20 includes a second MOS tube and at least one third MOS tube. The drain terminal of the second MOS tube is connected to the reference current source, the source terminal is connected to the voltage source or the ground, and the gate terminal is connected to the drain terminal. The drain terminal of each third MOS tube serves as an output branch of the output current, the source terminal is commonly connected to the voltage source or the ground, and the gate terminal is connected to the gate terminal of the second MOS tube. The second MOS tube can form a basic current mirror with a third MOS tube to mirror the reference current source to the corresponding output branch.

[0064] In this embodiment, the second MOS tube and the third MOS tube are selected from PMOS tubes or NMOS tubes, and can be selected according to actual needs.

[0065] Combination Figure 2 and Figure 3 As shown, the switch circuit 30 includes a fourth MOS tube, which is selected from a PMOS tube or an NMOS tube. Among them, the source end of the fourth MOS tube is connected to the corresponding output branch, the drain end is connected to the corresponding connection point A, and the gate end is connected to the control signal. In a specific implementation, the control signal controls the fourth MOS tube to be turned on, and then the output branch and the corresponding load capacitor can form a loop, so that a current is generated in the loop, and then the voltage value of the load capacitor changes with the passage of time.

[0066] In this embodiment, each switch circuit 30 is controlled by a different control signal, that is, each switch circuit 30 is controlled by a corresponding control signal. Figure 2 and Figure 3 As shown, each fourth MOS transistor is controlled by a different control signal. By controlling the switch circuit 30 by a different control signal, the charging or discharging time of each load capacitor can be controlled individually.

[0067] Combined with 5~ Figure 7 As shown, the compensation circuit includes a detection resistor, a plurality of calibration circuits, and at least one detection circuit. Each calibration circuit is connected to a voltage source or ground (GND) through a detection resistor to form a detection point. Each calibration circuit is used to receive Pixel Data The corresponding pixel data is converted into reference current and calibration current and input into the detection resistor; the detection circuit is used to obtain the reference data voltage and calibration data voltage of the detection point according to the reference current and calibration current, and adjust the pixel data according to the two. The pixel data here is gray value data. For example, for a display with a color depth of 10, the calibration circuit receives pixel data such as 10'h200 and so on.

[0068] In a specific implementation, first, the compensation circuit receives a whole row of pixel data, wherein the highest bit of the pixel data of the first pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0, and the detection circuit obtains the reference voltage Ref_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor; thereafter, a whole row of pixel data is sent again, wherein the highest bit of the pixel data of the second pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0, and the detection circuit obtains the reference voltage Ref_Vdata generated by the calibration circuit of the second pixel column through the detection resistor; the above process is repeated to obtain the reference voltage Ref_Vdata corresponding to all pixel columns.

[0069] Finally, the compensation circuit receives a whole row of pixel data, where the pixel data of the first column is 10'h300, and the data of other columns are all 10'h000. The detection circuit obtains the calibration voltage Cal_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor, and at the same time, compares the calibration voltage Cal_Vdata with the obtained reference voltage Ref_Vdata. If the calibration voltage Cal_Vdata is greater than the reference voltage Ref_Vdata, the pixel data of the first column is subtracted by one. If the calibration voltage Cal_Vdata is less than the reference voltage Ref_Vdata, the pixel data of the first column is added by one. Repeat the above process until the calibration voltage Cal_Vdata is the same as the reference voltage Ref_Vdata. At this time, the received pixel data of the first column is the number of clock cycles required for the first pixel column to reach the reference voltage.

[0070] The above process is repeated to obtain the number of clock cycles required for each pixel column to reach the reference voltage.

[0071] After the number of clock cycles is obtained, it can be used to obtain the time required for each pixel column to reach the reference voltage, that is, the product of the number of clocks and the length of the clock cycle is the time.

[0072] In this embodiment, all pixel columns share one detection circuit. Of course, in other embodiments, a corresponding detection circuit may be separately provided for each pixel column, and the configuration may be performed according to actual needs.

[0073] Combination Figure 6 and Figure 7 As shown, the calibration circuit includes a fifth MOS transistor T, a first switch K1, a second switch K2 and a third switch K3. The fifth MOS transistor T and the detection resistor R are connected in series to the voltage source V H and ground (GND), one end of the first switch K1 is connected to the calibration voltage Vcal, the opposite end is connected to the gate end of the fifth MOS transistor T, and one end of the second switch K2 is connected to the data signal Vdata , the opposite end is connected to the gate end of the fifth MOS tube T, and one end of the third switch K3 is connected to the reference voltage source V H , the gate terminal of the fifth MOS tube T at the opposite end.

[0074] In the specific implementation, when performing the first step of calibration, the first switch K1 is closed, the second switch K2 circuit and the third switch K3 are opened, so that the reference voltage V cal can be input into the calibration circuit; when performing the second step of calibration, the first switch K1 and the third switch K3 are opened, and the second switch K2 is closed, so that the data voltage Vdata can be input into the calibration circuit.

[0075] In this embodiment, the first switch K1, the second switch K2 and the third switch K3 can be controlled to be turned on or off by the switch control circuit (Control) shown in the figure. The switch control circuit here is a simple logic circuit composed of gate-level circuits, whose inputs are calibration_mode0, calibration_mode1 and data[M], and whose outputs are Q1, Q2, Q3, which can respectively control the closing or opening of the first switch K1, the second switch K2 and the third switch K3. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit of the grayscale value of the pixel column (M is the color depth of the grayscale).

[0076]

[0077] Furthermore, the following takes the case where the color depth is 10 and the first pixel column is compensated as an example to explain in detail how the compensation circuit performs compensation.

[0078] First, calibration_mode0 and calibration_mode1 are configured to 1 and 0 respectively. After that, a whole row of pixel data is received, where the pixel data of the first column is 10'h200 (the highest bit needs to be 1), and the pixel data of other columns are 10'h000. Under the control of the switch control circuit (Control), the first switch K1 corresponding to the first pixel column is closed, the second switch K2 and the third switch K3 are opened, and the gate terminal of the fifth MOS tube T is connected to the reference voltage V cal , at this time the reference voltage V calA current I1 will be generated from the source terminal S to the drain terminal D of the fifth MOS tube T, and the current I1 will flow through the resistor R. Since the data [M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are opened, and the fifth MOS tube T does not generate current, so only the current I1 flows through the detection resistor R. At this time, the voltage detected by the detection circuit at the detection point P represents the reference voltage V cal The converted data is Ref_Vdata corresponding to the 1st pixel column.

[0079] Secondly, calibration_mode0 and calibration_mode1 are configured to 0 and 1 respectively. After that, a whole row of pixel data is received, wherein the pixel data of the first column is 10'h300, and the pixel data of other columns is 10'h000. Under the control of the switch control circuit (Control), the second switch K2 is closed, the first switch K1 and the third switch K3 are opened, and the gate terminal of the fifth MOS transistor T is connected to the data voltage Vdata, and the voltage of the data voltage Vdata depends on the pixel data input by the first pixel column. At this time, the data voltage Vdata will generate a current I1' from the source terminal S to the drain terminal D of the fifth MOS transistor T, and the current I1' will flow through the detection resistor R. Since the data [M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are opened, and the fifth MOS transistor T does not generate current, so the detection resistor R only flows through the current I1'. At this time, the detection circuit detects that the voltage at the detection point P represents the data voltage Vdata of the first pixel column, and the converted data is the Cal_Vdata corresponding to the first pixel column.

[0080] Finally, it is determined whether the voltage Cal_Vdata is the same as Ref_Vdata, and the pixel data is adjusted according to the determination result. That is, if the voltage Cal_Vdata is greater than Ref_Vdata, the pixel data input to the first pixel column is reduced by one, and if the voltage Cal_Vdata is less than Ref_Vdata, the pixel data input to the first pixel column is increased by one.

[0081] Repeat the above process until the voltage Cal_Vdata is the same as Ref_Vdata. At this time, the pixel data (i.e., grayscale value data) of the first pixel column is the number of clock cycles required for the first pixel column to reach the reference voltage, which can be used to obtain the time required for each pixel column to reach the reference voltage.

[0082] In this embodiment, an M-bit counter is used to count from 0 to 2 M -1 is used to count the charging or discharging time, and M is an integer greater than 0. Figure 4As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels (the grayscale value is the value that has been compensated by the above-mentioned pixel compensation circuit), the fourth MOS tube in the switch circuit corresponding to the column of pixels is controlled to be disconnected by the corresponding control signal. At this time, the loop is disconnected, and no current flows, thereby stopping the discharge of the load capacitor, and the voltage of the load capacitor is fixed.

[0083] The following takes two embodiments as examples to describe the charge and discharge circuit of the present invention in detail.

[0084] Embodiment 1

[0085] like Figure 2 As shown, the charge and discharge circuit includes n pre-processing circuits 10, n switch circuits 30, and the current mirror circuit 20 has n output branches. Among them, the first MOS transistor of the pre-processing circuit 10 is a PMOS transistor, the second MOS transistor and the third MOS transistor in the current mirror circuit 20 are both NMOS transistors, and the fourth MOS transistor in the switch circuit 30 is an NMOS transistor. Among them, the source terminal of each first MOS transistor (denoted as T11~Tn1) is connected to the reference voltage source V H , the drain end is connected to the corresponding load capacitor (denoted as C1~Cn) and forms a connection point A, the gate end is connected to the control signal S0; the drain end of the second MOS tube (denoted as T0) is connected to the reference current source I bias , the source terminal is grounded, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS tube (denoted as T13~Tn3) is used as an output branch, the source terminal is grounded, and the gate terminal is connected to the gate terminal of the second MOS tube; the source terminal of each fourth MOS tube (denoted as T12~Tn2) is connected to the drain terminal of the corresponding third MOS tube, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signal.

[0086] In a specific implementation, after a row of time starts, the control signal S0 controls all the first MOS transistors (T11-Tn1) to be turned on, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to be turned off, such as the control signal S1 controls the fourth MOS transistor T1 to be turned off. At this time, the voltage values ​​of all load capacitors (C1-Cn) are increased to the high voltage reference voltage value V H .

[0087] Furthermore, the control signal S0 controls all the first MOS transistors to turn off, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to turn on, and the charge-discharge circuit starts to discharge. At this time, the current mirror circuit 20 can mirror a current I in each output branch, and the current I is equal to the reference current source I bias In specific implementation, the width-to-length ratio of the second MOS tube to the third MOS tube can be adjusted to control the current I and the current I biasThe proportional relationship can be used to select the appropriate current according to actual needs.

[0088] The discharge time of the load capacitor can be further controlled by counting, such as using an M-bit counter from 0 to 2 M -1 is used to count the discharge time, and M is an integer greater than 0. Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels (the grayscale value is the value that has been compensated by the above-mentioned pixel compensation circuit), the fourth MOS tube in the switch circuit corresponding to the pixel in the column is controlled to be disconnected by the corresponding control signal. At this time, the loop is disconnected, and no current flows, and the discharge of the load capacitor stops, and the voltage of the load capacitor is fixed. The voltage at this time is the voltage corresponding to the grayscale value of the pixel in this column, and this voltage will be stored by the load capacitor. When the load capacitors of all columns are discharged, they will be written into the pixel driving circuit of a certain row together.

[0089] Embodiment 2

[0090] like Figure 3 As shown, different from the first embodiment, the first MOS transistor of the preprocessing circuit 10 is an NMOS transistor, the second MOS transistor and the third MOS transistor in the current mirror circuit 20 are both PMOS transistors, and the fourth MOS transistor in the switch circuit 30 is a PMOS transistor. The source terminal of each first MOS transistor is connected to the reference voltage source V L , the drain end is connected to the load capacitor and forms a connection point A, the gate end is connected to the control signal S0; the drain end of the second MOS tube is connected to the reference current source I bias , the source terminal is connected to the voltage VDD, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS tube serves as an output branch, the source terminal is connected to the voltage VDD, and the gate terminal is connected to the gate terminal of the second MOS tube; the source terminal of each fourth MOS tube is connected to the drain terminal of the third MOS tube, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signal.

[0091] In the specific implementation, after the start of a row, the control signal S0 controls all the first MOS transistors to be turned on, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to be turned off. At this time, the voltage values ​​of all load capacitors are adjusted to the low voltage reference voltage value V L .

[0092] Furthermore, the control signal S0 controls all the first MOS transistors to turn off, and at the same time, the control signal Sn controls the corresponding fourth MOS transistor Tn to turn on, and the charge-discharge circuit starts charging. At this time, the current mirror circuit 20 can mirror a current in each output branch, and the current is proportional to the reference current source.

[0093] The charging time of the load capacitor can be further controlled by counting, such as using an M-bit counter from 0 to 2 M -1 is used to count the charging time, and M is an integer greater than 0. Figure 4 As shown, when the counter counts from 0 to the grayscale value corresponding to a certain column of pixels (the grayscale value is the value that has been compensated by the above-mentioned pixel compensation circuit), the fourth MOS tube in the switch circuit corresponding to the column is controlled to be disconnected by the corresponding control signal. At this time, the loop is disconnected, and no current flows, thereby stopping the charging of the load capacitor, and the voltage of the load capacitor is fixed. The voltage at this time is the voltage corresponding to the grayscale value of the pixels in this column, and this voltage will be stored by the load capacitor. When the load capacitors of all columns are charged, they will be written into the pixel driving circuit of a certain row together.

[0094] In this embodiment, the compensation circuit can realize the compensation for charging and discharging through the above-mentioned specific circuit. Of course, in other embodiments, the compensation circuit can also compensate for the charging and discharging time in the following manner.

[0095] Specifically, first, a calibration voltage is selected from the ramp voltage;

[0096] Secondly, each pixel column is discharged from the maximum value of the ramp voltage, or each pixel column is charged from the minimum value of the ramp voltage, and the pixel column with the slowest discharge or charge is determined;

[0097] Thirdly, calibrate the pixel column with the slowest discharge or charge, and determine the time offset values ​​corresponding to the remaining pixel columns based on the pixel column with the slowest discharge or charge;

[0098] Finally, the discharge or charge time of each pixel column minus the corresponding time offset value is the actual charge or discharge time.

[0099] The following describes in detail how to perform compensation using the discharge and charge processes respectively.

[0100] (1) Discharge process

[0101] like Figure 8 As shown in the figure, it is a schematic diagram of the ramp voltage, which can be expressed by the following formula:

[0102] V out =V H -(I L / C L )*t,

[0103] Where t is T*P W , T is the number of clock cycles, ranging from 0 to 2 M -1,P W is the cycle time length; C L is the load capacitance; IL is the pixel column discharge current; V out is the display pixel data voltage.

[0104] In a specific implementation, the pre-processing circuit 10 first adjusts each load capacitor to a preset value, that is, to a voltage V H In order to realize the compensation of the discharge process, the present invention firstly increases the voltage V H and V L Select a reference voltage V cal Here the reference voltage V cal It can be selected by the following method: Set the voltage V L To V H The voltage between the two M , corresponding to the pixel gray value 2 M -1 to 0, where V H The corresponding pixel minimum gray value is 0, V L The maximum gray value of the corresponding pixel is 2 M -1.

[0105] In this embodiment, in order to achieve better calibration accuracy, reuse the latch circuit, and ensure that the maximum difference of all pixel columns can be covered, the reference voltage V cal It is preferred to choose a voltage close to V L point.

[0106] Furthermore, when the reference voltage V cal After that, all pixel columns are discharged, and the discharge time is (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles. When the discharge time is over, the pixel column with the slowest discharge is determined. In specific implementation, the pixel column with the slowest discharge can be determined by a detection circuit, such as the detection circuit determining whether the pixel column is discharged to the reference voltage V cal , to determine whether it is the slowest discharging pixel column, and so on.

[0107] After the pixel column with the slowest discharge is determined, the reference current source I bias , by changing the reference current source I bias To change the current mirrored by the current mirror circuit 20 in the pixel column, and at the same time, discharge the pixel column, the discharge time is (2 M -1)*(V H -V cal ) / (V H -V L) clock cycles. At the same time, the data voltage V data Is it consistent with the reference voltage V cal If the data voltage V data With reference voltage V cal If the same, the calibration is completed, the current reference current source I bias is the reference current source after calibration. At this time, the current reference current source I bias Configuration parameters are stored to facilitate subsequent use of the reference current source I bias Calibrate other pixel columns. If the data voltage V data With reference voltage V cal If they are not the same, the reference current source I of the current mirror circuit 20 is adjusted continuously. bias , until it is discharged (2 M -1)*(V H -V cal ) / (V H -V L ) clock cycles, the data voltage V data With reference voltage V cal same.

[0108] Furthermore, after the pixel column with the slowest discharge time is calibrated, the time offset values ​​corresponding to the remaining pixel columns are determined based on the discharge time of the pixel column with the slowest discharge time. In specific implementation, the time offset values ​​corresponding to the remaining pixel columns can be obtained by the following method:

[0109] From the above, we can know and combine Figure 8 As shown, the pixel column with the slowest discharge voltage is V H Discharge to V cal The time taken T' max *P w , then the pixel column changes from voltage V H Discharge to V L The time taken is T max *P w =T' max *P w *(2 M -1) / G cal , which can be achieved through Figure 8 The similar triangle relationship shown in the figure is deduced, where G cal is the voltage V cal The corresponding pixel grayscale value.

[0110] Among the remaining pixel columns, the first pixel column is from the voltage V H Discharge to V cal The time used is T'1*P w , then the first pixel column is from the voltage VH Discharge to V L The time taken is T1*P w =T'1*P w *(2 M -1) / G cal .

[0111] By (T max *P w -T1*P w ) / P w , the clock cycle offset value Offset corresponding to the first pixel column is obtained as:

[0112] △T1=(T' max -T'1)*(2 M -1) / G cal ;

[0113] Furthermore, the second pixel column corresponds to Clock cycle offset value Offset is:

[0114] △T2=(T' max -T'2)*(2 M -1) / G cal ;

[0115] By analogy, any pixel column k in other pixel columns corresponds to Clock cycle offset value Offset values ​​are:

[0116] △T k =(T' max -T' k )*(2 M -1) / G cal .

[0117] Since the gray value G of a pixel on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k , where G k is the grayscale value of a pixel on any pixel column k, t k0 is a pixel G on any pixel column k k The corresponding discharge time.

[0118] Therefore, the clock cycle offset value Offset corresponding to any pixel point on any pixel column k is:

[0119] △T k0 / △T k =t k0 / t k =Gk / (2 M -1).

[0120] If the external input display signal grayscale of the k-th pixel column is G k When , the corresponding discharge time clock cycle number (Clock Cycle) is

[0121] G k / (2 M -1)*(T' max *(2 M -1) / G cal -△T k ).

[0122] After the clock cycle number offset value Offset corresponding to any pixel point on any pixel column k is determined, the clock cycle length Pw may be further used to determine the time offset value corresponding to any pixel point on any pixel column k.

[0123] In specific implementation, the clock cycle number offset value Offset of the slowest discharging pixel column is usually set to 0, and the offset values ​​Offset corresponding to the remaining pixel columns can be stored in a corresponding storage medium for subsequent use.

[0124] In this embodiment, the gray value G of a pixel point on any pixel column k is k and the maximum gray value is G k / (2 M -1)=t k0 / t k It can be obtained by combining Figure 8 As shown, for any pixel point on pixel column k, the corresponding gray value formula G k =(2 M -1)*(I k / C k )*t k0 / (V H -V L ). For any pixel column k, (I k / C k ) is a constant, (2 M -1) and (V H -V L ) is a constant value, G k and t k0 is proportional to the grayscale value G corresponding to any two pixels on the pixel column. k1 and G k2 , all have G k1 / G k2 =t k1 / t k2 ; Therefore, the pixel point G on any pixel column kk and the maximum gray value is G k / (2 M -1)=t k0 / t k Among them, I k is the actual charging current of any pixel column k, C k is the actual load capacitance of any pixel column k.

[0125] (2) Charging process

[0126] like Fig. 9 As shown in the figure, it is a schematic diagram of the ramp voltage, which can be expressed by the following formula:

[0127] V out =V L +(I L / C L )*t,

[0128] Where t is T*P W , T is the number of clock cycles, ranging from 0 to 2 M -1,P W is the cycle time length; C L is the load capacitance; I L is the pixel column discharge current; V out is the display pixel data voltage.

[0129] In a specific implementation, the pre-processing circuit 10 first adjusts each load capacitor to a preset value, that is, to a voltage V L In order to realize the compensation of the charging process, the present invention firstly H and V L Select a reference voltage V cal Here the reference voltage V cal It can be selected by the following method: Set the voltage V L To V H The voltage between the two M , corresponding to the pixel gray value 2 M -1 to 0, where V L The corresponding pixel minimum gray value is 0, V H The maximum gray value of the corresponding pixel is 2 M -1.

[0130] In this embodiment, in order to achieve better calibration accuracy, reuse the latch circuit, and ensure that the maximum difference of all pixel columns can be covered, the reference voltage V cal It is preferred to choose a voltage close to V H point.

[0131] Furthermore, when the reference voltage Vcal After that, all pixel columns are charged, and the charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles. When the charging time is over, the pixel column with the slowest charging is determined. In specific implementation, the pixel column with the slowest charging can be determined by a detection circuit, such as the detection circuit determining whether the pixel column is charged to the reference voltage V cal , to determine whether it is the slowest charging pixel column, etc.

[0132] Furthermore, after determining the pixel column with the slowest charging speed, the reference current source I of the current mirror circuit 20 is adjusted. bias , by changing the reference current source I bias To change the current mirrored by the current mirror circuit 20 in the pixel column, and at the same time, charge the pixel column, the charging time is (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles. At the same time, the data voltage V data Is it consistent with the reference voltage V cal If the data voltage V data With reference voltage V cal The same, then the current reference current source I bias is the reference current source after calibration. At this time, the current reference current source I bias Configuration parameters are stored to facilitate subsequent use of the reference current source I bias Calibrate other pixel columns. If the data voltage V data With reference voltage V cal If they are not the same, the reference current source I of the current mirror circuit 20 is adjusted continuously. bias , until it is charging (2 M -1)*(V cal -V L ) / (V H -V L ) clock cycles, the data voltage V data With reference voltage V cal same.

[0133] Furthermore, after the pixel column with the slowest charging time is calibrated, the time offset values ​​corresponding to the remaining pixel columns are determined based on the charging time of the pixel column with the slowest charging time. In specific implementation, the time offset values ​​corresponding to the remaining pixel columns can be obtained by:

[0134] From the above, we can know and combine Fig. 9 As shown, the slowest charging pixel column starts from voltage V L Charge to V cal The time taken T' max *P w , then the pixel column changes from voltage V L Charging V H The time taken is T max *P w =T' max *P w *(2 M -1) / G cal , which can be achieved through Fig. 9 The similar triangle relationship shown in the figure is deduced, where G cal is the voltage V cal The corresponding pixel grayscale value.

[0135] In the remaining pixel columns, the first pixel column is from the voltage V L Charge to V cal The time used is T'1*P w , then the first pixel column voltage V L Charging V H The time taken to reach is T1*P w =T'1*P w *(2 M -1) / G cal .

[0136] By (T max *P w -T1*P w ) / P w , the clock cycle offset value Offset corresponding to the first pixel column is obtained as:

[0137] △T1=(T' max -T'1)*(2 M -1) / G cal ;

[0138] Furthermore, the clock cycle offset value Offset corresponding to the second pixel column is:

[0139] △T2=(T' max -T'2)*(2 M -1) / G cal ;

[0140] By analogy, the clock cycle offset value Offset corresponding to any pixel column k in other pixel columns is:

[0141] △T k =(T'max -T' k )*(2 M -1) / G cal .

[0142] Since the gray value G of a pixel on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k , where G k is the grayscale value of a pixel on any pixel column k, t k0 is a pixel G on any pixel column k k The corresponding charging time.

[0143] Therefore, the clock cycle offset value Offset corresponding to any pixel point on any pixel column k is:

[0144] △T k0 / △T k =t k0 / t k =G k / (2 M -1).

[0145] After the clock cycle number offset value Offset corresponding to any pixel point on any pixel column k is determined, the clock cycle length Pw may be further used to determine the time offset value corresponding to any pixel point on any pixel column k.

[0146] In this embodiment, the gray value G of a pixel point on any pixel column k is k and the maximum gray value is G k / (2 M -1)=t k0 / t k It can be obtained by combining Fig. 9 As shown, for any pixel point on pixel column k, the corresponding gray value formula G k =(2 M -1)*(I k / C k )*t k0 / (V H -V L ). For any pixel column k, (I k / C k ) is a constant, (2 M -1) and (V H -V L ) is a constant value, G k and t k0 is proportional to the grayscale value G corresponding to any two pixels on the pixel column.k1 and G k2 , all have G k1 / G k2 =t k1 / t k2 ; Therefore, the pixel point G on any pixel column k k and the maximum gray value is G k / (2 M -1)=t k0 / t k Among them, I k is the actual charging current of any pixel column k, C k is the actual load capacitance of any pixel column k.

[0147] The present invention also discloses a display screen having the above-mentioned charging and discharging circuit, which can charge or discharge the load capacitors in the pixel circuits of all columns in the same row, so that the voltage value of the load capacitors meets the actual use requirements, and the charging or discharging of the load capacitors in the pixel circuits of each column is independent and does not interfere with each other. The display screen here includes but is not limited to OLED / LED / LCD display screens.

[0148] At the same time, the present invention also discloses an electronic device having the above-mentioned display screen, which can charge or discharge the load capacitors in the pixel circuits of all columns in the same row in a short time, so that the voltage value of the load capacitors meets the actual use requirements, and the charging or discharging of the load capacitors in each column of the pixel circuits is independent and does not interfere with each other. The electronic devices here include but are not limited to smart phones, tablet computers, laptops, televisions, and desktop monitors.

[0149] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A charging and discharging circuit, characterized in that: include at least one load capacitor; at least one preprocessing circuit, each of the preprocessing circuits corresponds to one of the load capacitors, the preprocessing circuit is connected to the corresponding load capacitor to form a connection point, and the preprocessing circuit is used to adjust the voltage of the corresponding load capacitor to a reference voltage value; A current mirror circuit, the current mirror circuit is used to mirror a reference current source and output it through at least one output branch, each of the output branches corresponds to one of the connection points; A compensation circuit for compensating the charging or discharging time of the load capacitance; At least one switch circuit, each of the switch circuits corresponds to an output branch, each of the output branches is connected to the corresponding connection point through the corresponding switch circuit, and the switch circuit is used to control the charging or discharging time of the load capacitor.

2. The charge and discharge circuit according to claim 1, characterized in that: Each of the pre-processing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to a reference voltage value.

3. The charge and discharge circuit according to claim 1, characterized in that: Each switch circuit is turned on or off by a different control signal.

4. The charge and discharge circuit according to claim 1, characterized in that: The preprocessing circuit includes a reference voltage source; The first MOS tube has a source terminal connected to a reference voltage source, a drain terminal connected to the load capacitor to form the connection point, and a gate terminal connected to a control signal.

5. The charge and discharge circuit according to claim 1, characterized in that: The current mirror circuit comprises a second MOS tube, a drain terminal of which is connected to a reference current source, a source terminal of which is connected to a voltage source or ground, and a gate terminal of which is connected to a drain terminal; At least one third MOS tube, the drain terminal of each third MOS tube is used as an output branch, the source terminal is commonly connected to a voltage source or ground, and the gate terminal is connected to the gate terminal of the second MOS tube.

6. The charge and discharge circuit according to claim 5, characterized in that: The second MOS tube and the third MOS tube are selected from PMOS tubes or NMOS tubes.

7. The charge and discharge circuit according to claim 1, characterized in that: The switch circuit includes The fourth MOS tube has a source terminal connected to the output branch, a drain terminal connected to the connection point, and a gate terminal connected to the control signal.

8. The charge and discharge circuit according to claim 1, characterized in that: The compensation circuit includes Detection resistor; A plurality of calibration circuits, each calibration circuit corresponds to a pixel column, and each calibration circuit is connected to a voltage source or ground through a detection resistor to form a detection point, and each calibration circuit is used to receive pixel data and convert the corresponding pixel data into a reference current and a calibration current and input them into the detection resistor; At least one detection circuit is used to obtain a reference voltage and a calibration voltage at a detection point according to a reference current and a calibration current, respectively, and adjust pixel data according to the reference voltage and the calibration voltage.

9. The charge and discharge circuit according to claim 8, characterized in that: All pixel columns share a detection circuit.

10. The charge and discharge circuit according to claim 8, characterized in that: The calibration circuit comprises a fifth MOS tube connected in series with the detection resistor between a voltage source and a ground; A first switch, one end of which is connected to a reference voltage, and an opposite end of which is connected to a gate terminal of a fifth MOS tube; A second switch, one end of which is connected to the data voltage of the pixel column, and the opposite end of which is connected to the gate end of the fifth MOS tube; A third switch, one end of which is connected to a voltage source, and an opposite end of which is connected to a gate terminal of a fifth MOS tube; The switch control circuit is connected to the first switch, the second switch and the third switch, and is used to control the first switch, the second switch and the third switch to be closed or opened according to the pixel data.

11. The charge and discharge circuit according to claim 10, characterized in that: The switch control circuit is a logic circuit composed of gate-level circuits, with inputs of calibration_mode0, calibration_mode1 and data[M], and outputs of Q1, Q2, and Q3. Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch, wherein calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

12. The charge and discharge circuit according to claim 1, characterized in that: The switch circuit controls the charging or discharging time of the load capacitor including: During charging or discharging, the M-bit counter increases from 0 to 2. M -1 counts the charging or discharging time, and when the counter counts from zero to the grayscale value corresponding to a column of pixels, the switch circuit corresponding to the column of pixels is disconnected, M is the color depth of the display, and M is an integer greater than 0.

13. The charge and discharge circuit according to claim 1, characterized in that: The current of each output branch is the same as or proportional to the reference current source.

14. A display screen, characterized in that: A charging and discharging circuit comprising any one of claims 1 to 13.

15. An electronic device, characterized in that: Includes the display screen as claimed in claim 14.

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