Gallium nitride power device
By adopting a stepped integrated field plate structure in gallium nitride high electron mobility transistor, the problem of increasing process complexity and cost increase in the number of field plate layers in the prior art is solved, and a more uniform electric field distribution and more High breakdown voltage and reliability.
Patent Information
- Application Number
- CN202421040010.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-14
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-05-14
AI Technical Summary
Existing GaN high-electron mobility transistors have become bottlenecks when increasing the number of field plate layers to improve breakdown voltage and reliability.
Using a step-shaped integrated field plate structure, a step-shaped side is formed between the gate metal and the drain metal through the design of a multi-layer dielectric layer, so as to rise step by step from the gate metal to the drain metal direction, simplifying the process and reducing it cost.
By simplifying the process and reducing costs, a more uniform electric field distribution is achieved, improving the breakdown voltage and reliability of the device.
Smart Images
Figure CN222532101U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a power semiconductor device, in particular to a gallium nitride power device. Background Art
[0002] Compared with silicon materials, gallium nitride materials have higher energy band gap, electron mobility, saturated electron velocity and breakdown electric field. GaN high electron mobility transistors are common GaN power devices and are widely used in high-frequency applications such as radio frequency and microwave. An existing GaN high electron mobility transistor structure is shown in FIG. Figure 1 As shown, the device is provided with a multi-layer independent field plate 102 located next to the gate metal 101. The main function of the multi-layer independent field plate 102 is to reduce the electric field peak between the gate metal 101 and the drain metal 103, so that the electric field distribution is more uniform, and the breakdown voltage and reliability of the device are improved. Figure 2 As shown, the number of field plate layers 102 is inversely proportional to the maximum electric field between the gate and the drain. The more field plate layers there are, the lower the maximum electric field between the gate and the drain, and the higher the breakdown voltage and reliability of the device. Figure 1 Each layer of field plate of the device needs to be deposited, photolithographically and etched separately. The more layers of field plates there are, the more complicated the process is and the higher the cost is. Utility Model Content
[0003] In order to solve the above-mentioned problems, the utility model provides a gallium nitride power device, the device includes a substrate layer located at the bottom, a buffer layer located above the substrate layer, a channel layer located above the buffer layer, the surface of the channel layer has a horizontal two-dimensional electron gas, a barrier layer located above the channel layer, a first dielectric layer located above the barrier layer, and a first conductive type gallium nitride, a source metal and a drain metal separated by the first dielectric layer, a gate metal is arranged above the first conductive type gallium nitride; at least a second dielectric layer and a third dielectric layer arranged on the second dielectric layer are arranged above the first dielectric layer, and the adjacent dielectric layers are composed of different materials; the first dielectric layer, the second dielectric layer and the third dielectric layer rise in a step-like manner between the gate metal and the drain metal to form a stepped side, a stepped integrated field plate is arranged above the stepped side, and a top dielectric layer is covered above the stepped integrated field plate.
[0004] Furthermore, a fourth dielectric layer is disposed above the third dielectric layer, and the fourth dielectric layer is further extended to form a stepped side edge, so that the stepped integrated field plate is further extended upward; or,
[0005] A fifth dielectric layer is further disposed above the fourth dielectric layer, and the fifth dielectric layer is further extended to form a stepped side edge, so that the stepped integrated field plate is further extended upward; or,
[0006] By analogy, more dielectric layers can be designed according to actual needs to further extend the stepped integrated field plate.
[0007] Furthermore, the stepped integrated field plate rises step by step from the gate metal toward the drain metal.
[0008] Furthermore, the inclination angle @ of the stepped integrated field plate is greater than or equal to 90° and less than 180°.
[0009] Furthermore, the separated dielectric layers are made of the same material to simplify the process.
[0010] The utility model provides a stepped integrated field plate to make the electric field distribution between the gate metal and the drain metal of the device more uniform, thereby improving the breakdown voltage and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a cross-sectional schematic diagram of an existing high electron mobility transistor structure.
[0012] Figure 2 for Figure 1 The relationship between the number of field plate layers and the maximum electric field between the gate and the drain of the device shown.
[0013] Figure 3 The figure is a cross-sectional schematic diagram of a device structure according to an embodiment of the utility model.
[0014] Figure 4 The figure is a cross-sectional schematic diagram of a device structure according to an embodiment of the utility model.
[0015] Figure 5 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0016] Figure 6 It is a cross-sectional schematic diagram of a device structure according to another embodiment of the utility model.
[0017] Figure 7 This is an embodiment of a method for forming a device structure of the utility model. DETAILED DESCRIPTION
[0018] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. The specific implementation does not limit the fixed direction. The devices in the accompanying drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and grooves in the accompanying drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.
[0019] Example 1
[0020] Please refer to Figure 3 , Figure 3 This is a cross-sectional schematic diagram of a device structure of the first embodiment of the utility model, the structure comprising:
[0021] a substrate layer 300 at the bottom;
[0022] a buffer layer 301 located above the substrate layer;
[0023] A channel layer 302 located on the buffer layer;
[0024] a barrier layer 303 located above the channel layer;
[0025] A P-type gallium nitride 304, a source metal 306, a drain metal 307 and a first dielectric layer 308A disposed therebetween are disposed above the barrier layer 303; a gate metal 305 is disposed above the P-type gallium nitride 304;
[0026] A second dielectric layer 309A located above the first dielectric layer 308A;
[0027] a third dielectric layer 308B located above the second dielectric layer 309A;
[0028] a fourth dielectric layer 309B located above the third dielectric layer 308B;
[0029] a fifth dielectric layer 308C located above the fourth dielectric layer 309B;
[0030] A multi-layer stepped integrated field plate 310 located above the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C;
[0031] A sixth dielectric layer 308D located above the multi-layer stepped integrated field plate 310;
[0032] In the above structure, the surface of the channel layer 302 has a horizontal two-dimensional electron gas (2DEG), and forms a current channel between the source and the drain when the device is turned on.
[0033] In the above structure, the multi-layer stepped integrated field plate 310 has five layers of field plates, which are respectively located on the side walls and the upper part of the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C. The sides formed by these dielectric layers are stepped continuous sides, so the field plates formed on these side walls and the upper part are also Figure 3 The multi-layer stepped integrated field plate 310 is shown. In this embodiment, the tilt angle @ of the stepped integrated field plate 310 is equal to or nearly equal to 90°.
[0034] In the above structure, the multi-layer stepped integrated field plate 310 is connected to the source metal 306 or the gate metal 305. In some variant embodiments, it may also be an additionally introduced electrode.
[0035] In one embodiment, the material of the multi-layer stepped integrated field plate 310 may include but is not limited to metals such as titanium, nickel, tungsten, aluminum, gold, and metal compounds thereof.
[0036] In the above structure, the first dielectric layer 308A isolates the upper multi-layer stepped integrated field plate 310 from the lower barrier layer 303 and reduces the lattice defects on the surface of the barrier layer 303 .
[0037] In the above structure, if Figure 4 As shown, the opening width d3 of the third dielectric layer 308B is larger than the opening width d2 of the second dielectric layer 309A, the opening width d4 of the fourth dielectric layer 309B is larger than the opening width d3 of the third dielectric layer 308B, and the opening width d5 of the fifth dielectric layer 308C is larger than the opening width d4 of the fourth dielectric layer 309B. The first to fifth dielectric layers form a multi-layer stepped shape and are located below the multi-layer stepped integrated field plate 310. Therefore, the stepped integrated field plate 310 gradually rises from the gate metal 305 to the drain metal 307, and the opening width gradually increases as the number of layers increases.
[0038] In one embodiment, the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, the fifth dielectric layer 308C, and the sixth dielectric layer 308D are generally composed of oxides or nitrides, such as aluminum oxide, silicon oxide, gallium oxide, aluminum nitride, silicon nitride, etc.
[0039] In the above structure, the second dielectric layer 309A and the third dielectric layer 308B are made of different materials.
[0040] In the above structure, the third dielectric layer 308B and the fourth dielectric layer 309B are made of different materials.
[0041] In the above structure, the fourth dielectric layer 309B and the fifth dielectric layer 308C are made of different materials.
[0042] In one embodiment, the first dielectric layer 308A, the third dielectric layer 308B, the fifth dielectric layer 308C and the sixth dielectric layer 308D may be made of the same material, that is, the materials of the separated dielectric layers may be the same, which simplifies the process.
[0043] In one embodiment, the second dielectric layer 309A and the fourth dielectric layer 309B may be made of the same material to simplify the process.
[0044] In the above structure, the multi-layer stepped integrated field plate 310 reduces the electric field peak between the gate metal 305 and the drain metal 307 when the device withstands voltage, making the electric field distribution more uniform, thereby improving the breakdown voltage and reliability of the device.
[0045] Example 2
[0046] A variation of the device implementation of the present invention is as follows: Figure 5 As shown, and Figure 3 The difference between the embodiments is that the side walls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C are inclined rather than vertical. Therefore, the multi-layer stepped integrated field plates 310 located on the side wall portions of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C are also inclined rather than vertical. In this embodiment, the inclination angle @ of the stepped integrated field plates 310 is greater than 90°.
[0047] In one embodiment, the inclination angles of the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C may be different, and the inclination angles depend on the process conditions.
[0048] In one embodiment, the inclination angles of the multi-layer stepped integrated field plates 310 located at the sidewall portions of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C may be different and depend on the inclination angles of the sidewalls of the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B and the fifth dielectric layer 308C.
[0049] In the above structure, the multi-layer stepped integrated field plate 310 can more effectively reduce the electric field peak between the gate metal 305 and the drain metal 307 when the device withstands voltage, making the electric field distribution more uniform, and further improving the breakdown voltage and reliability of the device.
[0050] Example 3
[0051] A variation of the device implementation of the present invention is as follows: Figure 6 As shown, and Figure 3 The difference between the embodiments is that the multi-layer stepped integrated field plates 310 have three layers instead of five layers of field plates, which are respectively located on the sidewalls and the top of the first dielectric layer 308A, the second dielectric layer 309A and the third dielectric layer 308B.
[0052] In the above structure, the second dielectric layer 309A and the third dielectric layer 308B are made of different materials.
[0053] In one embodiment, the first dielectric layer 308A, the third dielectric layer 308B and the fourth dielectric layer 308C may be made of the same material, that is, the materials of the separated dielectric layers may be the same, so as to simplify the process.
[0054] and with three layers of independent field plates Figure 1 Device Comparison, Figure 3 The embodiment has the same number of field plates, but the process is simpler and the cost is lower.
[0055] Example 4
[0056] A modified device embodiment of the utility model can have more than five Figure 3 Embodiments have a greater number of field plates, such as seven, nine, etc.
[0057] In the above structure, due to Figure 3 Embodiments have more field plates, such as Figure 2 As shown, the maximum electric field between the gate and the drain is low, the breakdown voltage and reliability of the device are high, but the process is more complicated.
[0058] Those skilled in the art should know that the structural features mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more device structures of the embodiments of the present invention.
[0059] Example 5
[0060] According to the structural features of the above-mentioned embodiments of the present invention, combined with the existing GaN high electron mobility transistor manufacturing process, a variety of methods for forming the embodiments can be obtained. An exemplary method for forming the device embodiment of the present invention is as follows: Figure 7 Shown:
[0061] In the first step, a buffer layer 301 is formed on the substrate layer 300, a channel layer 302 is formed on the buffer layer 301, and then a barrier layer 303 is formed on the channel layer 302, as shown in FIG7A.
[0062] The substrate layer 300 is usually composed of silicon, but may also be made of materials such as gallium nitride, silicon carbide, and sapphire.
[0063] The buffer layer 301 may include a combination of multiple material layers such as aluminum gallium nitride, aluminum nitride, gallium nitride, etc. The material layer combination may include multiple gallium nitride layers containing different impurity contents such as carbon and iron, and is beneficial to reducing leakage current and crystal layer dislocation.
[0064] The channel layer 302 may be undoped GaN or doped GaN.
[0065] The barrier layer 303 may be aluminum gallium nitride.
[0066] The above structure may be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth and other processes.
[0067] In the second step, a patterned P-type GaN layer 304 and a gate metal 305 are formed on the barrier layer 303 , as shown in 7B .
[0068] The P-type gallium nitride layer 304 may be formed by chemical vapor deposition, physical vapor deposition, epitaxial growth, etc. The method of forming the patterned P-type gallium nitride 304 may include photolithography, dry etching, wet etching, and other process steps.
[0069] The gate metal layer may be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium, nickel, tungsten, aluminum, gold and their metal compounds. The method of forming the patterned gate metal 305 may include photolithography, dry etching, wet etching and other process steps.
[0070] Generally, the gate metal 305 needs to form a Schottky contact with the P-type GaN 304 located therebelow.
[0071] In the third step, a patterned source metal 306 and a drain metal 307 are formed on the barrier layer 303, as shown in FIG7C.
[0072] The source and drain metal layers may be formed by evaporation, sputtering and other processes, and their constituent materials may include but are not limited to metals such as titanium, nickel, tungsten, aluminum, gold and their metal compounds. The method of forming the patterned source metal 306 and drain metal 307 may include photolithography, dry etching, wet etching and other process steps.
[0073] Generally, the source metal 306 and the drain metal 307 need to form an ohmic contact with the semiconductor thereunder.
[0074] In the fourth step, a first dielectric layer 308A is formed above the barrier layer 303, a second dielectric layer 309A is formed above the first dielectric layer 308A, a third dielectric layer 308B is formed above the second dielectric layer 309A, a fourth dielectric layer 309B is formed above the third dielectric layer 308B, and a fifth dielectric layer 308C is formed above the fourth dielectric layer 309B, as shown in 7D.
[0075] The first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C are generally composed of oxides or nitrides, such as aluminum oxide, silicon oxide, gallium oxide, aluminum nitride, silicon nitride, and the like.
[0076] The second dielectric layer 309A and the third dielectric layer 308B are made of different materials.
[0077] The third dielectric layer 308B and the fourth dielectric layer 309B are made of different materials.
[0078] The fourth dielectric layer 309B and the fifth dielectric layer 308C are made of different materials.
[0079] The first dielectric layer 308A, the third dielectric layer 308B, and the fifth dielectric layer 308C may be made of the same material.
[0080] The second dielectric layer 309A and the fourth dielectric layer 309B may be made of the same material.
[0081] In the fifth step, photolithography is performed on the surface of the fifth dielectric layer 308C to form a patterned photoresist layer 311, as shown in 7E.
[0082] In the sixth step, the fifth dielectric layer 308C is wet-etched to remove a portion of the fifth dielectric layer 308C and expose the fourth dielectric layer 309B thereunder, as shown in FIG7F .
[0083] Since the fourth dielectric layer 309B and the fifth dielectric layer 308C are made of different materials, the fifth dielectric layer 308C can be etched while preserving the fourth dielectric layer 309B through selective wet etching.
[0084] In the seventh step, the fourth dielectric layer 309B is dry-etched to remove a portion of the fourth dielectric layer 309B and expose the third dielectric layer 308B thereunder, as shown in FIG7G .
[0085] Since the third dielectric layer 308B and the fourth dielectric layer 309B are made of different materials, the third dielectric layer 308B can be used as an etching stop layer for dry etching of the fourth dielectric layer 309B.
[0086] In the eighth step, the photoresist layer 311 is removed, and a patterned photoresist layer 312 is formed by photolithography on the surface of the third dielectric layer 308B, as shown in FIG7H.
[0087] In the ninth step, the third dielectric layer 308B is wet-etched and the second dielectric layer 309A is dry-etched to remove the photoresist layer 312, as shown in FIG7I.
[0088] In the tenth step, a multi-layer stepped integrated field plate 310 is formed on the first dielectric layer 308A, the second dielectric layer 309A, the third dielectric layer 308B, the fourth dielectric layer 309B, and the fifth dielectric layer 308C. A sixth dielectric layer 308D is formed on the multi-layer stepped integrated field plate 310, as shown in FIG7J.
[0089] The multi-layer stepped integrated field plate layer may be formed by evaporation, sputtering and other processes, and its constituent materials may include but are not limited to metals such as titanium, nickel, tungsten, aluminum, gold and their metal compounds. The method of forming the patterned multi-layer stepped integrated field plate 310 may include photolithography, dry etching, wet etching and other process steps.
[0090] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps of forming a device. Specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in the field and can be appropriately increased, decreased or changed.
Claims
1. A gallium nitride power device, comprising a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a horizontal two-dimensional electron gas on the surface of the channel layer, a barrier layer above the channel layer, a first dielectric layer above the barrier layer, and a first conductive type gallium nitride, a source metal and a drain metal separated by the first dielectric layer, wherein a gate metal is disposed above the first conductive type gallium nitride; It is characterized in that At least a second dielectric layer and a third dielectric layer disposed on the second dielectric layer are disposed above the first dielectric layer, and adjacent dielectric layers are formed of different materials; The first dielectric layer, the second dielectric layer and the third dielectric layer rise in a stepped manner between the gate metal and the drain metal to form a stepped side edge, a stepped integrated field plate is provided above the stepped side edge, and a top dielectric layer is covered above the stepped integrated field plate.
2. A gallium nitride power device according to claim 1, characterized in that: A fourth dielectric layer is further disposed above the third dielectric layer, and the fourth dielectric layer is further extended to form a stepped side edge, so that the stepped integrated field plate is further extended upward; or, A fifth dielectric layer is further disposed above the fourth dielectric layer, and the fifth dielectric layer is further extended to form a stepped side edge, so that the stepped integrated field plate is further extended upward; or, More dielectric layers are provided to further extend the stepped integrated field plate.
3. A gallium nitride power device according to claim 1 or 2, characterized in that: The stepped integrated field plate rises step by step from the gate metal toward the drain metal.
4. A gallium nitride power device according to claim 1 or 2, characterized in that: The inclination angle of the stepped integrated field plate is greater than or equal to 90° and less than 180°.
5. A gallium nitride power device according to claim 1 or 2, characterized in that: The separated dielectric layers are dielectric layers composed of the same material.