Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises a substrate, a plurality of first reset signal lines, a plurality of second reset signal lines and a plurality of reset signal connecting lines. The substrate comprises a display area and a frame area surrounding the display area, a plurality of first reset signal lines and a plurality of second reset signal lines are located in the display area, a plurality of reset signal connecting lines are located in the frame area, and the reset signal connecting lines are connected with the first reset signal lines. The multiple second reset signal lines are located on the sides, away from the substrate, of the multiple first reset signal lines, and the multiple reset signal connecting lines are located on the sides, close to the substrate, of the multiple second reset signal lines. Thus, before the second reset signal line is formed, the reset signal connecting line located in the frame area can timely lead out static electricity accumulated by the first reset signal line from the display area, so that the risk that a film layer of the display area is broken down by the static electricity can be reduced, and then the yield of the display panel can be improved.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A display panel is a device with display function.

[0003] A display panel includes a substrate, and a plurality of first reset signal lines, a plurality of second reset signal lines, and a reset signal connection line located on the substrate. The first reset signal line and the second reset signal line have different extension directions, and the first reset signal line and the second reset signal line are arranged crosswise. The second reset signal line is located on a side of the first reset signal line away from the substrate, the reset signal connection line and the second reset signal line are of the same layer structure, the reset signal connection line is connected to part of the first reset signal line through the second reset signal line, the reset signal connection line is used to connect a reset signal to part of the first reset signal line, and can be used to derive static electricity on part of the first reset signal line.

[0004] However, before the reset signal connection lines are formed, static electricity on some first reset signal lines is difficult to release, which may easily lead to static electricity breakdown problems, thereby resulting in a low yield of the display panel. Utility Model Content

[0005] The embodiment of the utility model provides a display panel and a display device. The technical solution is as follows:

[0006] According to one aspect of the present invention, a display panel is provided, comprising:

[0007] A substrate, the substrate comprising a display area and a frame area surrounding the display area;

[0008] a plurality of first reset signal lines and a plurality of second reset signal lines, the plurality of first reset signal lines and the plurality of second reset signal lines are located in the display area, the first reset signal lines extend along a first direction, the second reset signal lines extend along a second direction, the first direction and the second direction are staggered, the orthographic projections of the plurality of first reset signal lines on the substrate are arranged crosswise with the orthographic projections of the plurality of second reset signal lines on the substrate, and the plurality of second reset signal lines are located on a side of the plurality of first reset signal lines away from the substrate;

[0009] A plurality of reset signal connection lines are provided, wherein the plurality of reset signal connection lines are located in the frame area, the plurality of reset signal connection lines are connected to the plurality of first reset signal lines, and the plurality of reset signal connection lines are located on a side of the plurality of second reset signal lines close to the substrate.

[0010] Optionally, the plurality of reset signal connection lines are located between the plurality of first reset signal lines and the plurality of second reset signal lines.

[0011] Optionally, the display panel further includes a first source-drain layer and an inorganic layer, the inorganic layer is located between the first reset signal line and the second reset signal line, the first source-drain layer is located between the first reset signal line and the inorganic layer, and the reset signal connecting line and the first source-drain layer are in the same layer structure.

[0012] Optionally, the plurality of reset signal connection lines are a first reset signal connection line, two second reset signal connection lines and a third reset signal connection line, the first reset signal connection line and the third reset signal connection line are respectively connected to two ends of the first reset signal line, and the two second reset signal connection lines are respectively connected to two ends of the first reset signal line;

[0013] The multiple first reset signal lines include a first target routing line, and the second reset signal connection line is used to transmit a second reset signal to the first target routing line. The display area includes multiple sub-pixel areas. In one of the sub-pixel areas, the display panel also includes a designated thin film transistor and a light-emitting unit located on the substrate. The designated thin film transistor is configured to reset the light-emitting unit, and the light-emitting unit is connected to a first electrode of the designated thin film transistor. The first target routing line is connected to a second electrode of the designated thin film transistor. One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0014] Optionally, the plurality of second reset signal lines include a plurality of routing groups arranged along the first direction, and each routing group includes a second target routing line, a third target routing line, and a fourth target routing line;

[0015] The first reset signal connection line is also connected to the second target wiring, the two second reset signal connection lines are connected, and the second reset signal connection line is also connected to the third target wiring, and the third reset signal connection line is also connected to the fourth target wiring.

[0016] Optionally, the border area includes a fan-out area located at one side of the display area in the second direction, the first reset signal connection line includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion is connected to the second portion, the first portion is located at a side of the second portion close to the fan-out area, the first portion is connected to the second target wiring, and the second portion is connected to the first reset signal line;

[0017] The second reset signal connection line includes a third portion extending along the first direction, and a fourth portion and a fifth portion extending along the second direction, the fourth portion and the fifth portion are respectively connected to two ends of the third portion, the third portion is located on a side of the fourth portion close to the fan-out area, the third portion is connected to the third target routing line, and the fourth portion and the fifth portion are respectively connected to two ends of the first reset signal line;

[0018] The third reset signal connection line includes a sixth portion extending along the first direction and a seventh portion extending along the second direction, the sixth portion is connected to the seventh portion, the sixth portion is located on a side of the seventh portion close to the fan-out area, the sixth portion is connected to the fourth target routing line, and the seventh portion is connected to the first reset signal line.

[0019] Optionally, the multiple reset signal connection lines are two first reset signal connection lines, two second reset signal connection lines and two third reset signal connection lines, the two first reset signal connection lines are respectively connected to two ends of the first reset signal line, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line;

[0020] The display panel also includes a plurality of power signal lines and two power signal connection lines. The power signal is located in the display area, the power signal connection line is located in the frame area, and the two power signal connection lines are respectively connected to both ends of the plurality of power signal lines.

[0021] Optionally, the plurality of second reset signal lines include a plurality of routing groups arranged along the first direction, and each routing group includes a second target routing line, a third target routing line, and a fourth target routing line;

[0022] The two first reset signal connection lines are connected, and the first reset signal connection line is also connected to the second target routing line, the two second reset signal connection lines are connected, and the second reset signal connection line is also connected to the third target routing line, and the two third reset signal connection lines are connected, and the third reset signal connection line is also connected to the fourth target routing line.

[0023] Optionally, the border area includes a fan-out area located at one side of the display area in the second direction, the first reset signal connection line includes a first portion extending along the first direction, and a second portion and an eighth portion extending along the second direction, the second portion and the eighth portion are respectively connected to two ends of the first portion, the first portion is located at a side of the second portion close to the fan-out area, the first portion is connected to the second target wiring, and the second portion and the eighth portion are respectively connected to two ends of the first reset signal line;

[0024] The second reset signal connection line includes a third portion extending along the first direction, and a fourth portion and a fifth portion extending along the second direction, the fourth portion and the fifth portion are respectively connected to two ends of the third portion, the third portion is located on a side of the fourth portion close to the fan-out area, the third portion is connected to the third target routing line, and the fourth portion and the fifth portion are respectively connected to two ends of the first reset signal line;

[0025] The third reset signal connection line includes a sixth portion extending along the first direction and a seventh portion and a ninth portion extending along the second direction, the seventh portion and the ninth portion are respectively connected to two ends of the sixth portion, the sixth portion is located on a side of the seventh portion close to the fan-out area, the sixth portion is connected to the fourth target routing line, and the seventh portion and the ninth portion are respectively connected to two ends of the first reset signal line.

[0026] Optionally, the display area includes a plurality of sub-pixel areas arranged in a plurality of rows, and the plurality of reset signal connection lines include two first reset signal connection lines, two second reset signal connection lines, and two third reset signal connection lines;

[0027] The two first reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of odd rows, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of each row, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of even rows;

[0028] The multiple first reset signal lines include a first target routing line, and the second reset signal connection line is used to transmit a second reset signal to the first target routing line. In one of the sub-pixel areas, the display panel also includes a designated thin film transistor and a light-emitting unit located on the substrate, and the designated thin film transistor is configured to reset the light-emitting unit, and the light-emitting unit is connected to a first electrode of the designated thin film transistor, and the first target routing line is connected to a second electrode of the designated thin film transistor, and one of the first electrode and the second electrode is a source, and the other is a drain.

[0029] Optionally, the display panel further comprises an inorganic layer, and the inorganic layer is located on a side of the second reset signal line away from the substrate;

[0030] The reset signal connection lines are two second reset signal connection lines and two third reset signal connection lines, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line;

[0031] The display panel also includes a first routing line extending along the first direction, the first routing line is located in the border area, the border area includes a fan-out area located on one side of the display area in the second direction, the first routing line is located on a side of the second reset signal line close to the fan-out area, the first routing line is connected to at least one of the second reset signal lines, and the first routing line and the second reset signal line are in the same layer structure.

[0032] Optionally, the plurality of reset signal connection lines and the plurality of first reset signal lines are in the same layer structure.

[0033] On the other hand, a display device is provided, comprising a housing and any one of the above-mentioned display panels.

[0034] The beneficial effects brought by the technical solution provided by the embodiment of the utility model include at least:

[0035] A display panel is provided, which includes a substrate, a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of reset signal connection lines. The substrate includes a display area and a frame area surrounding the display area, a plurality of first reset signal lines and a plurality of second reset signal lines are located in the display area, a plurality of reset signal connection lines are located in the frame area, the reset signal connection lines are connected to the plurality of first reset signal lines, a plurality of second reset signal lines are located on a side of the plurality of first reset signal lines away from the substrate, and a plurality of reset signal connection lines are located on a side of the plurality of second reset signal lines close to the substrate. In this way, before the second reset signal lines are formed, the reset signal connection lines located in the frame area can timely guide the static electricity accumulated in the first reset signal lines out of the display area, thereby reducing the risk of the film layer in the display area being broken down by static electricity, and further improving the yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic diagram of the structure of a display panel;

[0038] Figure 2 It is a structural schematic diagram of a display panel provided by an embodiment of the utility model;

[0039] Figure 3 yes Figure 2 A schematic diagram of a cross-sectional structure of a display panel is provided;

[0040] Figure 4 It is a structural schematic diagram of a part of the structure of another display panel provided by an embodiment of the utility model;

[0041] Figure 5 It is a structural schematic diagram of a part of the structure of another display panel provided by an embodiment of the utility model;

[0042] Figure 6 It is a structural schematic diagram of a part of the structure of another display panel provided by an embodiment of the utility model;

[0043] Figure 7 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the utility model;

[0044] Figure 8 is a schematic structural diagram of another display panel provided by an embodiment of the utility model;

[0045] Fig. 9 It is a signal connection diagram of a display panel provided by the related technology;

[0046] Fig.10 yes Figure 8 The signal connection diagram of the display panel provided;

[0047] Fig.11 is a schematic structural diagram of another display panel provided by an embodiment of the utility model;

[0048] Fig.12 yes Fig.11 An enlarged schematic diagram of a partial structure of a display panel is provided;

[0049] Fig.13 is a schematic structural diagram of another display panel provided by an embodiment of the utility model;

[0050] Fig.14 yes Fig.13 The signal connection diagram of the display panel provided;

[0051] Fig.15 is a schematic structural diagram of another display panel provided by an embodiment of the utility model;

[0052] Fig.16 yes Fig.15 An enlarged schematic diagram of a partial structure of a display panel is provided;

[0053] Fig.17 is a top view schematic diagram of a part of the structure of another display panel provided by an embodiment of the utility model;

[0054] Fig.18 for Fig.17 A schematic top view of a gate layer in a display panel is provided;

[0055] Fig.19 for Fig.17 A schematic top view of a first source / drain layer in a display panel is provided;

[0056] Fig. 20 for Fig.17 A schematic top view of a second source / drain layer in a display panel is provided;

[0057] Fig.21 This is a signal connection diagram of another display panel provided by an embodiment of the utility model;

[0058] Fig. 22 is a schematic structural diagram of another display panel provided by an embodiment of the utility model;

[0059] Fig.23 yes Fig. 22 A schematic diagram of a cross-sectional structure of a display panel is provided.

[0060] The above drawings have shown clear embodiments of the present invention, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present invention in any way, but to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present invention more clear, the implementation mode of the present invention will be further described in detail below with reference to the accompanying drawings.

[0062] Please refer to Figure 1 , Figure 1 The present invention is a schematic diagram of the structure of a display panel, wherein the display panel 10 includes a substrate 11, and a plurality of first reset signal lines 12, a plurality of second reset signal lines 13 and a reset signal connection line 14 located on the substrate 11. The first reset signal line 12 and the second reset signal line 13 have different extension directions, and the orthographic projection of the first reset signal line 12 on the substrate 11 and the orthographic projection of the second reset signal line 13 on the substrate 11 are arranged crosswise. The second reset signal line 13 is located on the side of the first reset signal line 12 away from the substrate, the reset signal connection line 14 and the second reset signal line 13 are in the same layer structure, the reset signal connection line 14 is connected to the first reset signal line 12 through the second reset signal line 13, and the reset signal connection line 14 is used to connect the reset signal to part of the first reset signal line 12.

[0063] However, before the reset signal connection line 14 is formed, some of the first reset signal lines 12 are not connected to the reset signal connection line 14, and the static electricity accumulated on some of the first reset signal lines 12 is difficult to release, which may easily lead to static electricity breakdown problems in the display area, thereby resulting in a low yield of the display panel 10.

[0064] The present invention provides a display panel. Figure 2 and Figure 3 , Figure 2 : is a schematic diagram of the structure of a display panel provided by an embodiment of the utility model (to clearly illustrate the first reset signal line, the second reset signal line and the reset signal connection line, Figure 2 The insulating layer is not shown, but this is not limited in the present embodiment. Figure 3 yes Figure 2 A schematic diagram of a cross-sectional structure of a display panel provided ( Figure 3 Can be Figure 2 A schematic diagram of a cross-sectional structure of a display panel at A1-A1 is provided, wherein the display panel 20 includes:

[0065] The substrate 21 includes a display area 211 and a frame area 212 surrounding the display area 211 .

[0066] A plurality of first reset signal lines 22 and a plurality of second reset signal lines 23 are provided, and the plurality of first reset signal lines 22 and the plurality of second reset signal lines 23 are located in the display area 211, the first reset signal lines 22 extend along a first direction X, and the second reset signal lines 23 extend along a second direction Y, the first direction X and the second direction Y are staggered, the orthographic projections of the plurality of first reset signal lines 22 on the substrate 21 and the orthographic projections of the plurality of second reset signal lines 23 on the substrate 21 are cross-arranged, and the plurality of second reset signal lines 23 are located on a side of the plurality of first reset signal lines 22 away from the substrate 21.

[0067] The reset signal connection lines 24 are located in the frame area 212 , connected to the first reset signal lines 22 , and located on one side of the second reset signal lines 23 close to the substrate 21 .

[0068] It should be noted that Figure 2 Only two reset signal connection lines 24 are shown, but the embodiment of the utility model does not limit the number of the reset signal connection lines 24 , and specifically, the number can be determined according to the pixel circuit adopted by the display panel 20 .

[0069] In summary, the embodiment of the utility model provides a display panel including a substrate, a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of reset signal connection lines. The substrate includes a display area and a frame area surrounding the display area, a plurality of first reset signal lines and a plurality of second reset signal lines are located in the display area, a plurality of reset signal connection lines are located in the frame area, the reset signal connection lines are connected to the plurality of first reset signal lines, a plurality of second reset signal lines are located on a side of the plurality of first reset signal lines away from the substrate, and a plurality of reset signal connection lines are located on a side of the plurality of second reset signal lines close to the substrate. In this way, before the second reset signal lines are formed, the reset signal connection lines located in the frame area can timely guide the static electricity accumulated in the first reset signal lines out of the display area, thereby reducing the risk of the film layer in the display area being broken down by static electricity, and further improving the yield of the display panel.

[0070] The following is an explanation of the position of the reset signal connection line in the direction perpendicular to the substrate:

[0071] There are multiple situations in which the multiple reset signal connection lines are located on the side of the multiple second reset signal lines 23 close to the substrate 21. Figure 3The reset signal connection line 24 is located between the first reset signal line 22 and the second reset signal line 23 . The reset signal connection line 24 and the first reset signal line 22 may be connected through a via to conduct static electricity on the first reset signal line 22 .

[0072] Alternatively, please refer to Figure 4 , Figure 4 It is a structural schematic diagram of a partial structure in another display panel provided by an embodiment of the utility model. The reset signal connection line 24 and the first reset signal line 22 are in the same layer structure. The reset signal connection line 24 and the first reset signal line 22 can be directly connected to derive the static electricity on the first reset signal line 22.

[0073] Alternatively, please refer to Figure 5 , Figure 5 It is a structural schematic diagram of a partial structure of another display panel provided by an embodiment of the utility model. The reset signal connection line 24 is located on the side of the first reset signal line 22 close to the substrate 21. The reset signal connection line 24 and the first reset signal line 22 can be connected through a via to conduct static electricity on the first reset signal line 22.

[0074] Optionally, the display panel may further include a first source / drain layer and an inorganic layer, see Figure 6 , Figure 6 It is a structural schematic diagram of a part of the structure in another display panel provided by an embodiment of the utility model. The display panel includes: a substrate 21, a plurality of first reset signal lines 22, a plurality of second reset signal lines 23, a plurality of reset signal connection lines 24, a first source-drain layer 25 and an inorganic layer 26, wherein the inorganic layer 26 is located between the first reset signal line 22 and the second reset signal line 23, the first source-drain layer 25 is located between the first reset signal line 22 and the inorganic layer 26, and the reset signal connection line 24 and the first source-drain layer 25 are in the same layer structure.

[0075] Among them, the inorganic layer 26 can play an isolating role between the first source and drain layer 25 and the second reset signal line 23, avoiding the current of the first source and drain layer 25 and the second reset signal line 23 from interfering with each other. It has been verified by experiments that more static electricity will be generated during the manufacturing process of the inorganic layer 26. By making the reset signal connection line 24 and the first source and drain layer 25 the same layer structure, not only can the effect of simplifying the structure be achieved, but also before more static electricity is generated, the reset signal connection line 24 can be connected to the first reset signal line 22 to conduct static electricity, thereby avoiding the accumulation of static electricity generated during the manufacturing process of the inorganic layer 26 on the first reset signal line 22, reducing the risk of static electricity breakdown. In addition, the first reset signal line 22 can be the same layer structure as the gate layer in the display panel, and the resistance of the conductive material used in the first source and drain layer 25 is less than the resistance of the conductive material used in the gate layer. Exemplarily, the conductive material used in the first source and drain layer 25 can include titanium / aluminum / titanium thin film, and the conductive material used in the gate layer includes molybdenum (Mo). Therefore, static electricity on the first reset signal line 22 is more easily transmitted to the reset signal connection line 24, so that static electricity can be effectively guided out of the display area, thereby improving the yield of the display panel. Figure 6 The specific conductive pattern in the first source-drain layer 25 is not shown, but the embodiment of the present invention is not limited to this.

[0076] The substrate 21 can be used to carry film layers or structures in the display panel. For example, the substrate 21 can be used to carry multiple first reset signal lines 22, multiple second reset signal lines 23, multiple reset signal connection lines 24, a first source and drain layer 25, and an inorganic layer 26.

[0077] The first reset signal line 22 and the second reset signal line 23 can be used to access the reset signal, and the reset signal can include a variety of reset signals with different functions. For example, please refer to Figure 7 , Figure 7 It is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the utility model. The pixel circuit includes eight thin film transistors (T1, T2, T3, T4, T5, T6, T7, T8) and a storage capacitor (Cst), that is, the pixel circuit is an 8T1C structure. The first reset signal line 22 and the second reset signal line 23 can be used to access the first reset signal (Vi1), the second reset signal (Vi2) and the third reset signal (Vi3), wherein the first reset signal can be used to reset the third node (N3), the second reset signal can be used to reset the light-emitting unit, and the third reset signal is used to reset the second node (N2). In addition, the first reset signal line 22 and the second reset signal line 23 can be connected at the intersection of the positive projection, so that a mesh connection structure can be formed, which is convenient for accessing the reset signal to multiple sub-pixels in the display panel.

[0078] The reset signal connection line 24 is connected to the plurality of first reset signal lines 22, and the reset signal connection line 24 can transmit the reset signal to the plurality of first reset signal lines 22. The plurality of reset signal connection lines 24 can be used to transmit different reset signals, for example, corresponding to Figure 7 In the pixel circuit shown, the reset signal connection line 24 may include a first reset signal connection line, a second reset signal connection line and a third reset signal connection line, and are respectively used to transmit the first reset signal, the second reset signal and the third reset signal to the first reset signal line 22 .

[0079] Multiple reset signal connection lines include multiple situations. In an exemplary embodiment, please refer to Figure 8 , Figure 8 : is a schematic diagram of the structure of another display panel provided by an embodiment of the utility model. The multiple reset signal connection lines 24 are a first reset signal connection line 241, two second reset signal connection lines 242 and a third reset signal connection line 243. The first reset signal connection line 241 and the third reset signal connection line 243 are respectively connected to the two ends of the first reset signal line 22, and the two second reset signal connection lines 242 are respectively connected to the two ends of the first reset signal line 22. The first reset signal connection line 241, the second reset signal connection line 242 and the third reset signal connection line 243 are respectively used to transmit different reset signals. Exemplarily, corresponding to Figure 7 In the pixel circuit shown, the two second reset signal connection lines 242 can be connected to the second reset signal (Vi2) at both ends of the first reset signal line 22, the first reset signal connection line 241 can be connected to the first reset signal (Vi1) at one end of the first reset signal line 22, and the third reset signal connection line 243 can be connected to the third reset signal (Vi3) at the other end of the first reset signal line 22.

[0080] The plurality of first reset signal lines 22 include a first target line C1, the second reset signal connection line 242 is used to transmit a second reset signal to the first target line C1, the display area 211 includes a plurality of sub-pixel areas E, in a sub-pixel area E, the display panel also includes a specified thin film transistor and a light emitting unit ( Figure 8 (not shown), the designated thin film transistor is configured to reset the light emitting unit, the light emitting unit is connected to the first electrode of the designated thin film transistor, the first target wiring C1 is connected to the second electrode of the designated thin film transistor, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode. Exemplarily, corresponding to Figure 7In the pixel circuit shown, the first target line C1 is the first reset signal line 22 connected to the second reset signal (Vi2), the designated thin film transistor is the seventh thin film transistor (T7), and the gate of the designated thin film transistor can be connected to the first reset control line (R_H(n)), then the first reset control line (R_H(n)) can control the conduction and disconnection of the designated thin film transistor, when the designated thin film transistor is turned on, the second reset signal connected to the first target line C1 can be output to the light-emitting unit, so that the light-emitting unit can be reset, and the signal residue that may exist in the previous light-emitting stage can be cleared, thereby improving the consistency and stability of the light-emitting unit. Therefore, compared with the first reset signal (Vi1) and the third reset signal (Vi3), the second reset signal (Vi2) connected to the first target line C1 has a greater impact on the light-emitting effect of the light-emitting unit. By setting two second reset signal connection lines 242 to simultaneously connect the second reset signal to both ends of the first target line C1, the stability of the second reset signal can be improved, thereby improving the stability of the reset of the light-emitting unit.

[0081] In addition, the border area 212 may include a fan-out area B1 located on one side of the display area 211 in the second direction Y, and a plurality of fan-out lines B2 are arranged on the fan-out area B1. The reset signal connection line 24 may be electrically connected to the driving chip B3 through the fan-out line B2, so that the reset signal provided by the driving chip B3 can be transmitted to the first reset signal line 22. Figure 8 The sub-pixel region E in FIG. 1 only includes one second reset signal line 23 as an example, but the embodiment of the utility model is not limited to this.

[0082] In each row of sub-pixel regions E, a plurality of connection lines accessing different signals from a first direction are alternately arranged in the gate layer and the source-drain layer, and the resistance of the conductive materials of the gate layer and the source-drain layer is different. When the number of connection lines in each row of sub-pixel regions E is an odd number, the resistance of the connection lines accessing the same signal in two adjacent rows of sub-pixel regions E is different. When the number of connection lines in each row of sub-pixel regions E is an even number, the connection lines accessing the same signal in each row of sub-pixel regions E are of the same layer structure, so that the resistance and capacitance can be kept consistent. In addition, the gate layer and the source-drain layer may also include a plurality of sub-layers, and a plurality of connection lines may also be alternately arranged in the plurality of sub-layers of the gate layer and the source-drain layer. For example, the gate layer may include a first gate layer and a second gate layer, and the thickness and process of the first gate layer and the second gate layer may be different, and the resistance and capacitance also have differences. Therefore, when the number of connection lines in each row of sub-pixel regions E is an even number, the resistance and capacitance of the connection lines accessing the same signal in each row of sub-pixel regions E can be kept consistent.

[0083] Please refer to Fig. 9 , Fig. 9This is a signal connection diagram of a display panel provided by the related art. The second reset signal (Vi2) and the third reset signal (Vi3) are connected from the first direction, and the first reset signal (Vi1) is connected from the second direction. The first reset signal line 12 corresponding to the first reset signal (Vi1) is prone to electrostatic breakdown. In each row of sub-pixel area E, the number of connection lines connected to different reset signals is an even number. In addition, the number of connection lines for other signals connected from the first direction except the reset signal is also an even number, so the number of connection lines in each row of sub-pixel area E is an even number. Please refer to Fig.10 , Fig.10 yes Figure 8 In the signal connection diagram of the display panel provided, the first reset signal connection line 241 and the third reset signal connection line 243 are connected to the reset signal only from one end of the first reset signal line 22, that is, the number of connection lines in each row of sub-pixel area E remains unchanged. The static electricity of the first reset signal line 22 corresponding to the first reset signal (Vi1) can be promptly derived by the first reset signal connection line 241. In this way, on the basis of ensuring that the reset signal connection line 24 successfully connects each reset signal to the first reset signal line 22, it is ensured that the number of signal lines in each row of sub-pixel area E in the first direction X remains an even number, so that the resistance and capacitance of the corresponding signal lines in each row of sub-pixel area E can be kept consistent.

[0084] In addition, in addition to the connection line for accessing the reset signal, other connection lines for signals accessed from the first direction include a power signal connection line VSS, a first connection line STV1, a second connection line STV2, a third connection line STV3, a fourth connection line STV4, a fifth connection line STV5, and a sixth connection line STV6. Other connection lines for signals accessed from the first direction remain unchanged, so the embodiments of the present invention will not be described in detail. For example, corresponding to Figure 7 In the pixel circuit shown, other connection lines for signals connected from the first direction can be used to connect the power signal (VSS), the first reset control signal (R_H(n)), the second reset control signal (R_P(n)), the light emitting control signal (EM), the gate signal (G_N), etc. Among them, the gate of the fifth thin film transistor T5 and the gate of the sixth thin film transistor T6 share the connection line for the light emitting control signal (EM).

[0085] Optionally, in Figure 8 Based on the embodiment shown, the reset signal connection line can also be connected to the second reset signal line, please refer to Fig.11 , Fig.11It is a structural schematic diagram of another display panel provided by an embodiment of the utility model. A plurality of second reset signal lines 23 include a plurality of routing groups C arranged along a first direction X, and each routing group C includes a second target routing line C2, a third target routing line C3, and a fourth target routing line C4. The first reset signal connection line 241 is also connected to the second target routing line C2, two second reset signal connection lines 242 are connected, and the second reset signal connection line 242 is also connected to the third target routing line C3, and the third reset signal connection line 243 is also connected to the fourth target routing line C4. Therefore, the reset signal connection line 24 can not only transmit the reset signal through the first reset signal line 22, but also transmit the reset signal through the second reset signal line 23, so that the input strength and density of the reset signal can be enhanced, and the reset voltage can be further stabilized, thereby improving the display quality of the display panel.

[0086] Optionally, Fig.11 A reset signal connection line arrangement structure is shown, which can improve space utilization. Please refer to Fig.11 and Fig.12 , Fig.12 yes Fig.11 An enlarged schematic diagram of a partial structure of a display panel is provided. The border area 212 may include a fan-out area B1 located on one side of the display area 211 in the second direction Y, the first reset signal connection line 241 includes a first portion D1 extending along the first direction X and a second portion D2 extending along the second direction Y, the first portion D1 is connected to the second portion D2, the first portion D1 is located on a side of the second portion D2 close to the fan-out area B1, the first portion D1 is connected to the second target wiring C2, and the second portion D2 is connected to the first reset signal line 22.

[0087] The second reset signal connection line 242 includes a third portion D3 extending along the first direction X, and a fourth portion D4 and a fifth portion D5 extending along the second direction Y. The fourth portion D4 and the fifth portion D5 are respectively connected to two ends of the third portion D3. The third portion D3 is located on a side of the fourth portion D4 close to the fan-out area B1. The third portion D3 is connected to the third target routing line C3. The fourth portion D4 and the fifth portion D5 are respectively connected to two ends of the first reset signal line 22.

[0088] The third reset signal connection line 243 includes a sixth portion D6 extending along the first direction X and a seventh portion D7 extending along the second direction Y, the sixth portion D7 is connected to the seventh portion D7, the sixth portion D6 is located on the side of the seventh portion D7 close to the fan-out area B1, the sixth portion D6 is connected to the fourth target wiring C4, and the seventh portion D7 is connected to the first reset signal line 22. In addition, the first reset signal connection line 241, the second reset signal connection line 242 and the third reset signal connection line 243 may also include other various arrangement structures, for example, the arrangement positions of the three reset signal connection lines 24 may be changed, and the embodiment of the utility model is not limited to this.

[0089] For another case of multiple reset signal connection lines, please refer to Fig.13 , Fig.13 It is a structural schematic diagram of another display panel provided by an embodiment of the utility model. The multiple reset signal connection lines 24 are two first reset signal connection lines 241, two second reset signal connection lines 242 and two third reset signal connection lines 243, the two first reset signal connection lines 241 are respectively connected to the two ends of the first reset signal line 22, the two second reset signal connection lines 242 are respectively connected to the two ends of the first reset signal line 22, and the two third reset signal connection lines 243 are respectively connected to the two ends of the first reset signal line 22, that is, the three reset signal connection lines 24 can be connected to the reset signal at both ends of the first reset signal line 22 at the same time.

[0090] The display panel also includes a plurality of power signal lines 27 and two power signal connection lines 28, the power signal 27 is located in the display area 211, the power signal connection line 28 is located in the frame area 212, and the two power signal connection lines 28 are respectively connected to both ends of the plurality of power signal lines 27. The power signal connection line 28 can be electrically connected to the driver chip B3 through the fan-out wiring B2, so that the power signal provided by the driver chip B3 can be transmitted to the power signal line 27 to drive the light-emitting unit to emit light.

[0091] Please refer to Fig.13 and Fig.14 , Fig.14 yes Fig.13 The signal connection diagram of the display panel provided shows that, compared with connecting the power signal from the display area 211, by setting the power signal connection line 28 in the frame area 212, the power signal line 27 and the power signal connection line 28 can be regarded as an integral structure, which can reduce the number of connection lines in each row of sub-pixel areas E. Fig.13 In the display panel shown, even if the two ends of the three reset signal connection lines 24 are connected to the reset signal at the same time, the number of connection lines in each row of sub-pixel regions E can still be ensured to be an even number, so that the resistance and capacitance of the corresponding signal lines in each row of sub-pixel regions E can be kept consistent. In addition, Fig.14 Other unchanged connection lines are not shown. For details, please refer to Fig.10 In addition, the power signal connection line 28 can be in the same layer structure as the gate layer or the source and drain layer, but the embodiment of the utility model is not limited to this. The power signal line 27 can be located on the side of the first reset signal line 22 away from the substrate 21, so that the number of wirings in the display area 221 that are in the same layer as the first reset signal line 22 can be reduced, thereby reducing the risk of electrostatic breakdown. The embodiment of the utility model can also increase the area of ​​the power signal connection line 28, for example, the width of the power signal connection line 28 can be increased, thereby reducing the load and improving the image quality.

[0092] Optionally, in Fig.13 Based on the embodiment shown, the reset signal connection line can also be connected to the second reset signal line, please refer to Fig.15 , Fig.15 It is a structural schematic diagram of another display panel provided by an embodiment of the utility model. A plurality of second reset signal lines 23 include a plurality of routing groups C arranged along a first direction X, and each routing group C includes a second target routing line C2, a third target routing line C3, and a fourth target routing line C4. Two first reset signal connection lines 241 are connected, and the first reset signal connection line 241 is also connected to the second target routing line C2, two second reset signal connection lines 242 are connected, and the second reset signal connection line 242 is also connected to the third target routing line C3, two third reset signal connection lines 243 are connected, and the third reset signal connection line 243 is also connected to the fourth target routing line C4. Therefore, the reset signal connection line 24 can not only transmit the reset signal through the first reset signal line 22, but also transmit the reset signal through the second reset signal line 23, so that the input strength and density of the reset signal can be enhanced, and the reset voltage can be further stabilized, thereby improving the display quality of the display panel.

[0093] Optionally, Fig.15 A layout structure of the reset signal connection line 23 is shown, which can improve space utilization. Please refer to Fig.15 and Fig.16 , Fig.16 yes Fig.15 An enlarged schematic diagram of a partial structure of a display panel is provided. The border area 212 may include a fan-out area B1 located on one side of the display area 211 in the second direction Y, the first reset signal connection line 241 includes a first portion D1 extending along the first direction X, and a second portion D2 and an eighth portion D8 extending along the second direction Y, the second portion D2 and the eighth portion D8 are respectively connected to the two ends of the first portion D1, the first portion D1 is located on the side of the second portion D2 close to the fan-out area B1, the first portion D1 is connected to the second target routing line C2, and the second portion D2 and the eighth portion D8 are respectively connected to the two ends of the first reset signal line 22.

[0094] The second reset signal connection line 242 includes a third portion D3 extending along the first direction X, and a fourth portion D4 and a fifth portion D5 extending along the second direction Y. The fourth portion D4 and the fifth portion D5 are respectively connected to two ends of the third portion D3. The third portion D3 is located on a side of the fourth portion D4 close to the fan-out area B1. The third portion D3 is connected to the third target routing line C3. The fourth portion D4 and the fifth portion D5 are respectively connected to two ends of the first reset signal line 22.

[0095] The third reset signal connection line 243 includes a sixth portion D6 extending along the first direction X, and a seventh portion D7 and a ninth portion D9 extending along the second direction Y, and the seventh portion D7 and the ninth portion D9 are respectively connected to both ends of the sixth portion D6, the sixth portion D6 is located on a side of the seventh portion D7 close to the fan-out area B1, the sixth portion D6 is connected to the fourth target wiring C4, and the seventh portion D7 and the ninth portion D9 are respectively connected to both ends of the first reset signal line 22. In addition, the three reset signal connection lines 241 may also include other various arrangement structures, which are not limited in the embodiment of the utility model.

[0096] To clearly illustrate the connection method between the reset signal connection line and the reset signal line, please refer to Fig.17 , Fig.17 is a top view schematic diagram of a partial structure of another display panel provided by an embodiment of the utility model ( Fig.17 shows part of the metal film layer in the display panel, Fig.17 Can be Fig.15 A schematic top view of the structure of the middle part of the area F in the display panel is provided), the metal film layer in the display panel is a multi-layer structure, and specifically, the display panel may include a gate layer, a first source and drain layer, and a second source and drain layer. Among them, the first reset signal line 22 may include a fifth target line C5 connected to the first reset signal, a first target line C1 connected to the second reset signal, and a sixth target line C6 connected to the third reset signal. The first reset signal connection line 241 is connected to the fifth target line C5, the second reset signal connection line 242 is connected to the first target line C1, and the third reset signal connection line 243 is connected to the sixth target line C6.

[0097] For the gate layer, please refer to Fig.18 , Fig.18 for Fig.17A schematic top view of a gate layer in a display panel is provided, wherein the gate layer may include a first gate layer Gate1, a second gate layer Gate2, and a third gate layer Gate3 arranged in a direction away from a substrate. The first portion C1-1 of the first target line and the first portion C6-1 of the sixth target line C6 are in the same layer structure as the first gate layer Gate1, the fifth target line C5 is in the same layer structure as the second gate layer Gate2, and the second portion C1-2 of the first target line and the second portion C6-2 of the sixth target line C6 are in the same layer structure as the third gate layer Gate3.

[0098] For the first source and drain layer, please refer to Fig.19 , Fig.19 for Fig.17 A schematic top view of the first source-drain layer in the provided display panel, the first reset signal connection line 241, the second reset signal connection line 242 and the third reset signal connection line 243 are all in the same layer structure as the first source-drain layer SD1, the power signal line 27 is in the same layer structure as the first source-drain layer SD1, the third portion C1-3 of the first target line and the third portion C6-3 of the sixth target line C6 are all in the same layer structure as the first source-drain layer SD1. The first portion C1-1 of the first target line and the second portion C1-2 of the first target line are bridged through the third portion C1-3 of the first target line to form the first target line C1, and the first portion C6-1 of the sixth target line and the second portion C6-2 of the sixth target line are bridged through the third portion C6-3 of the sixth target line to form the second target line C2.

[0099] For the second source and drain layer, please refer to Fig. 20 , Fig. 20 for Fig.17 A schematic top view of a second source-drain layer in a display panel is provided, wherein the second reset signal line 23 and the power signal connection line 28 are in the same layer structure as the second source-drain layer SD2. Fig. 20 Only one second reset signal line 23 is shown as an example, but the embodiment of the utility model does not limit the number and position of the second reset signal lines 23 .

[0100] For another case of multiple reset signal connection lines, please refer to Fig.21 , Fig.21This is another signal connection schematic diagram of a display panel provided by an embodiment of the utility model. The display area includes a plurality of sub-pixel areas E arranged in multiple rows, and the plurality of reset signal connection lines 24 are two first reset signal connection lines 241, two second reset signal connection lines 242, and two third reset signal connection lines 243. The two first reset signal connection lines 241 are respectively connected to the two ends of the first reset signal line 22 in the sub-pixel areas E of odd rows, the two second reset signal connection lines 242 are respectively connected to the two ends of the first reset signal line 22 in the sub-pixel areas E of each row, and the two third reset signal connection lines are respectively connected to the two ends of the first reset signal line 22 in the sub-pixel areas E of even rows. In this way, it can be ensured that the number of signal lines in each row of sub-pixel areas E in the first direction X remains an even number, so that the resistance and capacitance of the corresponding signal lines in each row of sub-pixel areas E can be kept consistent. In addition, Fig.21 Other unchanged connection lines are not shown. For details, please refer to Fig.10 The illustrated embodiment.

[0101] Among them, the plurality of first reset signal lines 22 include a first target line C1, and the second reset signal connection line 242 is used to transmit a second reset signal to the first target line C1. In a sub-pixel area E, the display panel also includes a designated thin film transistor and a light-emitting unit located on the substrate 21. The designated thin film transistor is configured to reset the light-emitting unit. The light-emitting unit is connected to the first electrode of the designated thin film transistor, and the first target line C1 is connected to the second electrode of the designated thin film transistor. One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode. The second reset signal transmitted by the second reset signal connection line 242 has a greater impact on the light-emitting effect of the light-emitting unit. Therefore, two second reset signal connection lines 242 are set to simultaneously connect the second reset signal to both ends of the first target line C1 of each row, which can improve the stability of the second reset signal, thereby improving the stability of the reset of the light-emitting unit.

[0102] In an exemplary embodiment, the risk of electrostatic breakdown can also be reduced by adjusting the position of the inorganic layer. Fig. 22 and Fig.23 , Fig. 22 is a schematic diagram of the structure of another display panel provided by an embodiment of the utility model, Fig.23 yes Fig. 22 A schematic diagram of a cross-sectional structure of a display panel provided ( Fig.23 Can be Fig. 22A schematic diagram of the cross-sectional structure of the display panel at A2-A2 is provided. The display panel also includes an inorganic layer 26, which is located on the side of the second reset signal line 24 away from the substrate 21. The multiple reset signal connection lines 24 are two second reset signal connection lines 242 and two third reset signal connection lines 243, the two second reset signal connection lines 242 are respectively connected to the two ends of the first reset signal line 22, and the two third reset signal connection lines 243 are respectively connected to the two ends of the first reset signal line 22. The display panel also includes a first routing line 29 extending along the first direction X, the first routing line 29 is located in the frame area 212, the frame area 212 includes a fan-out area B1 located on one side of the display area 211 in the second direction Y, the first routing line 29 is located on the side of the second reset signal line 23 close to the fan-out area B1, the first routing line 29 is connected to at least one second reset signal line 23, and the first routing line 29 and the second reset signal line 23 are in the same layer structure. The first routing line 29 can be used to transmit a reset signal to the second reset signal line 23.

[0103] The first reset signal line 22 and the second reset signal line 23 can be connected at the intersection of the orthographic projection to form a mesh connection structure, and the first routing line 29 can be connected to the first reset signal line 22 through the second reset signal line 23, so that the first routing line 29 can extract part of the static electricity on the first reset signal line 22 from the display area 211. A lot of static electricity will be generated during the manufacturing process of the inorganic layer 26. Since the inorganic layer 26 is arranged on the side of the second reset signal line 24 away from the substrate 21, and the first routing line 29 and the second reset signal line 23 are in the same layer structure, before a large amount of static electricity is generated, the static electricity on the first reset signal line 22 can be extracted by the reset signal connection line 24 or the first routing line 29, thereby avoiding the static electricity generated by the inorganic layer 26 from accumulating on the first reset signal line 22 for a long time, which can also reduce the risk of static electricity breakdown.

[0104] In summary, the embodiment of the utility model provides a display panel including a substrate, a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of reset signal connection lines. The substrate includes a display area and a frame area surrounding the display area, a plurality of first reset signal lines and a plurality of second reset signal lines are located in the display area, a plurality of reset signal connection lines are located in the frame area, the reset signal connection lines are connected to the plurality of first reset signal lines, a plurality of second reset signal lines are located on a side of the plurality of first reset signal lines away from the substrate, and a plurality of reset signal connection lines are located on a side of the plurality of second reset signal lines close to the substrate. In this way, before the second reset signal lines are formed, the reset signal connection lines located in the frame area can timely guide the static electricity accumulated in the first reset signal lines out of the display area, thereby reducing the risk of the film layer in the display area being broken down by static electricity, and further improving the yield of the display panel.

[0105] On the other hand, the embodiment of the utility model further provides a display device, which includes a housing and any one of the display panels provided in the above embodiments, and the display panel can be located in the housing. The display device can be various devices including a display function, such as a monitor, a television, a vertical advertising machine, a picture screen device, a mobile phone, various smart wearable devices, etc.

[0106] Since the display device includes the display panel provided by the above embodiment, the display device can also have a similar effect, that is, the yield of the display device can be improved.

[0107] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0108] In the present invention, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth" and "ninth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise clearly defined.

[0109] The above description is only an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: The display panel comprises: A substrate, the substrate comprising a display area and a frame area surrounding the display area; a plurality of first reset signal lines and a plurality of second reset signal lines, the plurality of first reset signal lines and the plurality of second reset signal lines are located in the display area, the first reset signal lines extend along a first direction, the second reset signal lines extend along a second direction, the first direction and the second direction are staggered, the orthographic projections of the plurality of first reset signal lines on the substrate are arranged crosswise with the orthographic projections of the plurality of second reset signal lines on the substrate, and the plurality of second reset signal lines are located on a side of the plurality of first reset signal lines away from the substrate; A plurality of reset signal connection lines are provided, wherein the plurality of reset signal connection lines are located in the frame area, the plurality of reset signal connection lines are connected to the plurality of first reset signal lines, and the plurality of reset signal connection lines are located on a side of the plurality of second reset signal lines close to the substrate.

2. The display panel according to claim 1, characterized in that: The plurality of reset signal connection lines are located between the plurality of first reset signal lines and the plurality of second reset signal lines.

3. The display panel according to claim 2, characterized in that: The display panel also includes a first source-drain layer and an inorganic layer. The inorganic layer is located between the first reset signal line and the second reset signal line. The first source-drain layer is located between the first reset signal line and the inorganic layer. The reset signal connection line and the first source-drain layer are in the same layer structure.

4. The display panel according to claim 3, characterized in that: The plurality of reset signal connection lines are a first reset signal connection line, two second reset signal connection lines and a third reset signal connection line, the first reset signal connection line and the third reset signal connection line are respectively connected to two ends of the first reset signal line, and the two second reset signal connection lines are respectively connected to two ends of the first reset signal line; The multiple first reset signal lines include a first target routing line, and the second reset signal connection line is used to transmit a second reset signal to the first target routing line. The display area includes multiple sub-pixel areas. In one of the sub-pixel areas, the display panel also includes a designated thin film transistor and a light-emitting unit located on the substrate. The designated thin film transistor is configured to reset the light-emitting unit, and the light-emitting unit is connected to a first electrode of the designated thin film transistor. The first target routing line is connected to a second electrode of the designated thin film transistor. One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

5. The display panel according to claim 4, characterized in that: The plurality of second reset signal lines include a plurality of routing groups arranged along the first direction, each routing group including a second target routing line, a third target routing line, and a fourth target routing line; The first reset signal connection line is also connected to the second target wiring, the two second reset signal connection lines are connected, and the second reset signal connection line is also connected to the third target wiring, and the third reset signal connection line is also connected to the fourth target wiring.

6. The display panel according to claim 5, characterized in that: The border area includes a fan-out area located at one side of the display area in the second direction, the first reset signal connection line includes a first portion extending along the first direction and a second portion extending along the second direction, the first portion is connected to the second portion, the first portion is located at a side of the second portion close to the fan-out area, the first portion is connected to the second target wiring, and the second portion is connected to the first reset signal line; The second reset signal connection line includes a third portion extending along the first direction, and a fourth portion and a fifth portion extending along the second direction, the fourth portion and the fifth portion are respectively connected to two ends of the third portion, the third portion is located on a side of the fourth portion close to the fan-out area, the third portion is connected to the third target routing line, and the fourth portion and the fifth portion are respectively connected to two ends of the first reset signal line; The third reset signal connection line includes a sixth portion extending along the first direction and a seventh portion extending along the second direction, the sixth portion is connected to the seventh portion, the sixth portion is located on a side of the seventh portion close to the fan-out area, the sixth portion is connected to the fourth target routing line, and the seventh portion is connected to the first reset signal line.

7. The display panel according to claim 2, characterized in that: The plurality of reset signal connection lines are two first reset signal connection lines, two second reset signal connection lines and two third reset signal connection lines, the two first reset signal connection lines are respectively connected to two ends of the first reset signal line, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line; The display panel also includes a plurality of power signal lines and two power signal connection lines. The power signal is located in the display area, the power signal connection line is located in the frame area, and the two power signal connection lines are respectively connected to both ends of the plurality of power signal lines.

8. The display panel according to claim 7, characterized in that: The plurality of second reset signal lines include a plurality of routing groups arranged along the first direction, each routing group including a second target routing line, a third target routing line, and a fourth target routing line; The two first reset signal connection lines are connected, and the first reset signal connection line is also connected to the second target routing line, the two second reset signal connection lines are connected, and the second reset signal connection line is also connected to the third target routing line, and the two third reset signal connection lines are connected, and the third reset signal connection line is also connected to the fourth target routing line.

9. The display panel according to claim 8, characterized in that: The frame area includes a fan-out area located at one side of the display area in the second direction, the first reset signal connection line includes a first portion extending along the first direction, and a second portion and an eighth portion extending along the second direction, the second portion and the eighth portion are respectively connected to two ends of the first portion, the first portion is located at a side of the second portion close to the fan-out area, the first portion is connected to the second target wiring, and the second portion and the eighth portion are respectively connected to two ends of the first reset signal line; The second reset signal connection line includes a third portion extending along the first direction, and a fourth portion and a fifth portion extending along the second direction, the fourth portion and the fifth portion are respectively connected to two ends of the third portion, the third portion is located on a side of the fourth portion close to the fan-out area, the third portion is connected to the third target routing line, and the fourth portion and the fifth portion are respectively connected to two ends of the first reset signal line; The third reset signal connection line includes a sixth portion extending along the first direction and a seventh portion and a ninth portion extending along the second direction, the seventh portion and the ninth portion are respectively connected to two ends of the sixth portion, the sixth portion is located on a side of the seventh portion close to the fan-out area, the sixth portion is connected to the fourth target routing line, and the seventh portion and the ninth portion are respectively connected to two ends of the first reset signal line.

10. The display panel according to claim 3, characterized in that: The display area includes a plurality of sub-pixel areas arranged in a plurality of rows, and the plurality of reset signal connection lines include two first reset signal connection lines, two second reset signal connection lines, and two third reset signal connection lines; The two first reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of odd rows, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of each row, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line in the sub-pixel areas of even rows; The multiple first reset signal lines include a first target routing line, and the second reset signal connection line is used to transmit a second reset signal to the first target routing line. In one of the sub-pixel areas, the display panel also includes a designated thin film transistor and a light-emitting unit located on the substrate, and the designated thin film transistor is configured to reset the light-emitting unit, and the light-emitting unit is connected to a first electrode of the designated thin film transistor, and the first target routing line is connected to a second electrode of the designated thin film transistor, and one of the first electrode and the second electrode is a source, and the other is a drain.

11. The display panel according to claim 1, characterized in that: The display panel further comprises an inorganic layer, wherein the inorganic layer is located on a side of the second reset signal line away from the substrate; The plurality of reset signal connection lines are two second reset signal connection lines and two third reset signal connection lines, the two second reset signal connection lines are respectively connected to two ends of the first reset signal line, and the two third reset signal connection lines are respectively connected to two ends of the first reset signal line; The display panel also includes a first routing line extending along the first direction, the first routing line is located in the border area, the border area includes a fan-out area located on one side of the display area in the second direction, the first routing line is located on a side of the second reset signal line close to the fan-out area, the first routing line is connected to at least one of the second reset signal lines, and the first routing line and the second reset signal line are in the same layer structure.

12. The display panel according to claim 1, characterized in that: The plurality of reset signal connection lines and the plurality of first reset signal lines are in the same layer structure.

13. A display device, characterized in that: The display device comprises a housing and the display panel according to any one of claims 1 to 12.

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