Double-trench SGT device with double-layer field plate

Abstract

The utility model relates to the power semiconductor technology, in particular to a double-groove SGT device with a double-layer field plate. Compared with a traditional SGT, the SGT structure provided by the utility model has a double-layer field plate structure, the depth of the second field plate is shallower, and the second field plate is closer to a drift region, so that when the device works in a reverse blocking manner, a longitudinal electric field at the corresponding depth of the first field plate is lifted, the electric field distribution is more uniform, and the on-resistance is reduced. And meanwhile, the P-type polycrystalline silicon and the lightly doped N-type polycrystalline silicon in the first field plate form a polycrystalline silicon PN junction, so that the polycrystalline silicon PN junction is introduced to deplete region capacitance and is connected with an original output capacitor in series, and the overall output capacitance is reduced.

Description

Technical Field

[0001] The utility model relates to a power semiconductor technology, in particular to a double-groove SGT device with a double-layer field plate. Background Art

[0002] Power MOSFET (Metal Oxide Semiconductor Fielded-effect Transistor) has excellent performance such as fast switching speed, high input impedance and good thermal stability, and has attracted much attention in intelligent power integrated circuits such as power management. Today, terminal markets such as new energy vehicles, industrial automation, and Internet of Things devices have increasingly higher performance requirements for power MOSFET devices.

[0003] Compared with traditional trench gate VDMOS devices, shield gate VDMOS (SGT) devices have deeper trenches, and the polysilicon inside the trench is divided into two parts. The upper part is a conventional gate electrode used to control the opening and closing of the device, and the lower part of the polysilicon is a buried shield gate electrode (also called a split gate electrode). The shielded gate electrode is led out in the three-dimensional front and back directions through the layout and short-circuited with the source electrode. It is generally set to zero potential when the device is working. It has the following two functions: first, it can be regarded as an internal field plate buried in the body to deplete the carriers in the drift region, which can effectively improve the depletion capacity of the drift region in the device, so that the axial electric field in the drift region of the device produces two electric field peaks, which can significantly increase the doping concentration of the drift region of the device and reduce the device's specific on-resistance; second, it can reduce the gate capacitance of the device to reduce the gate charge and dynamic loss, especially the Miller capacitance of the VDMOS device. Specifically, the overall gate capacitance of the device is mainly composed of the gate-source capacitance Cgs and the gate-drain capacitance, namely the Miller capacitance. In this structure, the overlapping area between the gate and drain electrodes is greatly reduced due to the presence of the shielded gate electrode.

[0004] Under the same withstand voltage conditions, reducing the on-resistance of the device is conducive to improving power density and reducing switching losses during use, which is a key factor in optimizing overall performance. Compared with ordinary VDMOS, the shielded gate connected to the source potential makes the output capacitance of SGT larger. The increase in output capacitance causes the turn-off time to be extended during the switching process; at the same time, as the static conduction characteristics of SGT are further optimized, the output charge introduced by the output capacitor causes a significant increase in the loss caused by the device application process. The larger output capacitance will also cause a reverse overshoot of the drain voltage, affecting the stability of the circuit and even causing device breakdown. Therefore, reducing the on-resistance of the device and reducing the output capacitance of the device are of great significance for increasing speed, reducing losses and improving overall performance. Utility Model Content

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a double-trench SGT device with a double-layer field plate.

[0006] In order to achieve the above utility model purpose, the technical solution of the utility model is as follows:

[0007] A double-trench SGT device with a double-layer field plate includes an N-type substrate 1, an N-type epitaxial layer 2, a shielding gate trench, a control gate trench, a body region 8, and an underlying metal 13;

[0008] Among them, the N-type epitaxial layer 2 is located on the upper surface of the N-type substrate 1; the shielding gate groove and the control gate groove are respectively located on the upper left surface and the upper right surface of the N-type epitaxial layer 2; the shielding gate groove is filled with a shielding gate insulating dielectric 3, and there are a first field plate and a second field plate inside the shielding gate groove; the first field plate is composed of a P-type polysilicon 5 and a lightly doped N-type polysilicon 4; the P-type polysilicon 5 is above the lightly doped N-type polysilicon 4, and the P-type polysilicon 5 and the lightly doped N-type polysilicon 4 are in contact with each other and connected up and down; the top metal 12 penetrates into the shielding gate insulating dielectric 3 to form a second field plate; the second field plate is on the right side of the first field plate, and the second field plate and the first field plate are isolated by an insulating dielectric; the control gate groove is filled with a control gate insulating dielectric 6, and there is an N-type doped control gate polysilicon 7 inside the control gate groove; the trench depth of the shielding gate insulating dielectric 3 is greater than the control gate insulating dielectric The depth of the trench where the dielectric 6 is located; the shielding gate trench and the control gate trench are separated on both sides of the body region 8; the upper surface of the body region 8 has a P-type doped ohmic contact region 11 and an N-type doped source region 9; the P-type doped ohmic contact region 11 is on the left side of the N-type doped source region 9, the P-type doped ohmic contact region 11 is in contact with the side of the shielding gate trench, and the N-type doped source region 9 is in contact with the side of the control gate insulating dielectric 6; the surface of the P-type doped ohmic contact region 11 is lower than the surface of the N-type doped source region 9; the P-type polysilicon 5, the P-type doped ohmic contact region 11, and the N-type doped source region 9 are all directly connected to the top metal 12, and the rest of the device surface except the P-type polysilicon 5, the P-type doped ohmic contact region 11, and the N-type doped source region 9 is isolated from the top metal 12 by the surface insulating dielectric layer 10; the bottom metal 13 is on the lower surface of the device.

[0009] As a preferred embodiment, the material of the top metal layer 12 is selected from aluminum, aluminum-copper alloy, or copper.

[0010] As a preferred embodiment, the material of the shielding gate insulating medium 3 and the control gate insulating medium 6 is silicon dioxide.

[0011] As a preferred embodiment, the depth of the first field plate is greater than the depth of the second field plate, that is, the depth of the top metal 12 extending into the shielding gate insulating medium 3 is less than the sum of the depths of the upper and lower connected P-type polysilicon 5 and lightly doped N-type polysilicon 4.

[0012] As a preferred embodiment, all N-type regions are exchanged with all P-type regions, and after the exchange, a device of opposite conductivity type is formed.

[0013] As a preferred embodiment, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.

[0014] As a preferred embodiment, the doping concentration of the lightly doped nanoparticles is less than 1e18.

[0015] The working principle of the utility model is described below from two aspects:

[0016] (1) Forward conduction of the device

[0017] The utility model provides a double-trench SGT device with a double-layer field plate, in which the connection mode of the electrodes during forward conduction is as follows: the N-type doped control gate polysilicon 7 is connected to the gate potential as the control gate, the top metal 12 is connected to the zero potential, and the bottom metal 13 is connected to the drain high potential. When the gate potential increases to be greater than the threshold voltage, an inversion layer channel is formed on the side of the body region 8 close to the control gate insulating medium 6, and under the action of the high potential of the bottom metal 13, a current path is formed from the N-type doped source region 9 through the inversion layer, the N-type epitaxial layer 2, and the N-type substrate 1 to the bottom metal 13, generating a forward current and the device is forward-conducted.

[0018] (2) Reverse blocking of the device

[0019] The utility model provides a double-trench SGT device with a double-layer field plate, and the connection mode of the electrodes during reverse blocking is: the N-type doped control gate polysilicon 7 is connected to zero potential, the top metal 12 is connected to zero potential, and the bottom metal 13 is connected to the drain high potential. Since the bottom metal 13 is connected to a high potential, the body region 8 and the N-type epitaxial layer 2 form a reverse biased PN junction, and the reverse withstand voltage is borne by the PN junction; at the same time, the first field plate and the second field plate are connected to zero potential so that a depletion layer is generated on the side of the N-type epitaxial layer 2 close to the shielding gate insulating medium 3, so that compared with the N-region electric field in a single PN, the trend of the longitudinal electric field decreasing with increasing depth is slowed down, and the reverse withstand voltage is improved. Compared with the traditional SGT, the polysilicon PN junction formed by the P-type polysilicon 5 and the lightly doped N-type polysilicon 4 in the first field plate in the reverse bias state is reverse biased, and the polysilicon depletion region expands to the side of the lightly doped N-type polysilicon 4 to form a PN junction depletion region capacitor, which is partially connected in series with the original output capacitor, thereby reducing the overall output capacitance.

[0020] The beneficial effects of the utility model are as follows: compared with the traditional SGT, the SGT structure provided by the utility model has a double-layer field plate structure. When the device is in a reverse blocking state, the drift region depleted by the second field plate is shallower, and the drift region depleted by the first field plate is deeper. Since the thickness of the insulating dielectric layer at the second field plate is much smaller than the thickness of the insulating dielectric layer corresponding to the first field plate, the longitudinal electric field at the corresponding depth of the second field plate can be raised, so that the electric field distribution is more uniform and its shape is closer to a rectangle, further optimizing the distribution of the longitudinal electric field and optimizing the relationship between the on-resistance and the breakdown voltage. At the same time, the first field plate is composed of a P-type polysilicon 5 and a lightly doped N-type polysilicon 4 connected up and down. While playing the role of a field plate, a polysilicon PN junction is formed inside. When the device is in the off state, the polysilicon PN junction is in a reverse biased state, and the lightly doped N-type polysilicon 4 region will be depleted downward, thereby introducing the polysilicon PN junction depletion region capacitance, which is equivalent to a significant reduction in the output capacitance of the corresponding part, and the overall output capacitance of the device is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The utility model provides a double-trench SGT device with a double-layer field plate;

[0022] Figure 2-Figure 14 It is a key process step in the manufacturing process of a double-trench SGT device with a double-layer field plate provided by the utility model;

[0023] 1 is an N-type substrate, 2 is an N-type epitaxial layer, 3 is a shielding gate insulating dielectric, 4 is a lightly doped N-type polysilicon, 5 is a P-type polysilicon, 6 is a control gate insulating dielectric, 7 is an N-type doped control gate polysilicon, 8 is a body region, 9 is an N-type doped source region, 10 is a surface insulating dielectric layer, 11 is a P-type doped ohmic contact region, 12 is a top metal, and 13 is a bottom metal. DETAILED DESCRIPTION

[0024] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] Example 1

[0026] like Figure 1 As shown, this embodiment provides a double-trench SGT device with a double-layer field plate, including an N-type substrate 1, an N-type epitaxial layer 2, a shield gate trench, a control gate trench, a body region 8 and an underlying metal 13;

[0027] Among them, the N-type epitaxial layer 2 is located on the upper surface of the N-type substrate 1; the shielding gate groove and the control gate groove are respectively located on the upper left surface and the upper right surface of the N-type epitaxial layer 2; the shielding gate groove is filled with a shielding gate insulating dielectric 3, and there are a first field plate and a second field plate inside the shielding gate groove; the first field plate is composed of a P-type polysilicon 5 and a lightly doped N-type polysilicon 4; the P-type polysilicon 5 is above the lightly doped N-type polysilicon 4, and the P-type polysilicon 5 and the lightly doped N-type polysilicon 4 are in contact with each other and connected up and down; the top metal 12 penetrates into the shielding gate insulating dielectric 3 to form a second field plate; the second field plate is on the right side of the first field plate, and the second field plate and the first field plate are isolated by an insulating dielectric; the control gate groove is filled with a control gate insulating dielectric 6, and there is an N-type doped control gate polysilicon 7 inside the control gate groove; the trench depth of the shielding gate insulating dielectric 3 is greater than the control gate insulating dielectric The depth of the trench where the dielectric 6 is located; the shielding gate trench and the control gate trench are separated on both sides of the body region 8; the upper surface of the body region 8 has a P-type doped ohmic contact region 11 and an N-type doped source region 9; the P-type doped ohmic contact region 11 is on the left side of the N-type doped source region 9, the P-type doped ohmic contact region 11 is in contact with the side of the shielding gate trench, and the N-type doped source region 9 is in contact with the side of the control gate insulating dielectric 6; the surface of the P-type doped ohmic contact region 11 is lower than the surface of the N-type doped source region 9; the P-type polysilicon 5, the P-type doped ohmic contact region 11, and the N-type doped source region 9 are all directly connected to the top metal 12, and the rest of the device surface except the P-type polysilicon 5, the P-type doped ohmic contact region 11, and the N-type doped source region 9 is isolated from the top metal 12 by the surface insulating dielectric layer 10; the bottom metal 13 is on the lower surface of the device.

[0028] Preferably, the material of the top metal layer 12 is selected from aluminum, aluminum-copper alloy, or copper.

[0029] Preferably, the material of the shield gate insulating medium 3 and the control gate insulating medium 6 is silicon dioxide.

[0030] Preferably, the depth of the first field plate is greater than the depth of the second field plate, that is, the depth of the top metal 12 extending into the shielding gate insulating medium 3 is less than the sum of the depths of the upper and lower connected P-type polysilicon 5 and lightly doped N-type polysilicon 4.

[0031] Preferably, all N-type regions are exchanged with all P-type regions, and after the exchange, a device of opposite conductivity type is formed.

[0032] Preferably, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide, or silicon germanium.

[0033] Preferably, the doping concentration of the lightly doped material is less than 1e18.

[0034] The utility model provides a double-trench SGT device with a double-layer field plate, wherein the electrode connection mode during reverse blocking is as follows: the N-type doped control gate polysilicon 7 and the top metal 12 are connected to a low potential, and the bottom metal 13 is connected to a high potential.

[0035] This embodiment also provides a method for preparing a double-trench SGT device with a double-layer field plate, comprising the following steps:

[0036] 1.1. Preparation and epitaxial growth of single crystal silicon. A heavily doped N-type substrate 1 with a crystal orientation of <100> An N-type epitaxial layer 2 with a certain thickness and doping concentration is grown on an N-type substrate 1, such as Figure 2 As shown;

[0037] 1.2. Etching shield gate trench: A shield gate trench accommodating the shield gate insulating medium 3, the first field plate and the second field plate is formed by etching silicon, such as Figure 3 As shown;

[0038] 1.3. Forming a shielding gate insulating dielectric 3 in the shielding gate trench can be done by deposition or thermal growth, such as Figure 4 As shown;

[0039] 1.4. Deposit lightly doped N-type polysilicon 4 inside the insulating medium of the shield gate trench, and the surface of the polysilicon is lower than the device surface, such as Figure 5 As shown;

[0040] 1.5. Deposit highly doped P-type polysilicon 5, and finally use chemical mechanical polishing to ensure that the surface of the P-type polysilicon is level with the device surface, such as Figure 6 As shown;

[0041] 1.6. Etch silicon to form a control gate trench, such as Figure 7 As shown;

[0042] 1.7, thermal growth forms a control gate insulating dielectric 6, such as Figure 8 As shown;

[0043] 1.8. Deposit polysilicon. Deposit polysilicon on the control gate insulating dielectric 6 to form an N-type doped control gate polysilicon 7. Fig. 9 As shown;

[0044] 1.9, inject P-type impurities to form body region 8, such as Fig.10 As shown;

[0045] 1.10. Inject N-type impurities into the corresponding position of the source region to form an N-type doped source region 9, such as Fig.11 As shown;

[0046] 1.11. Deposit a surface insulating dielectric layer 10 on the device surface as isolation, such as Fig.12 As shown;

[0047] 1.11. At the locations where contact needs to be formed, i.e., the surfaces of the first field plate, the second field plate, and the P-type doped ohmic contact region 11, the surfaces are exposed by photolithography, and the surface insulating dielectric layer at the corresponding locations is etched. At the same time, the shielding gate insulating dielectric 3 is deeply etched at the location corresponding to the second field plate to facilitate the subsequent deposition of metal to form the second field plate; and P-type impurities are injected into the ohmic contact holes, such as Fig.13 As shown;

[0048] 1.12, deposit a top metal 12 on the device surface as the second field plate and source contact, and deposit a bottom metal 13 at the bottom of the device as the drain contact, such as Fig.14 shown.

[0049] The working principle of this embodiment is as follows:

[0050] The utility model provides a double-trench SGT device with a double-layer field plate, wherein the electrode connection mode during reverse blocking is as follows: the N-type doped control gate polysilicon 7 is connected to zero potential, the top metal 12 is connected to zero potential, and the bottom metal 13 is connected to the drain high potential.

[0051] When the device is in a reverse blocking state, the drift region depleted by the second field plate is shallower, and the drift region depleted by the first field plate is deeper. Since the thickness of the insulating dielectric layer corresponding to the second field plate is much smaller than the thickness of the insulating dielectric layer corresponding to the first field plate, the longitudinal electric field at the second field plate can be raised, so that the electric field distribution is more uniform, and the relationship between the on-resistance and the breakdown voltage is optimized. At the same time, in addition to assisting the depletion of the drift region, the first field plate forms a polysilicon PN junction inside it. When the device is in the off state, the polysilicon PN junction will be reverse biased and the depletion region will expand to the side of the lightly doped N-type polysilicon 4. The introduced polysilicon PN junction depletion region capacitance greatly reduces the output capacitance of the equivalent corresponding part, thereby reducing the overall output capacitance. Compared with the traditional SGT, the SGT structure provided by the utility model has a double-layer field plate structure, the electric field distribution of the device is improved, the output capacitance is reduced, the switching speed is increased, and the switching loss is reduced.

[0052] The double-trench SGT device with a double-layer field plate proposed by the utility model is also suitable for devices made of semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A double-trench SGT device with a double-layer field plate, characterized in that: It comprises an N-type substrate (1), an N-type epitaxial layer (2), a shielding gate trench, a control gate trench, a body region (8) and a bottom metal (13); The N-type epitaxial layer (2) is located on the upper surface of the N-type substrate (1); the shielding gate trench and the control gate trench are respectively located on the upper left surface and the upper right surface of the N-type epitaxial layer (2); the shielding gate trench is filled with a shielding gate insulating medium (3), and a first field plate and a second field plate are arranged inside the shielding gate trench; the first field plate is composed of a P-type polysilicon (5) and a lightly doped N-type polysilicon (4); the P-type polysilicon (5) is above the lightly doped N-type polysilicon (4), and the P-type polysilicon (5) and the lightly doped N-type polysilicon (4) are in contact with each other and connected up and down; the top metal (12) penetrates into the shielding gate insulating medium (3) to form a second field plate; the second field plate is on the right side of the first field plate, and the second field plate and the first field plate are isolated by the insulating medium; the control gate trench is filled with a control gate insulating medium (6), and an N-type doped control gate polysilicon (7) is arranged inside the control gate trench; the depth of the trench where the shielding gate insulating medium (3) is located is greater than the depth of the trench where the control gate insulating medium (6) is located The shielding gate trench and the control gate trench are separated on both sides of the body region (8); the upper surface of the body region (8) has a P-type doped ohmic contact region (11) and an N-type doped source region (9); the P-type doped ohmic contact region (11) is on the left side of the N-type doped source region (9), the P-type doped ohmic contact region (11) contacts the side of the shielding gate trench, and the N-type doped source region (9) contacts the side of the control gate insulating medium (6); the P-type doped ohmic contact region ( The surface of the device is lower than the surface of the N-type doped source region (9); the P-type polysilicon (5), the P-type doped ohmic contact region (11), and the N-type doped source region (9) are all directly in contact with the top metal (12); the rest of the device surface except the P-type polysilicon (5), the P-type doped ohmic contact region (11), and the N-type doped source region (9) is isolated from the top metal (12) by a surface insulating dielectric layer (10); the bottom metal (13) is on the lower surface of the device.

2. A double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: The material of the top metal (12) is selected from aluminum, aluminum-copper alloy, or copper.

3. A double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: The material of the shielding gate insulating medium (3) and the control gate insulating medium (6) is silicon dioxide.

4. The double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: The depth of the first field plate is greater than the depth of the second field plate, that is, the depth of the top metal (12) extending into the shielding gate insulating medium (3) is less than the sum of the depths of the upper and lower connected P-type polysilicon (5) and lightly doped N-type polysilicon (4).

5. The double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: All N-type regions are swapped with all P-type regions, and after the swap, a device of opposite conductivity type is formed.

6. The double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: The material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.

7. The double-trench SGT device with a double-layer field plate according to claim 1, characterized in that: The doping concentration of light doping is less than 1e18.

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