Silicon carbide VDMOS integrated with Schottky diode
By constructing the masking layer and the homogeneous layer in the silicon carbide VDMOS, the problem of the device's electric field concentration and current unevenness at the gate corner is solved, and the effect of low on-resistance and high reverse recovery characteristics is achieved.
Patent Information
- Application Number
- CN202421297884.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-03-07
- Estimated Expiration
- 2034-06-07
AI Technical Summary
Silicon carbide VDMOS devices are prone to concentration of electric fields at the gate corners, resulting in gate breakdown and current cannot be evenly distributed within the device, resulting in a large on-resistance.
A silicon carbide VDMOS with integrated Schottky diodes was designed to suppress the concentration of electric fields and achieve uniform distribution of current by constructing a masking layer and a homogeneous current layer.
Effectively suppresses the concentration of electric field at the gate corners, reduces on-resistance, improves the reverse recovery characteristics of the device, and reduces process steps and costs.
Smart Images
Figure CN222582866U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a silicon carbide VDMOS with an integrated Schottky diode. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability. However, due to the characteristics of silicon carbide materials, the quality of silicon dioxide gate dielectric generated by it is relatively low compared with silicon process, and the work function gap of the material requires a high thickness of the insulating layer of the gate dielectric. At the corner of the gate of the trench gate structure, electric field concentration is prone to occur, resulting in gate breakdown; because the gate does not cover the entire p-type well area, as the distance from the gate increases, the inversion of the p-type well area decreases when the device is turned on, and all device currents are concentrated on both sides of the gate, and the current cannot be evenly distributed inside the device, resulting in current concentration and large on-resistance. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a silicon carbide VDMOS with an integrated Schottky diode, construct a shielding layer, and suppress the electric field concentration problem existing at the gate corner.
[0004] The utility model is implemented as follows: a silicon carbide VDMOS with an integrated Schottky diode, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;
[0007] A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer; and a groove is provided on the current balancing layer;
[0008] a masking layer, the masking layer being disposed in the groove;
[0009] A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer;
[0010] A source region, wherein a lower side of the source region is connected to an upper side of the well region;
[0011] A source metal layer, the source metal layer is respectively connected to the current balancing layer, the well region and the source region;
[0012] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the masking layer, and the lower part of the gate dielectric layer is located in the groove; and a groove is provided on the gate dielectric layer;
[0013] A gate metal layer, wherein the gate metal layer is disposed in the groove;
[0014] and a source metal layer, wherein the upper side of the source metal layer is connected to the lower side of the silicon carbide substrate.
[0015] The advantages of the present invention are:
[0016] 1. The device adopts VDMOS structure and has the characteristics of low on-resistance;
[0017] Second, in response to the gate reliability problem of VDMOS devices, a masking layer was constructed to suppress the electric field concentration problem at the gate corners;
[0018] 3. To address the problem of narrow current channel, a current balancing layer is constructed. The current balancing layer laterally wraps the source metal layer and the source region. When the device is not turned on, the electrons from the source metal are evenly distributed from the Schottky junction to all lateral regions of the device. After the device is turned on, the electrons from the source region close to the gate dielectric layer are evenly distributed to all lateral regions of the device, ultimately achieving current balancing of the device in all continuous current states, thereby reducing the on-resistance of the device and avoiding heat concentration caused by current concentration in the device.
[0019] Fourth, a Schottky junction with direct contact between the source metal layer and the current-balancing layer is constructed, which can effectively improve the reverse recovery characteristics of the device. Since the constructed Schottky diode can complete the freewheeling when the device is not turned on, there is no need to make an additional source region, which improves the device characteristics while reducing the device process steps and lowering costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0021] Figure 1 The utility model is a schematic diagram of a silicon carbide VDMOS with an integrated Schottky diode.
[0022] Figure 2 The utility model is a flow chart of a method for preparing a silicon carbide VDMOS with an integrated Schottky diode.
[0023] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 1 .
[0024] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 2 .
[0025] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 3 .
[0026] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 4 .
[0027] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 5 .
[0028] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 6 .
[0029] Fig. 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 7 .
[0030] Fig.10 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 8 .
[0031] Fig.11 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 9 .
[0032] Fig.12 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 10 .
[0033] Fig.13 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 10 one.
[0034] Fig.14 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 10 two.
[0035] Fig.15 This is a cross-sectional view of the process of a silicon carbide VDMOS with an integrated Schottky diode in the utility model. Figure 10 three. DETAILED DESCRIPTION
[0036] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0039] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0040] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0041] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide VDMOS with an integrated Schottky diode, including:
[0042] Silicon carbide substrate 101,
[0043] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;
[0044] A current balancing layer 103, wherein the lower side of the current balancing layer 103 is connected to the upper side of the drift layer 102; a groove 1031 is provided on the current balancing layer 103, and the depth of the groove 1031 is 600 nm;
[0045] A masking layer 104, wherein the masking layer 104 is disposed in the groove 1031;
[0046] A well region 105, wherein the lower side of the well region 105 is connected to the upper side of the current balancing layer 103;
[0047] A source region 106, wherein the lower side of the source region 106 is connected to the upper side of the well region 105;
[0048] A source metal layer 107, wherein the source metal layer 107 is respectively connected to the current balancing layer 103, the well region 105 and the source region 106;
[0049] A gate dielectric layer 108, wherein the lower side of the gate dielectric layer 108 is connected to the upper side of the masking layer 104, and the lower part of the gate dielectric layer 108 is located in the groove 1031; a groove 1081 is provided on the gate dielectric layer 108;
[0050] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1081;
[0051] And, a source metal layer 110 , wherein the upper side of the source metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .
[0052] The silicon carbide substrate 101 , the drift layer 102 , the current-balancing layer 103 and the source region 106 are all of N-type, and the well region 105 and the shielding layer 104 are all of P-type.
[0053] The doping concentration of the silicon carbide substrate 101 is 5e18cm -3 The doping concentration of the drift layer 102 is 6e16cm -3 The doping concentration of the current balancing layer 103 is 6e17cm -3 The doping concentration of the masking layer 104 is 1e18cm -3 The doping concentration of the well region 105 is 5e17 cm -3The doping concentration of the source region 106 is 8e18cm -3 The concentration of the silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 110 and reduce the overall on-resistance of the device. The doping concentration of the drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device. The doping concentration of the current-balancing layer 103 is to form a Schottky contact with the source metal layer 107 to construct a Schottky diode and redistribute the current from the source region and the Schottky junction formed by the source metal to the inside of the N-type drift layer relatively evenly, avoiding the burning phenomenon caused by excessive electric field density due to current concentration and reducing the on-resistance of the device; the doping concentration of the masking layer 104 is the electric field concentration suppression effect at the gate corner and The thickness is compromised, and the doping concentration of the source region 106 is to form an ohmic contact with the source metal and reduce the contact resistance; since the barrier of the Schottky diode is smaller than the barrier of the silicon carbide pn junction, constructing a Schottky diode can reduce the forward conduction voltage drop of the device. Since the Schottky diode is a single electron conductive device, compared with the bipolar conductive pn junction diode of the traditional device, the Schottky diode has a fast reverse recovery and improves the reverse recovery characteristics of the device. The P-type source region is not constructed in the device structure. This is because the Schottky diode completes the freewheeling function when the device is not turned on, thereby reducing the process steps of the device and reducing the manufacturing cost of the device.
[0054] The thickness of the silicon carbide substrate 101 of the device is 1 μm, the thickness of the drift layer 102 is 20-30 μm, the thickness of the current balancing layer 103 is 1 μm, the thickness of the well region 104 is 300 nm, the bottom of the well region 104 is at the same height as the bottom of the gate metal layer 109, and the thickness of the source region 106 is 1 μm; the bottom thickness of the gate dielectric layer 108 is 300 nm, and the side wall thickness is 100 nm; the device withstand voltage is 600-1200 V, the thickness of the drift layer 102 is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device, the thickness from the top of the source metal layer 107 to the top of the source region 106 is 200 nm, and the thickness from the top of the source metal layer 107 to the current balancing layer 103 is 200 nm. The thickness is 1500nm, the thickness of the masking layer 104 is 300nm, the thickness from the bottom of the masking layer 104 to the bottom of the current balancing layer 103 is 400nm, the doping concentration and thickness of the well region 105 are designed to increase the gate control ability of the device to the well region 105 while reducing the influence of the well region 105 on the formation of the space charge region of the masking layer 104 and the current balancing layer 103, the current balancing layer 103 can shield the capacitance effect from the gate to the drain of the device, thereby reducing the gate-drain capacitance of the device, reducing the Maitreya platform of the device, and improving the switching speed of the device. The dielectric thickness of the bottom and sidewalls of the device gate is to improve the voltage resistance and process compatibility at the corner of the device gate;
[0055] In response to the gate reliability problem of VDMOS devices, a P-type masking layer was constructed to suppress the electric field concentration problem at the gate corner. The P-type masking layer is located directly below the gate insulating medium of the device. The space charge region formed by the P-type masking layer and the N-type current equalizing layer wraps the gate corner, thereby improving the gate reliability of the device.
[0056] like Figures 2 to 15 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:
[0057] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing a drift layer 102 on the silicon carbide substrate 101, wherein the drift layer 102 has a thickness of 20-30 μm;
[0058] Step 2: Form a current balancing layer 103 in the drift layer 102 by ion implantation into the drift layer 102, with a thickness of 1 μm and an ion implantation energy of 500-830 kev;
[0059] Step 3: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, and forming a masking layer 104 by ion implantation into the current balancing layer 103, with a thickness of 300 μm and an ion implantation energy of 600-700 kev;
[0060] Step 4: forming a barrier layer a on the upper part of the drift layer 102, etching the barrier layer a to form a through hole, and forming a well region 105 in the drift layer 102 by ion implantation into the drift layer 102. The lower side of the well region 105 is connected to the current balancing layer 103, and the thickness is 300 nm. The ion implantation energy is 400-500 kev.
[0061] Step 5: forming a barrier layer a on the upper part of the drift layer 102, etching the barrier layer a to form a through hole, and using ion implantation to form a source region 106 in the drift layer with a thickness of 1 μm and an ion implantation energy of 70-400 kev;
[0062] Step 6, forming a barrier layer a, etching the barrier layer a to form a through hole, and then etching the drift layer 102, the well region 105 and the current-distributing layer 103, the etching depth is 1.8 μm, and the drift layer 102, the well region 105 and the current-distributing layer 103 are etched by wet chemical solution, the chemical solution is a mixture of sulfuric acid and hydrogen peroxide, firstly configuring the ratio of sulfuric acid and water to form a sulfuric acid solution, the ratio is 1:2; then configuring the concentration of hydrogen peroxide, the concentration of hydrogen peroxide is 45%, and finally mixing the sulfuric acid solution and hydrogen peroxide to form a chemical solution, the ratio of sulfuric acid solution and hydrogen peroxide is 3:2, and after etching, dry oxygen oxidation is performed to form a gate dielectric layer 108;
[0063] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 109;
[0064] Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and etching the drift layer 102 to a depth of 1.5 μm, performing metal deposition to form a first metal layer 1071;
[0065] Step 9, remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a through hole, and etch the drift layer 102 to a depth of 200 nm, deposit metal to form a second metal layer 1072, and the source metal layer 107 includes a first metal layer 1071 and a second metal layer 1072.
[0066] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A silicon carbide VDMOS with an integrated Schottky diode, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A current balancing layer, wherein the lower side of the current balancing layer is connected to the upper side of the drift layer; The flow balancing layer is provided with a groove; a masking layer, the masking layer being disposed in the groove; A well region, wherein the lower side of the well region is connected to the upper side of the current balancing layer; A source region, wherein a lower side of the source region is connected to an upper side of the well region; A source metal layer, the source metal layer is respectively connected to the current balancing layer, the well region and the source region; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the masking layer, and the lower part of the gate dielectric layer is located in the groove; and a groove is provided on the gate dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a source metal layer, wherein the upper side of the source metal layer is connected to the lower side of the silicon carbide substrate.
2. The silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The thickness of the masking layer is 300 nm.
3. The silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The thickness of the flow balancing layer is 1000 nm.
4. The silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The depth of the groove is 600 nm.
5. The silicon carbide VDMOS with integrated Schottky diode according to claim 1, characterized in that: The silicon carbide substrate, drift layer, current balancing layer and source region are all N-type, and the well region and masking layer are all P-type.