Photovoltaic cell and photovoltaic module

Abstract

The photovoltaic cell comprises a silicon wafer, a tunneling oxide layer and a doped polycrystalline silicon layer are sequentially arranged on one side of the silicon wafer in the thickness direction, the tunneling oxide layer is provided with a tunneling oxide layer body, a sticking point part is formed on the tunneling oxide layer body, and the doped polycrystalline silicon layer is arranged on one side of the silicon wafer in the thickness direction. The thickness of the sticking point part is d1, and the d1 is more than or equal to 1.81 nm and less than or equal to 1.86 nm; the thickness of the tunneling oxide layer body is d2, and the d2 is larger than or equal to 1.70 nm and smaller than or equal to 1.81 nm. According to the photovoltaic cell provided by the utility model, the thickness of the tunneling oxide layer body and the thickness of the sticking point part are respectively adjusted, so that the yield of the cell in the production process is improved, and the conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaics, in particular to a photovoltaic cell and a photovoltaic component. Background Art

[0002] In the related art, the Tunnel Oxide Passivating Contacts (TOPCon) battery uses tubular plasma enhanced chemical vapor deposition (PECVD) in-situ doping to deposit tunneling silicon oxide and doped amorphous silicon to prepare a tunneling passivation contact structure. The silicon wafer is fixed in a graphite boat through a card point, and is used as an electrode for discharge deposition of a tunneling silicon oxide layer and a doped amorphous silicon layer. The contact of the silicon wafer is mainly achieved through the card point. During the deposition process, the current is transmitted to the silicon wafer through the card point, which will cause the temperature of the card point position to rise. It is easier to grow thicker silicon oxide at this position than at other positions. The thickness of the tunneling silicon oxide has a greater impact on passivation and contact. The tunneling layer at this position is thicker than at other positions, and phosphorus is more difficult to diffuse into the substrate. The tunneling layer has fewer holes. It is difficult for this position to tunnel during electron transmission, resulting in contact problems. The prepared battery will have a card point mark at the card point position, resulting in poor electroluminescence (EL). Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a photovoltaic cell with less stuck point printing and high cell yield.

[0004] Another object of the present invention is to provide a photovoltaic module.

[0005] The photovoltaic cell according to the embodiment of the first aspect of the utility model includes: a silicon wafer, on one side of the silicon wafer in the thickness direction, a tunneling oxide layer and a doped polysilicon layer are sequentially provided, the tunneling oxide layer has a tunneling oxide layer body, a card point portion is formed on the tunneling oxide layer body, the card point portion has a thickness of d1, wherein d1 satisfies: 1.81nm≤d1≤1.86nm; the thickness of the tunneling oxide layer body is d2, wherein d2 satisfies: 1.70nm≤d2≤1.81nm.

[0006] According to the photovoltaic cell of the specific embodiment of the utility model, the purpose of improving the yield of the battery in the production process and improving the battery conversion efficiency is achieved by adjusting the thickness of the tunneling oxide layer body and the thickness of the card point part respectively. By adjusting (reducing) the thickness of the card point part, the area or frequency of occurrence of the card point print at the corresponding position of the card point part is reduced, thereby improving the yield of the produced battery. For example, in the prior art, the corresponding thickness of the card point part is 2.3nm~2.4nm, the occupancy rate of the card point print is 3%, and the yield of the battery is relatively low. When the thickness of the card point part is adjusted to 1.81nm~1.86nm of the utility model, the occupancy rate of the card point print is less than 1%, and the yield of the battery is relatively high. By adjusting the thickness of the tunneling oxide layer body, the conversion efficiency of the photovoltaic cell 100 can be improved.

[0007] According to some embodiments of the present invention, there are a plurality of the card point portions, and the plurality of the card point portions are dispersedly formed at the edge of the tunnel oxide layer.

[0008] According to some embodiments of the present invention, the number of the plurality of card points is three, and the three card points are respectively disposed at different edges of the tunnel oxide layer and are far away from each other.

[0009] According to some embodiments of the present invention, the tunnel oxide layer is a tunnel oxide layer treated by PECVD plasma bombardment.

[0010] According to some embodiments of the present invention, the silicon wafer is an N-type silicon wafer.

[0011] According to some embodiments of the present invention, the tunneling oxide layer is a silicon dioxide layer.

[0012] According to some embodiments of the present invention, the doped polysilicon layer is a phosphorus-doped polysilicon layer.

[0013] According to some embodiments of the present invention, the doping concentration in the doped polysilicon layer is 3E20cm -3 ~3E21cm -3 , preferably 5E20cm -3 ~3E21cm -3 .

[0014] According to some embodiments of the present invention, the thickness of the doped polysilicon layer is d3, wherein d3 satisfies: 20nm≤d3≤300nm; preferably, 60nm≤d3≤150nm.

[0015] The photovoltaic assembly according to the embodiment of the second aspect of the utility model includes the photovoltaic cell according to the embodiment of the first aspect of the utility model.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 It is a schematic structural diagram of a photovoltaic cell according to a specific embodiment of the utility model (only the tunneling oxide layer is shown).

[0019] Reference numerals:

[0020] 100: Photovoltaic cells;

[0021] 1: tunneling oxide layer; 11: tunneling oxide layer body; 12: stuck point. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Figure 1 The photovoltaic cell 100 according to the first embodiment of the present invention is described.

[0023] The photovoltaic cell 100 of the specific embodiment of the present utility model comprises a silicon wafer (not shown), and a tunneling oxide layer 1 and a doped polysilicon layer (not shown) are sequentially provided on one side of the silicon wafer in the thickness direction. In this way, the tunneling oxide layer 1 and the doped polysilicon layer are combined to form a tunneling passivation contact structure of the photovoltaic cell 100 of the present utility model. It can be understood that the "one side" here corresponds to the back side of the photovoltaic cell 100 of the present utility model.

[0024] The tunneling oxide layer 1 has a tunneling oxide layer body 11 , on which a clamping point portion 12 is formed. The clamping point portion 12 is used to clamp the silicon wafer so that the silicon wafer and the graphite boat can be fully fitted.

[0025] Further, the thickness of the card point portion 12 is d1, wherein d1 satisfies: 1.81nm≤d1≤1.86nm. In this way, if d1 is less than 1.81nm, the thickness of the card point portion 12 is small, the silicon wafer is easy to break, and the yield rate of the photovoltaic cell 100 may be reduced; if d1 is greater than 1.86nm, the thickness of the card point portion 12 is large, the contact performance of the card point portion 12 may be poor, and card point prints are likely to appear at the position corresponding to the card point portion 12, resulting in poor electroluminescence (EL) performance of the photovoltaic cell 100. By setting d1 to satisfy 1.81nm≤d1≤1.86nm, the thickness of the card point portion 12 is appropriate, the preparation process of the photovoltaic cell 100 is safe, and the cell yield is high. Optionally, the thickness of the card point portion 12 is 1.81nm, 1.84nm or 1.86nm. But not limited to this.

[0026] Further, the thickness of the tunneling oxide layer body 11 is d2, wherein d2 satisfies: 1.70nm≤d2≤1.81nm. In this way, if d2 is less than 1.70nm, the thickness of the tunneling oxide layer body 11 is small, and the passivation performance of the tunneling oxide layer 1 may be poor; if d2 is greater than 1.81nm, the thickness of the tunneling oxide layer body 11 is large, and the contact performance of the tunneling oxide layer 1 may be poor. By setting d2 to satisfy: 1.70nm≤d2≤1.81nm, the thickness of the tunneling oxide layer body is appropriate, the photovoltaic cell 100 is safe to use, the short-circuit current of the photovoltaic cell 100 is large, and the photoelectric conversion efficiency is high. Optionally, the thickness of the tunnel oxide layer body 11 is 1.70 nm, 1.71 nm, 1.72 nm, 1.73 nm, 1.74 nm, 1.75 nm, 1.76 nm, 1.76 nm, 1.78 nm, 1.79 nm or 1.81 nm, but is not limited thereto.

[0027] According to the photovoltaic cell 100 of the specific embodiment of the utility model, by adjusting the thickness of the tunneling oxide layer body 11 and the thickness of the card point part 12 respectively, the purpose of improving the yield of the battery in the production process and improving the battery conversion efficiency is achieved. By adjusting (reducing) the thickness of the card point part 12, the area or frequency of occurrence of the card point print at the corresponding position of the card point part 12 is reduced, thereby improving the yield of the produced battery. For example, in the prior art, the corresponding thickness of the card point part 12 is 2.3nm~2.4nm, the occupancy rate of the card point print is 3%, and the yield of the battery is low. When the thickness of the card point part 12 is adjusted to 1.81nm~1.86nm of the utility model, the occupancy rate of the card point print is less than 1%, and the yield of the battery is relatively high. By adjusting the thickness of the tunneling oxide layer body 11, the conversion efficiency of the photovoltaic cell 100 can be improved.

[0028] According to some embodiments of the present invention, there are multiple clamping points 12, and the multiple clamping points 12 are dispersedly formed on the tunneling oxide layer 1. In this way, the dispersed clamping points 12 facilitate clamping and fixing of the silicon wafer.

[0029] According to some embodiments of the present invention, there are three clamping points 12, and the three clamping points 12 are respectively arranged at different edges of the tunnel oxide layer 1 and are far away from each other. In this way, the three clamping points 12 are arranged in different directions and in a triangular shape, so that the silicon wafer can be stably clamped. For example, in combination with Figure 1 When the clamping surface of the silicon wafer is a rectangle, the three clamping points 12 can be respectively arranged on the edges of the three sides of the rectangle.

[0030] According to some embodiments of the present invention, the tunneling oxide layer 1 is a tunneling oxide layer treated by PECVD plasma bombardment. In this way, the process parameters of the PECVD plasma bombardment treatment on the stuck point portion 12 can be controlled by the PECVD plasma bombardment treatment, and the silicon oxide deposited on the stuck point portion 12 is etched, thereby reducing the thickness of the stuck point portion 12. Specifically, the tunneling oxide layer 1 treated by PECVD plasma bombardment of the present invention can be described in combination with the process of preparing the tunneling passivation contact structure by PECVD deposition. The process of preparing the tunneling passivation contact structure by PECVD deposition is as follows:

[0031] 1. Using laughing gas or a mixture of laughing gas and argon as the reaction gas, the power deposition power of the tunnel oxide layer 1 is 6000W to 25000W, the power frequency is 30kHZ to 400kHZ, and the deposition pressure is 120Pa to 250Pa. The deposition pressure is small and the deposition power is large. This is because the deposition of tunnel silicon oxide requires low pressure and high power.

[0032] 2. Use pure hydrogen or pure argon as the reaction gas, and use PECVD plasma to bombard the tunneling layer deposited in the first step. If argon is used, the deposition power is 3000W~10000W, the power frequency is 30kHZ~400kHZ, and the deposition pressure is 200Pa~350Pa. Argon is easily ionized and can be discharged at low pressure. If hydrogen is used, the deposition power is 6000W~15000W, the power frequency is 30kHZ~400kHZ, and the deposition pressure is 300Pa~450Pa, because hydrogen requires a higher pressure to discharge. The etching of the card point printing position mainly adopts the high-voltage and low-power method, so that the card point part 12 is easier to be etched;

[0033] 3. Using silane, hydrogen, phosphine or silane, argon, phosphine as reaction gas, tunnel doped amorphous silicon is deposited by PECVD, the power deposition power is 5000W~15000W, the power frequency is 20kHZ~200kHZ, and the deposition pressure is 150Pa~450Pa;

[0034] 4. Using silane and nitrous oxide as reaction gases, a tunneling silicon oxide mask is deposited by PECVD, with a power deposition power of 6000W to 20000W, a power frequency of 30kHZ to 200kHZ, and a deposition pressure of 150Pa to 250Pa;

[0035] 5. High temperature tube furnace annealing, annealing temperature 880℃~980℃, amorphous silicon crystallizes to form a tunnel passivation contact structure.

[0036] Thus, according to the photovoltaic cell 100 of the specific embodiment of the utility model, the silicon oxide at the stuck point is removed by plasma bombardment, thereby improving the yield rate of the production line of the photovoltaic cell 100. In addition, the production process is simple, and no additional process, equipment investment or process window expansion is required, thus saving costs.

[0037] According to some embodiments of the present invention, the silicon wafer is an N-type silicon wafer. The resistivity of the silicon wafer is 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 to 3.5 Ω·cm. With such a configuration, the performance of the silicon wafer is suitable.

[0038] According to some embodiments of the present invention, the tunneling oxide layer 1 is a silicon dioxide layer. In this way, the silicon dioxide layer is suitable for forming the passivation contact structure of the present invention.

[0039] According to some embodiments of the present invention, the doped polysilicon layer is a phosphorus-doped polysilicon layer. Such a configuration can further improve the passivation performance of the doped polysilicon layer.

[0040] According to some embodiments of the present invention, the doping concentration in the doped polysilicon layer is 3E20cm -3 ~3E21cm -3 In this way, the doping concentration in the doped polysilicon layer is appropriate, which can not only improve the passivation performance of the doped polysilicon layer, but also will not affect the conversion efficiency of the photovoltaic cell 100. Preferably, the doping concentration in the doped polysilicon layer is 5E20cm -3 ~3E21cm -3 With such configuration, the doping concentration in the doped polysilicon layer is more appropriate.

[0041] According to some embodiments of the utility model, the thickness of the doped polysilicon layer is d3, wherein d3 satisfies: 20nm≤d3≤300nm. In this way, if d3 is less than 20nm, the thickness of the doped polysilicon layer is small, the safety may be low, and the safe use of the photovoltaic cell 100 may be affected; if d3 is greater than 300nm, the thickness of the doped polysilicon layer is large, which may cause the light absorption effect of the doped polysilicon layer to be large and the short-circuit current to be small, thereby affecting the efficiency of the back of the photovoltaic cell 100. By setting, so that d3 satisfies 20nm≤d3≤300nm, the thickness of the doped polysilicon layer is appropriate, the photovoltaic cell 100 is safe to use, and the conversion efficiency of the back of the photovoltaic cell 100 is high. Optionally, the thickness of the second doped microcrystalline silicon layer 5 is 20nm, 60nm, 100nm, 150nm, 200nm or 300nm. But not limited to this. Preferably, d3 satisfies 60nm≤d4≤150nm, then the thickness of the doped polysilicon layer is appropriate.

[0042] According to an embodiment of the second aspect of the utility model, the utility model provides a photovoltaic assembly, including the photovoltaic cell 100 according to the embodiment of the first aspect of the utility model.

[0043] According to the photovoltaic assembly of the specific embodiment of the present invention, the photovoltaic cell 100 has high conversion efficiency and good yield during the preparation process.

[0044] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0045] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A photovoltaic cell, characterized in that: include: A silicon wafer, wherein a tunnel oxide layer and a doped polysilicon layer are sequentially provided on one side of the silicon wafer in a thickness direction. The tunneling oxide layer has a tunneling oxide layer body, a card point portion is formed on the tunneling oxide layer body, and the card point portion has a thickness of d1, wherein d1 satisfies: 1.81nm≤d1≤1.86nm; The thickness of the tunnel oxide layer body is d2, wherein d2 satisfies: 1.70nm≤d2≤1.81nm.

2. The photovoltaic cell according to claim 1, characterized in that: There are a plurality of the card point portions, and the plurality of the card point portions are dispersedly formed at the edge of the tunnel oxide layer.

3. The photovoltaic cell according to claim 1, characterized in that: There are three of the plurality of card points, and the three card points are respectively disposed at different edges of the tunnel oxide layer and are far away from each other.

4. The photovoltaic cell according to claim 1, characterized in that: The tunnel oxide layer is a tunnel oxide layer treated by PECVD plasma bombardment.

5. The photovoltaic cell according to claim 1, characterized in that: The silicon wafer is an N-type silicon wafer.

6. The photovoltaic cell according to claim 1, characterized in that: The tunneling oxide layer is a silicon dioxide layer.

7. The photovoltaic cell according to claim 1, characterized in that: The doped polysilicon layer is a phosphorus-doped polysilicon layer.

8. The photovoltaic cell according to claim 1, characterized in that: The thickness of the doped polysilicon layer is d3, wherein d3 satisfies: 20nm≤d3≤300nm.

9. The photovoltaic cell according to claim 8, characterized in that: The d3 further satisfies: 60nm≤d3≤150nm.

10. A photovoltaic module, characterized in that: Comprising the photovoltaic cell according to any one of claims 1-9.

Images