Optical sensor based on silicon-based CMOS
By growing germanium films in silicon-based CMOS processes, the infrared wavelength of SPAD array sensors is expanded, the limitations of infrared wavelength applications in the prior art are solved, and a high-performance and low-cost single-chip packaging is achieved.
Patent Information
- Application Number
- CN202421317904.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-11
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-06-11
AI Technical Summary
Existing SPAD array sensors have limitations in infrared wavelength applications, especially the limitations of silicon materials on infrared wavelengths, which make their performance poor in infrared lidar detection.
The silicon-based CMOS process is adopted and germanium film is grown on the basis of silicon material, and the infrared light absorption characteristics of germanium material are used to expand the infrared wavelength of the sensor, realizing a single-chip packaging where the avalanche diode and the silicon-based CMOS circuit are connected on the same plane.
The infrared wavelength of the SPAD array sensor is effectively expanded to 1800nm, improving performance and application range, while reducing costs and improving yield, avoiding the disadvantages of multi-chip stacking packaging.
Smart Images
Figure CN222602920U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of optical sensors, in particular to an optical sensor based on silicon-based CMOS. Background Art
[0002] As artificial intelligence is widely used in various fields, photoelectric conversion devices, as important sensors, are also gaining more and more attention. SPAD (single photon avalanche diode) arrays can be widely used in fields such as homeland security, aerial mapping, lidar, time-of-flight sensing, security monitoring, biomedical imaging, etc., which require detection and imaging under extremely weak light intensity.
[0003] The SPAD array sensor mainly includes an avalanche diode, a bias circuit, a quenching circuit, and a readout circuit to form a complete sensor function. The existing SPAD array sensors are mainly divided into two categories: 1. The avalanche diode 10 made of III-V materials and the auxiliary circuit 20 (including: bias circuit, quenching circuit, readout circuit) realized by silicon-based CMOS (complementary metal oxide semiconductor transistor) process are stacked and packaged, such as Figure 1 This type of SPAD array sensor has good functional parameters, but is difficult to process, has high cost, and has a low yield rate.
[0004] 2. Avalanche diodes 30 are directly manufactured based on silicon-based CMOS technology, and avalanche diode arrays are directly manufactured on silicon-based CMOS auxiliary circuits 40. The two are directly connected through lines 50, so that all sensor functions can be completed on one chip, such as Figure 2 This type of SPAD array sensor is easy to process and has low cost, but SPAD uses silicon material and has poor infrared sensing performance, especially when used in infrared lidar detection. Due to the limitation of silicon material to infrared wavelength, the maximum infrared wavelength can only reach 910nm, which greatly limits its application. Utility Model Content
[0005] In order to solve at least some of the above problems in the prior art, the utility model provides a light sensor based on silicon-based CMOS, comprising:
[0006] One or more single photon avalanche diodes (SPADs);
[0007] One or more silicon-based CMOS transistor circuits, wherein the single photon avalanche diode and the CMOS transistor circuit are located in the same plane and are electrically connected.
[0008] Furthermore, the single photon avalanche diode SPAD comprises:
[0009] buried layer;
[0010] an avalanche zone thin film located above the buried layer;
[0011] A diode doped region, which is located on the upper surface of the avalanche region film;
[0012] A SPAD electrode lead-out region, which is located on the buried layer and on one side, both sides or all around the avalanche region film;
[0013] The SPAD electrode contact region is located on the upper surface of the SPAD electrode lead-out region.
[0014] Further, when the diode doped region is used as the SPAD anode, it is formed by P-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD cathode, all of which are formed by N-type ion doping; or
[0015] When the diode doped region is used as the negative electrode of the SPAD, it is formed by N-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD positive electrode, all of which are formed by P-type ion doping.
[0016] Furthermore, the avalanche zone film is an N-type germanium film, a P-type germanium film, an intrinsic germanium film, an N-type germanium silicon film, a P-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, a P-type GaAs film, an N-type InGaAsP film or a P-type InGaAsP film.
[0017] Furthermore, the SPAD further comprises:
[0018] An isolation buffer wall is located around the avalanche zone film.
[0019] Furthermore, the silicon-based CMOS transistor circuit comprises:
[0020] A silicon-based PMOS transistor circuit comprising:
[0021] N-well;
[0022] Gate;
[0023] A P active region located on the upper surface of the N well; and
[0024] An N active region located on an upper surface of the N well; and
[0025] A silicon-based NMOS transistor circuit comprising:
[0026] P well;
[0027] Gate;
[0028] A P active region, which is located on the upper surface of the P well;
[0029] The N active region is located on the upper surface of the P well.
[0030] Furthermore, it also includes:
[0031] substrate;
[0032] An epitaxial layer is located on the substrate, the single photon avalanche diode is located on the substrate, and the silicon-based CMOS transistor circuit is located in the epitaxial layer.
[0033] Furthermore, it also includes:
[0034] A gate oxide layer, which is located above the epitaxial layer and below the gate;
[0035] an oxide layer, which is located on the gate oxide layer and covers the gate;
[0036] A first dielectric layer, which is located above the oxide layer and above the positive electrode structure;
[0037] a second dielectric layer, which is located on the first dielectric layer;
[0038] The metal wire is electrically connected to the P active region, the N active region, the gate, the diode doped region and the SPAD electrode contact region.
[0039] The utility model has at least the following beneficial effects:
[0040] (1) In the optical sensor of the utility model, the avalanche diode and the CMOS circuit are on the same plane. The silicon-based CMOS process is adopted and a germanium film or other III-V material film is grown on the basis of the silicon material. The avalanche diode is manufactured without affecting the CMOS process and connected to the silicon-based CMOS auxiliary circuit in the same plane, so that all the functions of the sensor can be completed on one chip. (2) The avalanche zone film of the sensor is made of germanium material. By utilizing the physical property that germanium absorbs infrared light better than silicon, its infrared wavelength can be extended to 1800nm, which has greatly improved the performance and application scenarios compared with the all-silicon-based SPAD, especially the application range of the infrared wavelength has been greatly expanded. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.
[0042] Figure 1 A schematic diagram of the structure of a sensor with an existing avalanche diode and a CMOS auxiliary circuit stack is shown;
[0043] Figure 2 The schematic diagram of the structure of the sensor in which the existing avalanche diode array is directly fabricated on the silicon-based CMOS auxiliary circuit is shown;
[0044] Figures 3 to 20 A cross-sectional schematic diagram showing a process of forming a silicon-based CMOS optical sensor according to an embodiment of the present invention; and
[0045] Fig.21 A cross-sectional schematic diagram of a silicon-based CMOS optical sensor according to an embodiment of the present utility model is shown. DETAILED DESCRIPTION
[0046] It should be noted that various components in the various drawings may be shown exaggeratedly for illustrative purposes and are not necessarily correct to scale.
[0047] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be understood as limiting.
[0048] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of multiple elements.
[0049] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person of ordinary skill in the art will understand that, under the guidance of the present invention, required parts or components may be added according to the needs of specific scenarios.
[0050] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".
[0051] It should also be pointed out that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as explicitly or implicitly indicating relative importance.
[0052] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.
[0053] In the utility model, the N-type doping element includes arsenic, phosphorus or antimony; the P-type doping element includes boron, gallium or indium.
[0054] Figures 3 to 20 A cross-sectional schematic diagram shows a process of forming a silicon-based CMOS optical sensor according to an embodiment of the present invention.
[0055] A method for forming a light sensor based on a silicon-based CMOS compatible germanium film comprises:
[0056] Step 1, such as Figure 3 As shown, a photoresist is arranged on a substrate 101, and the photoresist is patterned by a photolithography process to obtain a buried layer region 102. The substrate 101 is a P-type silicon substrate, and may also be an N-type silicon substrate.
[0057] Step 2, such as Figure 4 As shown, N+ ion implantation is performed on the exposed substrate of the buried layer region 102 to generate a buried layer 103, and then the photoresist is removed. The buried layer 103 is an N+ buried layer. The buried layer 103 is the charge collection region of the SPAD.
[0058] Step 3, such as Figure 5 As shown, an epitaxial layer 104 is grown on the substrate 101 , and during the epitaxial process, elements of the buried layer 103 diffuse into the epitaxial layer 104 .
[0059] In this embodiment, if the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer (N-epitaxial layer). If it is an N-type substrate, the epitaxial layer is a P-type epitaxial layer (P-epitaxial layer). In one embodiment of the present invention, the epitaxial temperature is 1000-1200°C.
[0060] Step 4, such as Figure 6 As shown, a photoresist is arranged on the epitaxial layer 104 , and the photoresist is patterned by a photolithography process to obtain a thin film deposition area 105 , exposing the epitaxial layer below. The thin film deposition area 105 is located above the buried layer 103 .
[0061] Step 5, such as Figure 7 As shown, the epitaxial layer 104 exposed in the thin film deposition area 105 is etched to expose a portion of the buried layer 103 to form a thin film deposition groove 1051, and finally the photoresist is removed.
[0062] Optionally, step 6, such as Figure 8As shown, an isolation buffer wall 1052 is formed on the side wall of the thin film deposition groove 1051. The dielectric layer is filled in the thin film deposition groove 1051 by thermal oxidation growth or CVD silicon dioxide deposition or CVD high-resistance polysilicon deposition or other dielectric growth methods, and the dielectric layer on the buried layer 103 is etched away by anisotropic etching, and the dielectric layer around the thin film deposition groove 1051 is retained. This step can be omitted according to requirements.
[0063] Step 6, such as Fig. 9 As shown, an avalanche region film 106 is formed on the buried layer 103. The avalanche region film 106 is formed in the film deposition groove 1051 by chemical vapor deposition CVD or epitaxial growth method, and the excess film material is removed by reverse etching, so that the upper surface of the avalanche region film 106 is flush with the upper surface of the epitaxial layer 104.
[0064] In one embodiment of the present invention, the avalanche region film 106 is an N-type or intrinsic germanium film, and may also be an N-type or intrinsic germanium silicon film.
[0065] The germanium film is used as the SPAD avalanche region, with a thickness of 2-6um to meet the bias voltage of 10V-100V.
[0066] In other embodiments of the present invention, other Group III-V materials, such as gallium arsenide, indium phosphide, etc., may be used to replace the germanium material.
[0067] Step 7, such as Fig.10 As shown, a SPAD electrode lead-out region 1071 and an N well 1072 are formed in the epitaxial layer 104. A photoresist is arranged on the upper surface of the epitaxial layer 104 and the avalanche region film 106, and the photoresist is patterned by a photolithography process to obtain a plurality of N well regions, and N-type ion implantation and diffusion (annealing) are performed on the epitaxial layer exposed in the plurality of N well regions to form the SPAD electrode lead-out region 1071 and the N well 1072, and then the photoresist is removed. The SPAD electrode lead-out region 1071 is an N well adjacent to the avalanche region film 106. The SPAD electrode lead-out region is a negative electrode lead-out region.
[0068] In situations where the noise requirement is low, the SPAD electrode lead-out region can also be subjected to a separate high-concentration N+ type implantation.
[0069] Step 8, such as Fig.11 As shown, a P well 108 is formed in the epitaxial layer 104. A photoresist is arranged on the upper surface of the epitaxial layer 104 and the avalanche region film 106, and the photoresist is patterned by a photolithography process to obtain a P well region, and P-type ion implantation and diffusion are performed on the epitaxial layer exposed in the P well region to form the P well 108, and then the photoresist is removed.
[0070] The order of steps 7 and 8 can be reversed.
[0071] Step 9, such as Fig.12 As shown, a gate oxide layer 109 and a polysilicon layer 110 are sequentially grown on the upper surfaces of the epitaxial layer 104 and the avalanche region film 106 .
[0072] Step 10, such as Fig.13 As shown, the polysilicon layer 110 is etched to form a gate 111. Specifically, a photoresist is arranged on the polysilicon layer 110 and patterned, the polysilicon is etched to obtain the gate 111, and the photoresist is removed.
[0073] Step 11, such as Fig.14 As shown, an oxide layer 112 is deposited on the gate oxide layer 109 and the gate electrode 111.
[0074] Step 12, such as Fig.15 As shown, an N active region 113 is formed in the N well 1072 and the P well 108, and a SPAD electrode contact region 114 is formed in the SPAD electrode lead-out region 1071. Specifically, a photoresist is arranged on the oxide layer 112, and a portion of the photoresist located above the SPAD cathode lead-out region 1071, the N well 1072, and the P well 108 is removed by photolithography, and the exposed oxide layer 112 and the gate oxide layer 109 are etched to expose the SPAD electrode lead-out region 1071, the N well 1072, and the P well 108, and then the exposed SPAD electrode lead-out region 1071, the N well 1072, and the P well 108 are implanted with N+ ions to form an N active region 113 and a SPAD electrode contact region 114. The buried layer 103, the SPAD electrode contact region 114, and the SPAD electrode lead-out region constitute the SPAD cathode.
[0075] Step 13, such as Fig.16 As shown, a diode doped region 115 is formed in the avalanche region film 106 , and a P active region 116 is formed in the N well 1072 and the P well 108 .
[0076] A photoresist is arranged on the oxide layer 112 and a portion of the photoresist located above the N-well 1072, the P-well 108 and the avalanche region film 106 is removed by photolithography, and the exposed oxide layer 112 and the gate oxide layer 109 are etched to expose the N-well, the P-well and the avalanche region film, and then P+ ions are implanted into the exposed avalanche region film, the N-well and the P-well to form the diode doped region 115 and the P active region 116 of the SPAD. The diode doped region serves as the anode of the SPAD.
[0077] The diode doped region 115 serves as the anode of the SPAD and can be synchronously generated by the P active region in the CMOS process.
[0078] Step 14: Fig.17As shown, the first dielectric layer 117 and the second dielectric layer 118 are sequentially deposited to cover the oxide layer 112, the N active region 113, the SPAD electrode contact region 114, the diode doped region 115 and the P active region 116. The first dielectric layer 117 may be, for example, silicon dioxide, and the second dielectric layer 118 may be, for example, silicon nitride.
[0079] Step 15, such as Fig.18 As shown, the N active region 113, the SPAD electrode contact region 114, the diode doped region 115, the P active region 116 and the second dielectric layer 118 above the gate are removed. Specifically, a photoresist is coated on the second dielectric layer 118, and after exposure and development, the photoresist located on the N active region 113, the SPAD electrode contact region 114, the diode doped region 115, the P active region 116 and the gate is removed, and then the exposed second dielectric layer 118 is etched.
[0080] Step 16, such as Fig.19 and 20 As shown, a metal line 120 is formed to connect the N active region 113, the SPAD electrode contact region 114, the diode doped region 115, the P active region 116 and the gate, thereby obtaining a light sensor.
[0081] A photoresist is coated on the second dielectric layer 118, and after exposure and development, the photoresist located on the N active area 113, the SPAD electrode contact area 114, the P active area 116 and the gate and part of the photoresist located on the diode doped area 115 are removed, and then the exposed first dielectric layer 117 is etched, and the oxide layer on the gate is etched to expose the N active area 113, the SPAD electrode contact area 114, the diode doped area 115, the P active area 116 and the gate to form a blind hole 119. A metal layer is formed in the blind hole and on the surface of the second dielectric layer by a hole filling, sputtering or evaporation process, and then a photoresist is coated and patterned, and the metal layer not covered by the photoresist is etched to form a metal wire 120 to achieve metal connection.
[0082] Optionally, in step 17, a passivation layer is deposited on the surface of the light sensor, and then a photoresist is coated and patterned, and finally the passivation layer on the metal wire is removed by etching.
[0083] In another embodiment of the utility model, the buried layer can be made into P+ type, the Ge film can be P- doped or intrinsic type, the P well is used as the positive electrode lead-out area of the SPAD, the P active is used as the positive electrode contact area, and the diode doped area is used as the cathode, which has the same effect. The specific operation is as follows:
[0084] Step 2, perform P+ implantation on the exposed buried layer region of the substrate to generate a P+ buried layer.
[0085] Step 7, forming a SPAD electrode lead-out region and a P-well in the epitaxial layer. A photoresist is arranged on the upper surface of the epitaxial layer and the avalanche region film, and the photoresist is patterned by a photolithography process to obtain a plurality of P-well regions, and P-type ion implantation and diffusion (annealing) are performed on the epitaxial layer exposed in the plurality of P-well regions to form a plurality of SPAD electrode lead-out regions and P-wells, and then the photoresist is removed. The SPAD electrode lead-out region is a P-well adjacent to the avalanche region film 106.
[0086] In situations where the noise requirement is lower, the SPAD electrode lead-out region can also be subjected to a separate high-concentration P-type implantation.
[0087] Step 8, forming an N well in the epitaxial layer. Photoresist is arranged on the upper surface of the epitaxial layer and the avalanche region film, and the photoresist is patterned by photolithography to obtain an N well region, and N-type ion implantation and diffusion are performed on the epitaxial layer exposed in the N well region to form an N well, and then the photoresist is removed.
[0088] Step 12, forming a P active region in the N well and the P well, and forming a SPAD electrode contact region in the SPAD electrode lead-out region. Specifically, a photoresist is arranged on the oxide layer and a portion of the photoresist located above the SPAD electrode lead-out region, the N well and the P well is removed by photolithography, and the exposed oxide layer and the gate oxide layer are etched to expose the SPAD electrode lead-out region, the N well and the P well, and then the exposed SPAD electrode lead-out region, the N well and the P well are implanted with P+ ions to form a P active region and a SPAD electrode contact region. The P+ buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD positive electrode.
[0089] Step 13, forming a diode doped region in the avalanche region thin film, and forming an N active region in the N well and the P well.
[0090] A photoresist is arranged on the oxide layer and the photoresist located above the N-well, P-well and avalanche region film is removed by photolithography, and the exposed oxide layer and gate oxide layer are etched to expose the N-well, P-well and avalanche region film, and then N+ ions are implanted into the exposed avalanche region film, N-well and P-well to form the diode doped region 115 and the N active region of the SPAD. The diode doped region serves as the negative electrode of the SPAD.
[0091] In other embodiments of the present invention, the SPAD positive and negative electrodes and the lead-out region are not compatible, and the sensor formed above has the same effect. For SPADs with higher performance requirements, such as lower noise coefficient, a negative electrode or positive electrode lead-out region injection diffusion process can be added to reduce the lead-out region series resistance. Specific implementation:
[0092] After the N-well and P-well processes are completed, photoresist is applied, and N+ or P+ injection or diffusion is performed on the SPAD cathode lead-out area of the N+ buried layer or the SPAD anode lead-out area of the P+ buried layer. That is, the N-well, P-well and the SPAD electrode lead-out area near the SPAD are made separately.
[0093] Fig.21 A cross-sectional schematic diagram of a silicon-based CMOS optical sensor according to an embodiment of the present utility model is shown.
[0094] like Fig.21 As shown, the optical sensor based on silicon-based CMOS includes a substrate 201, an epitaxial layer 202, a single photon avalanche diode SPAD and a silicon-based CMOS transistor circuit. The single photon avalanche diode SPAD and the silicon-based CMOS transistor circuit are located in the same plane and are connected by metal wires.
[0095] The epitaxial layer 202 is located on the substrate 201. In one embodiment of the present invention, the substrate 201 is a P-type silicon substrate, and may also be an N-type silicon substrate. If the substrate 201 is a P-type substrate, the epitaxial layer 202 is an N-type epitaxial layer (N-epitaxial layer); if it is an N-type substrate, the epitaxial layer is a P-type epitaxial layer (P-epitaxial layer).
[0096] The single photon avalanche diode SPAD includes a buried layer 203 , an avalanche region thin film 204 , a diode doping region 205 , a SPAD electrode lead-out region 206 , and a SPAD electrode contact region 207 .
[0097] The buried layer 203 is an N+ buried layer, which is formed by implanting N+ ions into the substrate and diffusing them. The buried layer 203 serves as a charge (electric field) collection region of the SPAD.
[0098] The buried layer 203 is located between the substrate 201 and the epitaxial layer 202. The avalanche region film 204 is located on the buried layer 203. In one embodiment of the present invention, the avalanche region film 204 is an N-type or intrinsic germanium film. The germanium film is used as the SPAD avalanche region, and the thickness is 2-6um to meet the bias voltage of 10V-100V.
[0099] The avalanche region film may also be an N-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, an N-type InGaAsP film, or the like.
[0100] The diode doping region 205 is located on the upper surface of the avalanche region film 204. P+ ion implantation is performed on the upper surface of the avalanche region film 204 to form the diode doping region 205. The diode doping region serves as the positive electrode of the SPAD.
[0101] The SPAD electrode lead-out region 206 is located on both sides of the avalanche region film 204 and on the buried layer 203. The SPAD electrode lead-out region 206 can also be located on one side or all around the avalanche region film.
[0102] The SPAD electrode lead-out region 206 can be formed by performing N-type ion implantation and diffusion (annealing) on the epitaxial layer 202 .
[0103] The SPAD electrode contact region 207 is located on the upper surface of the SPAD electrode lead-out region 206. N+ ion implantation is performed on the upper surface of the SPAD electrode lead-out region 206 to form the SPAD electrode contact region 114. The buried layer 203, the SPAD electrode lead-out region 206 and the SPAD electrode contact region 207 constitute the negative electrode of the SPAD.
[0104] The silicon-based CMOS transistor circuit is located in the epitaxial layer 202 , and the silicon-based CMOS transistor circuit includes a silicon-based PMOS transistor circuit and a silicon-based NMOS transistor circuit.
[0105] The silicon-based NMOS transistor circuit includes a P-well 208, a P-active region 209, an N-active region 210, and a gate 2151. The P-active region 209 and the N-active region 210 are located on the upper surface of the P-well 208. The P-well 208 is located in the epitaxial layer 202, and the P-well 208 can be formed by implanting and diffusing P-type ions into a portion of the epitaxial layer. The P-active region 209 and the N-active region 210 can be formed by implanting and diffusing P+ ions and N+ ions into the P-well 208. The gate 2151 is located above the epitaxial side 202, specifically above the P-well 208. The material of the gate 2152 is polysilicon.
[0106] The silicon-based PMOS transistor circuit includes an N well 211, a P active region 212, an N active region 213, and a gate 2152. The P active region 212 and the N active region 213 are located on the upper surface of the N well 211. The N well 211 is located in the epitaxial layer 202, and the N well 211 can be formed by performing N-type ion implantation and diffusion on a portion of the epitaxial layer. The P active region 212 and the N active region 213 can be formed by performing P+ ion and N+ ion implantation and diffusion on the N well 211. The gate 2152 is located above the epitaxial side 202, specifically above the N well 211.
[0107] The metal line 214 is electrically connected to the diode doped region 205 , the SPAD electrode contact region 207 , the P active region 209 , the N active region 210 , the P active region 212 , and the N active region 213 .
[0108] The photosensor further includes a gate oxide layer 216 disposed on the epitaxial side 202 .
[0109] The oxide layer 217 is located on the gate oxide layer 216 and covers the gate.
[0110] The first dielectric layer 218 is located on the oxide layer 217 and the diode doped region 205. The first dielectric layer 218 may be silicon dioxide.
[0111] The second dielectric layer 219 is located on the first dielectric layer 218. The second dielectric layer 219 may be silicon nitride.
[0112] The metal line 214 passes through the second dielectric layer 219 , the first dielectric layer 218 , the oxide layer 217 and the gate oxide layer 216 to be electrically connected to the SPAD electrode contact region 207 , the P active region, the N active region and the gate. The metal line 214 passes through the second dielectric layer 219 to be electrically connected to the diode doped region 205 .
[0113] Optionally, the above-mentioned optical sensor may further include an isolation buffer wall (not shown) which is located around the avalanche zone film.
[0114] In another embodiment of the present invention, the buried layer 203 is a P+ buried layer, which is formed by implanting P+ ions into the substrate and diffusing them.
[0115] The avalanche region film is a P-type germanium film, an intrinsic germanium film, a P-type germanium silicon film, an intrinsic germanium silicon film, a P-type GaAs film or a P-type InGaAsP film.
[0116] The diode doped region 205 is used as the negative electrode of the SPAD and is located on the upper surface of the avalanche region film. The diode doped region can be formed by performing N+ ion implantation on the upper surface of the avalanche region film.
[0117] By changing the type of doping ions, the negative electrode of the SPAD can be turned into a positive electrode.
[0118] The SPAD electrode lead-out region is located on both sides of the avalanche region film 204 and on the buried layer 203. The SPAD electrode lead-out region can be formed by performing P-type ion implantation and diffusion (annealing) on the epitaxial layer 202.
[0119] The SPAD electrode contact region is located on the upper surface of the SPAD electrode lead-out region. The SPAD electrode contact region can be formed by performing P+ ion implantation on the upper surface of the SPAD electrode lead-out region. P+ implantation is performed on the exposed substrate of the buried layer region to generate a P+ buried layer.
[0120] The P+ buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the positive electrode of the SPAD.
[0121] also, Fig.21 The silicon-based CMOS transistor circuit and SPAD are illustrated only in unit numbers, but the actual photosensor includes multiple SPADs arranged in an array and multiple silicon-based CMOS transistor circuits, and multiple silicon-based CMOS transistor circuits are combined to drive the SPAD.
[0122] The utility model has the following beneficial effects:
[0123] The utility model adopts silicon-based CMOS technology and grows germanium thin film on the basis of silicon material, uses the characteristics of germanium to produce avalanche diodes, and connects with auxiliary circuits realized by silicon-based CMOS technology in the same plane to achieve all the functions of the sensor on one chip. Since the sensor adopts germanium material, its infrared wavelength can be extended to 1800nm, which greatly expands the application range of SPAD array sensors, while avoiding the use of dual-chip stacking packaging, which greatly improves the yield rate and reliability and reduces the cost.
[0124] If you want to use the physical properties of Ge to make a SPAD array, a simple method is to selectively grow a Ge film directly outside the silicon-based CMOS, but this method has great limitations in the application field:
[0125] 1) The thickness of the Ge film grown by this method is limited. Since SPAD works in the avalanche breakdown region, a thicker film is required to ensure a wider barrier region to ensure that the diode is in an avalanche breakdown state rather than other breakdowns. Therefore, the thickness of this film will be between 2um and 6um. A film of this thickness directly protrudes from the surface of the silicon wafer, forming a large step on the device, which is not conducive to metal wiring, especially multi-layer wiring of CMOS process below 0.25um will be difficult to implement.
[0126] 2) In the CMOS process with a thickness less than 0.25um, the junction depth of the device is relatively shallow. If the Ge film is grown later, it usually needs to go through multiple high temperatures above 800°C, which will affect the process parameters that have been completed in the CMOS process. It is even impossible to manufacture CMOS devices with fine lines.
[0127] In order to fully utilize the advantages of mature silicon-based CMOS in circuits and further expand the infrared wavelength of the sensor, the utility model carves grooves of sufficient depth and area on the silicon-based epitaxial layer, fills the grooves with Ge material or other III-V materials, and then generates SPAD diodes on the Ge material.
[0128] The utility model implants Ge material without affecting the traditional CMOS process, and uses the physical property of Ge material that absorbs infrared light better than silicon to make a SPAD array directly connected to the silicon-based CMOS. The utility model takes advantage of the respective advantages of the two materials, and has greatly improved the performance compared with the all-silicon-based SPAD, especially the application range of infrared wavelengths is greatly expanded. At the same time, it avoids the disadvantages of high cost and low yield caused by multi-chip stacking packaging, and realizes single-chip packaging.
[0129] Although some embodiments of the present invention have been described in this application document, it will be understood by those skilled in the art that these embodiments are only shown as examples. Under the guidance of the present invention, those skilled in the art can think of numerous variations, alternatives and improvements without exceeding the scope of the present invention. The attached claims are intended to define the scope of the present invention and thereby cover methods and structures within the scope of these claims themselves and their equivalents.
Claims
1. A light sensor based on silicon-based CMOS, characterized in that: include: One or more single photon avalanche diodes (SPADs); One or more silicon-based CMOS transistor circuits, wherein the single photon avalanche diode and the CMOS transistor circuit are located in the same plane and are electrically connected.
2. The optical sensor according to claim 1, characterized in that The single photon avalanche diode SPAD comprises: buried layer; an avalanche zone thin film located above the buried layer; A diode doped region, which is located on the upper surface of the avalanche region film; A SPAD electrode lead-out region, which is located above the buried layer and on one side, both sides or all around the avalanche region film; The SPAD electrode contact region is located on the upper surface of the SPAD electrode lead-out region.
3. The optical sensor according to claim 2, characterized in that When the diode doped region is used as the SPAD positive electrode, it is formed by P-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD negative electrode, which are all formed by N-type ion doping; or When the diode doped region is used as the negative electrode of the SPAD, it is formed by N-type ion doping, and the buried layer, the SPAD electrode lead-out region and the SPAD electrode contact region constitute the SPAD positive electrode, all of which are formed by P-type ion doping.
4. The optical sensor according to claim 2, characterized in that The avalanche zone film is an N-type germanium film, a P-type germanium film, an intrinsic germanium film, an N-type germanium silicon film, a P-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, a P-type GaAs film, an N-type InGaAsP film or a P-type InGaAsP film.
5. The optical sensor according to claim 2, characterized in that The SPAD further comprises: An isolation buffer wall is located around the avalanche zone film.
6. The optical sensor according to claim 2, characterized in that The silicon-based CMOS transistor circuit comprises: A silicon-based PMOS transistor circuit comprising: N-well; Gate; A P active region located on the upper surface of the N well; and An N active region located on an upper surface of the N well; and A silicon-based NMOS transistor circuit comprising: P well; Gate; A P active region, which is located on the upper surface of the P well; The N active region is located on the upper surface of the P well.
7. The optical sensor according to claim 6, characterized in that Also includes: substrate; An epitaxial layer is located on the substrate, the single photon avalanche diode is located on the substrate, and the silicon-based CMOS transistor circuit is located in the epitaxial layer.
8. The optical sensor according to claim 7, characterized in that Also includes: A gate oxide layer, which is located above the epitaxial layer and below the gate; an oxide layer, which is located on the gate oxide layer and covers the gate; A first dielectric layer, which is located above the oxide layer and above the positive electrode structure; a second dielectric layer, which is located on the first dielectric layer; The metal wire is electrically connected to the P active region, the N active region, the gate, the diode doped region and the SPAD electrode contact region.