Enabling control circuit of power supply chip and power supply device
By introducing the delay debounce function into the enable control circuit of the power chip, the problem of false triggering of the enable signal is solved, and the stability and reliability of the power chip when switching is achieved.
Patent Information
- Application Number
- CN202420477357.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-12
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-03-12
AI Technical Summary
During the startup and shutdown of the power chip, the main control may be affected by noise or interference signals, resulting in the false triggering of the enable signal, which in turn leads to abnormal operation of the high-frequency power module.
Design an enable control circuit for the power chip to delay dejitter the enable signal starting the power chip to prevent the enable signal from being triggered by mistake. The circuit includes a first resistor, a second resistor, a first control switch and a second control switch, and uses the delay on and off characteristics of these components to achieve delay dejitter of the enable signal.
Through the delay debounce technology, the error triggering of the enable signal is effectively prevented, the stability and reliability of the power chip when switching, and the abnormal operation of the high-frequency power module is avoided.
Smart Images
Figure CN222620897U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of power supplies, in particular to an enabling control circuit of a power supply chip and a power supply device. Background Art
[0002] With the continuous development of power chips, users have higher requirements for the accuracy and reliability of the working process of power chips, especially high-frequency power modules. At present, the startup and shutdown process of power chips is mainly realized by enabling signals. Users will send instructions to the main control through the host computer software according to the specific usage. The main control, as the controller of the power chip, will determine whether it is necessary to output an enable signal to enable the high-frequency power module based on the received instructions, so as to control the normal startup and shutdown of the high-frequency power module. However, in this process, if the main control is affected by noise, interference signals or other uncertain factors, it may cause the enable signal to be triggered incorrectly, resulting in abnormal working process of the high-frequency power module. Utility Model Content
[0003] The purpose of the utility model is to provide an enable control circuit and a power supply device for a power chip, which effectively prevents false triggering of the enable signal by delaying and debouncing the enable signal of the start-up power chip, and provides excellent delay and debouncing performance while controlling the switch enable of the power chip, thereby ensuring the stability and reliability of the power chip when switching.
[0004] In order to solve the above technical problems, the utility model provides an enabling control circuit of a power chip, comprising:
[0005] A first resistor, a first end of which is respectively connected to the power supply and the first end of the first control switch, and a second end of which is respectively connected to the control end of the first control switch and the first end of the second control switch;
[0006] a second resistor, a first end of which is grounded;
[0007] The second control switch has a control end connected to the output end of the controller of the power chip and a second end grounded, and is used to turn on after a preset delay time when the output signal of the controller is an enable signal, and turn on when the output signal of the controller is not an enable signal;
[0008] The second end of the first control switch serves as the output end of the enable control circuit of the power chip, and is respectively connected to the enable end of the power chip and the second end of the second resistor, and is used to be turned on when the second control switch is turned on, and turned off when the second control switch is turned off.
[0009] Optionally, the enable control circuit of the power chip further includes a third resistor, a first end of the third resistor being respectively connected to the second end of the first resistor and the control end of the first control switch, and a second end of the third resistor being connected to the first end of the second control switch.
[0010] Optionally, the enable control circuit of the power chip further includes a fourth resistor, a first end of the fourth resistor is connected to the output end of the controller of the power chip, and a second end of the fourth resistor is connected to the control end of the second control switch.
[0011] Optionally, the enable control circuit of the power chip further includes a fifth resistor, a first end of the fifth resistor is connected to the first preset voltage, and a second end is respectively connected to the first end of the fourth resistor and an output end of the controller of the power chip.
[0012] Optionally, the enable control circuit of the power chip also includes a first capacitor, a first end of the first capacitor is grounded, and a second end is respectively connected to the second end of the fifth resistor, the first end of the fourth resistor and the output end of the controller of the power chip.
[0013] Optionally, the enabling control circuit of the power chip further includes a delay circuit, the input end of the delay circuit is connected to the output end of the controller of the power chip, and the output end is connected to the control end of the second control switch;
[0014] The delay circuit is used to output a delay signal when the output signal of the controller is an enable signal, so that the second control switch is turned on for a preset delay time and then turned off.
[0015] Optionally, the enable control circuit of the power chip further includes a sixth resistor, a first end of the sixth resistor is connected to the output end of the delay circuit, and a second end of the sixth resistor is connected to the control end of the second control switch.
[0016] Optionally, the delay circuit includes a monostable multivibrator, a seventh resistor and a second capacitor, the first reset terminal of the monostable multivibrator is connected to the second preset voltage, the second reset terminal is connected to the second preset voltage, the first input terminal is grounded, the second input terminal is connected to the output terminal of the controller of the power chip, the first output terminal is connected to its own third input terminal, the fourth input terminal is connected to the second preset voltage, the second output terminal is connected to the control terminal of the second control switch, the first configuration terminal is respectively connected to the first end of the seventh resistor, the first end of the second capacitor and the second configuration terminal of itself, the second end of the seventh resistor is connected to the second preset voltage, and the second end of the second capacitor is grounded.
[0017] Optionally, the delay circuit also includes an eighth resistor and a ninth resistor, the first end of the eighth resistor is connected to the second preset voltage, and the second end is connected to the first reset end of the monostable multivibrator, the first end of the ninth resistor is connected to the second preset voltage, and the second end is connected to the second reset end of the monostable multivibrator.
[0018] In order to solve the above technical problems, the utility model also provides a power supply device, including a power supply chip, a controller of the power supply chip and an enable control circuit of the power supply chip as described above, wherein the input end of the enable control circuit of the power supply chip is connected to the output end of the controller of the power supply chip, and the output end is connected to the enable end of the power supply chip.
[0019] The utility model provides an enable control circuit of a power chip, comprising a first resistor, a second resistor, a first control switch and a second control switch. When the power chip needs to be started, the output end of the controller outputs an enable signal. After receiving the enable signal, the control end of the second control switch will first maintain an on state for a preset delay time, delay and de-jitter the enable signal, and then shut down based on the enable signal. At the same time, the first control switch will also be turned on for a preset delay time and then turned off, thereby controlling the enable end of the power chip to be enabled; when the power chip needs to stop working, the output end of the controller will not output an enable signal, and the first control switch and the second control switch will both remain in an on state to avoid controlling the enable end of the power chip to be enabled; by delaying and de-jittering the enable signal of the start-up power chip, the enable signal can be effectively prevented from being falsely triggered, and while controlling the switch enable of the power chip, excellent delay and de-jitter performance is provided, thereby ensuring the stability and reliability of the power chip when switching.
[0020] The utility model also provides a power supply device, which has the same beneficial effects as the enabling control circuit of the power supply chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0022] Figure 1 A schematic diagram of the structure of an enabling control circuit of a power chip provided by the utility model;
[0023] Figure 2 A schematic diagram of the structure of an enable control circuit of another power chip provided by the utility model;
[0024] Figure 3 A structural schematic diagram of a delay circuit provided by the utility model;
[0025] Figure 4 The present invention is a schematic structural diagram of a power supply device provided by the utility model. DETAILED DESCRIPTION
[0026] The core of the utility model is to provide an enable control circuit and a power supply device for a power chip, which effectively prevents false triggering of the enable signal by delaying and debouncing the enable signal of the start-up power chip, and provides excellent delay and debouncing performance while controlling the switch enable of the power chip, thereby ensuring the stability and reliability of the power chip when switching.
[0027] In order to make the purpose, technical solution and advantages of the embodiment of the utility model clearer, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0028] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an enabling control circuit of a power chip provided by the utility model; please refer to Figure 2 , Figure 2 A schematic diagram of the structure of another power chip enable control circuit provided by the utility model; GND represents grounding; In order to solve the above technical problems, the utility model provides an enable control circuit of a power chip, including:
[0029] A first resistor R1, a first end of which is respectively connected to the power supply and the first end of the first control switch Q1, and a second end of which is respectively connected to the control end of the first control switch Q1 and the first end of the second control switch Q2;
[0030] A second resistor R2, a first end of which is grounded;
[0031] A second control switch Q2, a control end of which is connected to the output end of the controller 1 of the power chip, and a second end of which is grounded, and is used to turn on after a preset delay time when the output signal of the controller 1 is an enable signal, and turn on when the output signal of the controller 1 is not an enable signal;
[0032] The first control switch Q1 has a second end serving as an output end of an enable control circuit of the power chip, and is respectively connected to the enable end of the power chip and the second end of the second resistor R2, and is used to be turned on when the second control switch Q2 is turned on, and turned off when the second control switch Q2 is turned off.
[0033] Specifically, taking the low-level enabled power chip, that is, the normal operation of the power chip when the enable end of the power chip receives a low level as an example, when the power chip needs to be started, the controller 1 of the power chip will output a low-level enable signal to the control end of the second control switch Q2, and the second control switch Q2 will first be turned on for a preset delay time. After the preset delay time, if the enable signal output by the controller 1 still exists, the second control switch Q2 will be turned off, and then the first control switch Q1 will be turned off, so that the second end of the first control switch Q1, that is, the output end of the enable control circuit of the power chip, is grounded through the second resistor R2, and the enable control circuit outputs a low level to the power chip. The enable end of the chip is connected to the enable end of the chip, thereby enabling the power chip and controlling the power chip to work normally; when the power chip does not need to be started or needs to be turned off, the controller 1 of the power chip will not output an enable signal, and usually a standby signal opposite to the enable signal will be output to the control end of the second control switch Q2. The second control switch Q2 will remain in the on state under the control of the standby signal, and the first control switch Q1 will also remain in the on state, so that the output end of the enable control circuit of the power chip is connected to the power supply through the turned-on first control switch Q1, and the enable control circuit outputs a high level to the enable end of the power chip, controlling the power chip to remain in the standby state.
[0034] In practical applications, the first control switch Q1 and the second control switch Q2 generally remain in the on state in the initial state. After the controller 1 outputs the enable signal, the second control switch Q2 and the first control switch Q1 will first delay and maintain the on state for a preset delay time before being turned off; the first resistor R1 is set between the control end and the first end of the first control switch Q1 as a pull-up resistor to ensure the stable operation of the first control switch Q1; the second resistor R2 is connected between the second end of the first control switch Q1 and the ground to play a voltage divider role to avoid the second end of the first control switch Q1 being directly grounded, thereby improving the safety and reliability of the entire circuit. The present application does not make any special restrictions on the specific types and implementation methods of the first control switch Q1, the second control switch Q2, the first resistor R1, the second resistor R2, and the power supply. The first control switch Q1 and the second control switch Q2 can be implemented by power electronic devices such as triodes, MOS tubes (Metal Oxide Semiconductor Field Effect Transistors) or other types of controllable switches. The first control switch Q1 and the second control switch Q2 can be implemented by the same type of switching devices to ensure the accuracy of the entire circuit, or they can be implemented by different types of switching devices according to actual needs; the first resistor R1 and the second resistor R2 can be implemented in the form of fixed resistors or variable resistors, or they can be implemented by other types of impedance modules such as inductors. The power supply can be implemented by a preset fixed voltage power supply, or it can directly reuse the fixed reference voltage in the chip according to the situation of the power supply chip.
[0035] It can be understood that the conduction or shutdown of the second control switch Q2 and the first control switch Q1 depends on the control signal output by the controller 1 of the power chip to the control end of the second control switch Q2. At the same time, the delayed conduction process of the second control switch Q2 and the first control switch Q1 in the control process of starting the power chip can also be achieved by adding a setting delay signal; the specific type and implementation method of the controller 1 of the power chip are not particularly limited in this application. There are many options for the specific implementation method of the delay process of the enable signal in the process of starting the power chip. It can be achieved by adding a delay signal connected to the control end of the second control switch Q2. The application does not make any special restrictions here.
[0036] It should be noted that when the enable signal of the power chip is at a high level, the working principle of the enable control circuit of the power chip is similar to the working principle when the enable signal of the power chip is at a low level. Figure 1 and Figure 2The circuit structures shown are symmetrical to each other. When the controller 1 outputs an enable signal, the second control switch Q2 can be turned off for a preset delay time and then turned on to delay and de-bounce the enable signal; or only the connection relationship between the first control switch Q1, the second control switch Q2 and the power supply and the ground can be adjusted. When the second control switch Q2 and the first control switch Q1 are turned off, the enable control circuit of the power chip outputs a high level to the enable end of the power chip, thereby controlling the normal operation of the voltage chip. The specific working process when the enable signal is at a high level and the like will not be described in detail in the utility model.
[0037] It is not difficult to understand that the power chip enable control circuit provided by the utility model is suitable for various power chips or power circuits, especially high-frequency power chips or circuits, and provides a safe and stable high-precision delay debouncing circuit for controlling the enablement of high-frequency power supply. It can provide excellent delay debouncing performance while controlling the high-frequency power circuit switch (on, i.e., the normal operation of the power circuit, off, i.e., the standby state of the power circuit), prevent false triggering of the high-frequency power circuit, and ensure the stability and reliability of the high-frequency power supply. The delay accuracy is high. At the same time, when enabling delay debouncing, only the on state is delayed and debouncing is performed, while the off state is normally closed, which is safer and more reliable.
[0038] As a specific embodiment, when the power chip is a high-frequency power chip, the enable signal output by the controller 1 needs to be connected to the SD pin of the high-frequency power chip, such as Figure 2 As shown, the first control switch Q1 uses a PNP transistor, whose emitter is connected to the 5.1V reference voltage output by the power pin of the high-frequency power chip, and the reference voltage generated by the power pin of the high-frequency power chip is directly used as the power supply of the enable control circuit, which further simplifies the circuit structure of the entire power circuit and saves cost and volume; the collector of the first control switch Q1 is connected to the SD pin of the high-frequency power chip and connected to the ground through the second resistor R2, and the base is connected to the 5.1V reference voltage (Vref) output by the power pin of the high-frequency power chip through the first resistor R1. The SD pin of the high-frequency power chip is also the shutdown pin. When the SD pin is connected to a high level, the high-frequency power chip is in standby mode. When the SD pin is connected to the ground, the high-frequency power chip can work normally. The second control switch Q2 adopts an NPN transistor, whose collector is connected to the base of the first control switch Q1 through the third resistor R3, and the emitter is grounded. The base of the second control switch Q2 is connected to the control signal output by the controller 1 through the fourth resistor R4, and then connected to the 5V DC through the fifth resistor R5. At the same time, the base of the second control switch Q2 is connected to the delay signal through the sixth resistor R6.
[0039] Specifically, when the upper computer software sends a standby signal of the high-frequency power chip to the controller 1, the controller 1 also outputs a standby signal to the enable control circuit, the control signal is suspended, and the base of the second control switch Q2 is pulled up to a high level of 5V through the fifth resistor R5. At this time, the first control switch Q1 and the second control switch Q2 both operate in the saturation region and remain in the on state. At this time, the collector of the first control switch Q1 is at a high level, and the collector of the first control switch Q1 is connected to the SD pin of the high-frequency power chip. Therefore, the SD pin of the high-frequency power chip is also at a high level, so that the high-frequency power supply is in a standby state. When the upper computer sends an enable signal to the controller 1, the controller 1 also outputs an enable signal to the enable control circuit, and the control signal is pulled to the ground. At this time, the delay signal will output a high-level pulse, and the base of the second control switch Q2 will be pulled high by the delay signal. After the set delay time, the delay signal will return to a low level, and the corresponding base of the second control switch Q2 will also become a low level, causing the second control switch Q2 and the first control switch Q1 to work in the cut-off area and become the off state; at this time, the output signal is connected to the ground through the second resistor R2, so that the high-frequency power chip works normally.
[0040] The utility model provides an enable control circuit of a power chip, comprising a first resistor R1, a second resistor R2, a first control switch Q1 and a second control switch Q2. When the power chip needs to be started, the output end of the controller 1 outputs an enable signal. After receiving the enable signal, the control end of the second control switch Q2 will first maintain an on state for a preset delay time, delay and de-jitter the enable signal, and then shut down based on the enable signal. At the same time, the first control switch Q1 will also be turned on for a preset delay time and then turned off, thereby controlling the enable end of the power chip to be enabled; when the power chip needs to stop working, the output end of the controller 1 will not output an enable signal, and the first control switch Q1 and the second control switch Q2 will both remain in an on state to avoid enabling the enable end of the power chip; by delaying and de-jittering the enable signal of the start-up power chip, the enable signal can be effectively prevented from being falsely triggered, and while controlling the switch enable of the power chip, excellent delay and de-jitter performance is provided, thereby ensuring the stability and reliability of the power chip when switching.
[0041] Based on the above embodiments:
[0042] As an optional embodiment, the enable control circuit of the power chip further includes a third resistor R3, a first end of the third resistor R3 is respectively connected to the second end of the first resistor R1 and the control end of the first control switch Q1, and a second end is connected to the first end of the second control switch Q2.
[0043] It is not difficult to understand that a third resistor R3 may be further provided between the control end of the first control switch Q1 and the first end of the second control switch Q2 to avoid direct connection between the control end of the first control switch Q1 and the first end of the second control switch Q2. The third resistor R3 and the first resistor R1 cooperate with each other to play a role of voltage division, thereby avoiding malfunction of the first control switch Q1 and the second control switch Q2, and further improving the stability and reliability of the operation process of the first control switch Q1 and the second control switch Q2. The specific type and implementation method of the third resistor R3 are not particularly limited in this application.
[0044] Specifically, a third resistor R3 is further added between the control end of the first control switch Q1 and the first end of the second control switch Q2 to ensure the stability and reliability of the operation process of the first control switch Q1 and the second control switch Q2 to avoid malfunction caused by direct connection. The components used are easy to implement, low cost, small size, and simple circuit structure, which is conducive to the simple implementation of the enabling control circuit.
[0045] As an optional embodiment, the enable control circuit of the power chip further includes a fourth resistor R4, a first end of the fourth resistor R4 is connected to the output end of the controller 1 of the power chip, and a second end of the fourth resistor R4 is connected to the control end of the second control switch Q2.
[0046] It is not difficult to understand that a fourth resistor R4 may be further provided between the output end of the controller 1 of the power chip and the control end of the second control switch Q2. The fourth resistor R4 may play the role of current limiting and voltage dividing, thereby avoiding a large voltage impact on the control end of the second control switch Q2 caused by the control signal output by the controller 1, thereby ensuring the safety and reliability of the second control switch Q2 and ensuring the accurate operation of the second control switch Q2. The specific type and implementation method of the fourth resistor R4 are not particularly limited in this application.
[0047] Specifically, a fourth resistor R4 is further added between the output end of the controller 1 of the power chip and the control end of the second control switch Q2 to ensure the accuracy and reliability of the operation process of the second control switch Q2, avoid voltage shock caused by direct connection, and improve the safety and reliability of the second control switch Q2 and the entire enabling control circuit. The components used are easy to implement, low cost, small size, and simple circuit structure, which is conducive to the simple implementation of the enabling control circuit.
[0048] As an optional embodiment, the enable control circuit of the power chip also includes a fifth resistor R5, a first end of the fifth resistor R5 is connected to the first preset voltage, and a second end is respectively connected to the first end of the fourth resistor R4 and the output end of the controller 1 of the power chip.
[0049] It is not difficult to understand that a fifth resistor R5 can be further provided as a pull-up resistor at the output end of the controller 1 of the power chip. The fifth resistor R5 as a pull-up resistor can improve the stability of the entire circuit, avoid malfunction of the second control switch Q2, and at the same time improve the driving capability of the output end of the controller 1 of the power chip, ensure the accurate control of the second control switch Q2 by the control signal, and also play a role in current limiting, ensuring the safety and reliability of the second control switch Q2; the specific type and implementation method of the fifth resistor R5 are not particularly limited in this application, and the specific value and implementation method of the first preset voltage are not particularly limited in this application. Considering the low-voltage working environment of the chip circuit, the first preset voltage can be directly implemented using a fixed voltage of 5V.
[0050] Specifically, a fifth resistor R5 connected to the output end of the controller 1 of the power chip is further added to serve as a pull-up resistor, so as to further ensure the accuracy and reliability of the operation process of the second control switch Q2, and improve the safety and reliability of the second control switch Q2 and the entire enabling control circuit. The components used are easy to implement, low in cost, small in size, and simple in circuit structure, which is conducive to the simple implementation of the enabling control circuit.
[0051] As an optional embodiment, the enable control circuit of the power chip also includes a first capacitor C1, a first end of the first capacitor C1 is grounded, and a second end is respectively connected to the second end of the fifth resistor R5, the first end of the fourth resistor R4 and the output end of the controller 1 of the power chip.
[0052] It is not difficult to understand that a first capacitor C1 can be further provided as a pull-up capacitor at the output end of the controller 1 of the power chip. The first capacitor C1 as a pull-up capacitor can keep the circuit in a stable state and avoid false triggering. When there is a high-frequency interference signal, it can be discharged through the pull-up capacitor, thereby improving the anti-interference ability of the entire circuit and ensuring the accurate control of the second control switch Q2 by the control signal. At the same time, it can also play the role of filtering and stabilizing voltage, thereby further improving the accuracy and reliability of the operation process of the second control switch Q2. The specific type and implementation method of the first capacitor C1 are not particularly limited in this application.
[0053] Specifically, a first capacitor C1 connected to the output end of the controller 1 of the power chip is further added as a pull-up capacitor to further ensure the accuracy and reliability of the action process of the second control switch Q2, improve the safety and reliability of the second control switch Q2 and the entire enabling control circuit, and the components used are easy to implement, low cost, small size, and simple circuit structure, which is conducive to the simple implementation of the enabling control circuit.
[0054] As an optional embodiment, the enabling control circuit of the power chip further includes a delay circuit, the input end of the delay circuit is connected to the output end of the controller 1 of the power chip, and the output end is connected to the control end of the second control switch Q2;
[0055] The delay circuit is used to output a delay signal when the output signal of the controller 1 is an enable signal, so that the second control switch Q2 is turned on for a preset delay time and then turned off.
[0056] It is not difficult to understand that the second control switch Q2 and the first control switch Q1 require a certain delay control when receiving the enable signal, so a delay circuit connected to the control end of the second control switch Q2 can be added to generate a delay signal, so that the action process of the second control switch Q2 is controlled by the control signal output by the controller 1 and the delay signal output by the delay circuit at the same time, and because the delay signal only needs to be generated when the controller 1 outputs the enable signal, the input end of the delay circuit needs to be connected to the output end of the controller 1 of the power chip, and the delay signal is generated accordingly according to whether the output of the controller 1 is an enable signal. The specific type and implementation method of the delay circuit are not particularly limited in this application.
[0057] Specifically, a delay signal required by the second control switch Q2 in the process of starting the power chip can be generated by further adding a delay circuit, and the delay signal is only generated when the controller 1 inputs an enable signal. When the power chip needs to be turned on, the delay signal and the enable signal act on the control end of the second control switch Q2 at the same time, thereby realizing accurate control of the delayed shutdown process of the second control signal and ensuring the delayed de-bouncing process of the enable signal.
[0058] As an optional embodiment, the enable control circuit of the power chip further includes a sixth resistor R6, a first end of the sixth resistor R6 is connected to the output end of the delay circuit, and a second end of the sixth resistor R6 is connected to the control end of the second control switch Q2.
[0059] It is not difficult to understand that a sixth resistor R6 may be further provided between the output end of the delay circuit and the control end of the second control switch Q2. The sixth resistor R6 may play the role of current limiting and voltage dividing, thereby avoiding a large voltage impact on the control end of the second control switch Q2 caused by the delay signal output by the delay circuit, thereby ensuring the safety and reliability of the second control switch Q2 and ensuring the accurate operation of the second control switch Q2. The specific type and implementation method of the sixth resistor R6 are not particularly limited in this application.
[0060] Specifically, a sixth resistor R6 is further added between the output end of the delay circuit and the control end of the second control switch Q2 to ensure the accuracy and reliability of the operation process of the second control switch Q2, avoid voltage shock caused by direct connection, and improve the safety and reliability of the second control switch Q2 and the entire enabling control circuit. The components used are easy to implement, low in cost, small in size, and simple in circuit structure, which is conducive to the simple implementation of the enabling control circuit.
[0061] Please refer to Figure 3 , Figure 3 A structural schematic diagram of a delay circuit provided by the utility model; as an optional embodiment, the delay circuit includes a monostable multivibrator, a seventh resistor R7 and a second capacitor C2, a first reset terminal of the monostable multivibrator is connected to a second preset voltage, a second reset terminal is connected to the second preset voltage, a first input terminal is grounded, a second input terminal is connected to an output terminal of a controller 1 of a power chip, a first output terminal is connected to a third input terminal of the monostable multivibrator, a fourth input terminal is connected to the second preset voltage, a second output terminal is connected to a control terminal of a second control switch Q2, a first configuration terminal is respectively connected to a first terminal of the seventh resistor R7, a first terminal of the second capacitor C2 and a second configuration terminal of the monostable multivibrator, a second terminal of the seventh resistor R7 is connected to the second preset voltage, and a second terminal of the second capacitor C2 is grounded.
[0062] Considering that the delay circuit only needs to generate a delay signal when the controller 1 outputs an enable signal, and does not need to generate a delay signal when the controller 1 outputs a standby signal, a monostable multivibrator can be used to generate this delay signal. The specific circuit structure of the monostable multivibrator and its peripheral circuit is as follows: Figure 3 As shown, the truth table of the monostable multivibrator is shown in Table 1. The specific types and implementation methods of the monostable multivibrator, the seventh resistor R7 and the second capacitor C2 are not particularly limited in this application, and the specific value and implementation method of the second preset voltage are not particularly limited in this application. Considering the low-voltage working environment of the chip circuit, the second preset voltage can be directly implemented by a fixed voltage of 5V.
[0063] Table 1 Truth table of monostable multivibrator
[0064]
[0065] H=HighLevel,L=Low Level,↑=Transition from Low to High,
[0066] , =Transition fromHigh toLow One HighLevelPulse,
[0067] OneLowLevel Pulse,×=Irrelevant.
[0068] Specifically, Figure 3 As shown, the 3rd pin of the monostable multivibrator is used as the first reset terminal, connected to the second preset voltage of 5V through the eighth resistor R8, the 4th pin is used as the first input terminal, connected to the ground through the tenth resistor R10, the 5th pin is used as the second input terminal, connected to the control signal output by the controller 1 through the eleventh resistor R11, and the 6th pin is used as the first output terminal. The 13th pin is used as the second reset terminal, connected to the second preset voltage of 5V through the ninth resistor R9, the 12th pin is used as the third input terminal, connected to the 6th pin, the 11th pin is used as the fourth input terminal, connected to the second preset voltage of 5V through the twelfth resistor R12, and the 10th pin is used as the second output terminal to output the delay signal. Vcc, that is, the 16th pin, is used as the power supply terminal of the monostable multivibrator, which can be directly connected to the preset power supply, or directly reuse the second preset voltage to realize power supply; the 14th pin is used as the first configuration terminal, and the 15th pin is used as the second configuration terminal.
[0069] Among them, the first reset terminal and the second reset terminal of the monostable multivibrator both maintain a high level state, the first input terminal maintains a low level state, and the fourth input terminal maintains a high level state. The output signal of the first output terminal depends on the first input terminal and the second input terminal, and the output signal of the second output terminal depends on the third input terminal and the fourth input terminal. When the power chip needs to standby, the second input terminal receives a high level control signal. At this time, the first input terminal is low level and the second input terminal is high level. According to the third row of the truth table, the first output terminal will output a low level. Correspondingly, the third input terminal is also low level at this time, and because the fourth input terminal is high level, according to the third row of the truth table, It can be seen from row 3 that the second output terminal will also output a low level, which will not affect the control process of the second control switch Q2 by the standby signal output by the controller 1; when the upper computer sends an enable signal, the control signal received by the second input terminal is pulled to the ground, and the second input terminal generates a falling edge signal from high to low. According to row 4 of the truth table, the first output terminal will output a high level pulse signal, so the third input terminal will change from low to high to generate a rising edge signal. According to row 5 of the truth table, the second output terminal will output a high level pulse as a delay signal to the base of the second control switch Q2, so that the second control switch Q2 is first delayed for a preset delay time.
[0070] It is not difficult to understand that the pulse width of the high-level pulse output by the second output terminal is also the preset delay time, which is determined by the resistance and capacitance of the seventh resistor R7 and the second capacitor C2 connected to the second configuration terminal of the monostable multivibrator, and the delay time τ=(0.7)R7C2, where R7 is the resistance of the seventh resistor R7, and C2 is the capacitance of the second capacitor C2. As a specific embodiment, the seventh resistor R7 can use a 1M resistor, and the second capacitor C2 uses a 0.33uF capacitor. At this time, the delay time τ=0.7*1000K*0.33uF=231ms. The delay time can be changed according to actual needs by adjusting the resistance of the seventh resistor R7 and the capacitance of the second capacitor C2 to achieve the best delay de-jittering effect.
[0071] Specifically, the delay circuit can be implemented using a monostable multivibrator and its peripheral circuits. The first control switch Q1 and the second control switch Q2 can use a triode. The delay circuit constructed by using a triode for enabling switch and a monostable multivibrator enables the entire enabling control circuit to have the characteristics of fast switching speed, high delay accuracy, safety and reliability. In the delay circuit composed of a monostable multivibrator, the delay signal will automatically recover to a steady state when the enabling signal is not received. The power chip will perform delay debouncing when starting, but not when shutting down. The reliability of the entire delay circuit is good and the delay accuracy is high. It is also possible to further obtain the precise required delay time by simply adjusting the configured resistance and capacitance values, which is highly flexible and portable.
[0072] As an optional embodiment, the delay circuit also includes an eighth resistor R8 and a ninth resistor R9, the first end of the eighth resistor R8 is connected to the second preset voltage, and the second end is connected to the first reset end of the monostable multivibrator, and the first end of the ninth resistor R9 is connected to the second preset voltage, and the second end is connected to the second reset end of the monostable multivibrator.
[0073] It is not difficult to understand that an eighth resistor R8 may be added between the first reset terminal and the second preset voltage, and a ninth resistor R9 may be added between the second reset terminal and the second preset voltage. The eighth resistor R8 and the ninth resistor R9 may play the role of current limiting and voltage dividing, avoiding direct connection between the second preset voltage and the first reset terminal and the second reset terminal, thereby ensuring the safety of the pins of the monostable multivibrator. The specific types and implementation methods of the eighth resistor R8 and the ninth resistor R9 are not particularly limited in this application.
[0074] Further, the delay circuit also includes a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12, the first end of the tenth resistor R10 is grounded, and the second end is connected to the first input end of the monostable multivibrator, the first end of the eleventh resistor R11 is connected to the output end of the controller 1 of the power chip, and the second end is connected to the second input end of the monostable multivibrator, the first end of the twelfth resistor R12 is connected to the second preset voltage, and the second end is connected to the fourth input end of the monostable multivibrator, the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 can all play the role of current limiting and voltage dividing, avoiding that each pin of the monostable multivibrator is directly grounded, directly connected to the second preset voltage or directly connected to the control signal output by the controller 1, and further improving the safety and reliability of the pins of the monostable multivibrator. The specific types and implementation methods of the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 are not particularly limited in this application.
[0075] It can be understood that pin 1 and pin 2 of the monostable multivibrator are also configuration terminals, pin 1 is directly grounded and connected to one end of capacitor C3, the other end of capacitor C3 is respectively connected to pin 2 and one end of resistor R13, and the other end of resistor R13 is connected to the second preset voltage.
[0076] Specifically, further increasing the resistor connected to the pin of the monostable multivibrator can further ensure the safety of the pin of the monostable multivibrator, improve the safety and reliability of the delay circuit and the entire enable control circuit, and the components used are easy to implement, low cost, small size, and simple circuit structure, which is conducive to the simple implementation of the enable control circuit, further improves the peripheral circuit structure of the monostable multivibrator, and is conducive to the application and promotion of the enable control circuit.
[0077] Please refer to Figure 4 , Figure 4 A schematic diagram of the structure of a power supply device provided by the utility model. To solve the above technical problems, the utility model further provides a power supply device, comprising a power supply chip 11, a controller 1 of the power supply chip and an enable control circuit 12 of the power supply chip as described above, wherein the input end of the enable control circuit 12 of the power supply chip is connected to the output end of the controller 1 of the power supply chip, and the output end is connected to the enable end of the power supply chip 11.
[0078] For an introduction to a power supply device provided in the present application, please refer to the embodiment of the enable control circuit of the above-mentioned power supply chip, and the present application will not go into details here.
[0079] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.
[0080] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.
[0081] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An enabling control circuit of a power chip, characterized in that: include: A first resistor, a first end of which is respectively connected to the power supply and the first end of the first control switch, and a second end of which is respectively connected to the control end of the first control switch and the first end of the second control switch; a second resistor, a first end of which is grounded; The second control switch has a control end connected to the output end of the controller of the power chip and a second end grounded, and is used to turn on after a preset delay time when the output signal of the controller is an enable signal, and turn on when the output signal of the controller is not an enable signal; The second end of the first control switch serves as the output end of the enable control circuit of the power chip, and is respectively connected to the enable end of the power chip and the second end of the second resistor, and is used to be turned on when the second control switch is turned on, and turned off when the second control switch is turned off.
2. The enabling control circuit of the power chip according to claim 1, characterized in that: The enable control circuit of the power chip further includes a third resistor, a first end of the third resistor is respectively connected to the second end of the first resistor and the control end of the first control switch, and a second end of the third resistor is connected to the first end of the second control switch.
3. The enabling control circuit of the power chip according to claim 1, characterized in that: The enable control circuit of the power chip further includes a fourth resistor, a first end of the fourth resistor is connected to the output end of the controller of the power chip, and a second end of the fourth resistor is connected to the control end of the second control switch.
4. The enabling control circuit of the power chip according to claim 3, characterized in that: The enable control circuit of the power chip further includes a fifth resistor, a first end of the fifth resistor is connected to the first preset voltage, and a second end is respectively connected to the first end of the fourth resistor and an output end of the controller of the power chip.
5. The enabling control circuit of the power chip according to claim 4, characterized in that: The enabling control circuit of the power chip further includes a first capacitor, a first end of which is grounded, and a second end of which is respectively connected to the second end of the fifth resistor, the first end of the fourth resistor, and the output end of the controller of the power chip.
6. The enabling control circuit of the power chip according to any one of claims 1 to 5, characterized in that: The enabling control circuit of the power chip further includes a delay circuit, wherein an input end of the delay circuit is connected to an output end of the controller of the power chip, and an output end of the delay circuit is connected to a control end of the second control switch; The delay circuit is used to output a delay signal when the output signal of the controller is an enable signal, so that the second control switch is turned on for a preset delay time and then turned off.
7. The enabling control circuit of the power chip according to claim 6, characterized in that: The enable control circuit of the power chip further includes a sixth resistor, a first end of the sixth resistor is connected to the output end of the delay circuit, and a second end of the sixth resistor is connected to the control end of the second control switch.
8. The enabling control circuit of the power chip according to claim 6, characterized in that: The delay circuit includes a monostable multivibrator, a seventh resistor and a second capacitor, wherein the first reset terminal of the monostable multivibrator is connected to the second preset voltage, the second reset terminal is connected to the second preset voltage, the first input terminal is grounded, the second input terminal is connected to the output terminal of the controller of the power chip, the first output terminal is connected to the third input terminal of the monostable multivibrator, the fourth input terminal is connected to the second preset voltage, the second output terminal is connected to the control terminal of the second control switch, the first configuration terminal is respectively connected to the first terminal of the seventh resistor, the first terminal of the second capacitor and the second configuration terminal of the monostable multivibrator, the second terminal of the seventh resistor is connected to the second preset voltage, and the second terminal of the second capacitor is grounded.
9. The enabling control circuit of the power chip according to claim 8, characterized in that: The delay circuit also includes an eighth resistor and a ninth resistor, wherein a first end of the eighth resistor is connected to the second preset voltage, and a second end is connected to the first reset end of the monostable multivibrator, and a first end of the ninth resistor is connected to the second preset voltage, and a second end is connected to the second reset end of the monostable multivibrator.
10. A power supply device, characterized in that: It comprises a power chip, a controller of the power chip and an enable control circuit of the power chip as described in any one of claims 1 to 9, wherein the input end of the enable control circuit of the power chip is connected to the output end of the controller of the power chip, and the output end is connected to the enable end of the power chip.