Clock module for data link communication processing device

Abstract

The utility model relates to the technical field of signal processing, in particular to a clock module for a data link communication processing device, which comprises a clock selection circuit, a first clock circuit and a second clock circuit. The clock selection circuit is electrically connected with the FPGA circuit, the first clock circuit and the second clock circuit respectively; the first clock circuit is connected with the data receiving circuit, the second clock circuit is connected with the data transmitting circuit, the clock selection circuit is connected with a plurality of clock sources, including the first clock circuit and the second clock circuit, so that the clock module can select proper clock signals from different clock sources; and the data is distributed to the data receiving and transmitting circuit according to needs, so that the flexibility and adaptability of the system are improved, the clock domain crossing problem is avoided, and the performance of the data link communication processing module is enhanced.

Description

Technical Field

[0001] The utility model relates to the technical field of signal processing, in particular to a clock module used for a data link communication processing device. Background Art

[0002] With the rapid development and widespread application of mobile communication technology, the demand for communication between mobile terminals and base stations is growing. Mobile communication equipment needs to process complex communication signals, perform efficient modulation and demodulation, and perform spectrum management and access control to ensure the normal operation of the entire system and improve user experience. As a core component in the mobile communication system, the data link communication processing module plays a vital role.

[0003] Currently, there is a data link communication processing module that uses the FPGA chip XC7Z045 as the core motherboard. As the core motherboard, this chip is connected to the data receiving circuit and the data sending circuit respectively. If a single clock is used in the traditional way, the receiving and sending circuits will not be able to independently select the frequency that best suits their modules, resulting in performance degradation. In addition, when using a single clock domain, since each clock domain has its own frequency and phase, it is difficult to avoid the clock domain crossing problem, which leads to reduced data transmission efficiency. Utility Model Content

[0004] The utility model aims to solve the problem that the prior art uses a single clock module to provide a clock for a data link communication processing module of an XC7Z045 core motherboard, which results in performance degradation and poor data transmission effect.

[0005] The utility model is realized by the following technical solutions:

[0006] A clock module for a data link communication processing device comprises a clock selection circuit, a first clock circuit and a second clock circuit; the clock selection circuit is electrically connected to an FPGA circuit, a first clock circuit and a second clock circuit respectively; the first clock circuit is connected to a data receiving circuit, and the second clock circuit is connected to a data sending circuit.

[0007] Furthermore, it also includes an oscillation circuit, which is electrically connected to the clock selection circuit.

[0008] Furthermore, it also includes a differential clock circuit, and the differential clock circuit is connected to the clock selection circuit.

[0009] Furthermore, the FPGA circuit includes a main control chip, and the model of the main control chip is XC7Z045.

[0010] Furthermore, the clock selection circuit includes a clock selection chip U1, the model of the clock selection chip U1 is 8305AGILF, pin 7 of the clock selection chip U1 is connected to the B13_L10_N pin of the main control chip, pin 16 of the clock selection chip U1 is connected to the first clock circuit, pin 14 of the clock selection chip is connected to the second clock circuit, pin 12 of the clock selection chip is connected to the B13_L1 pin of the main control chip, pins 5 and 6 of the clock selection chip are respectively connected to the differential clock circuit, and pin 8 of the clock selection chip is connected to the oscillation circuit.

[0011] Furthermore, the first clock circuit includes a clock chip U2, the model of the clock chip U2 is ADF4350BCPZ, the pin 29 of the clock chip U2 is connected to the pin 16 of the clock selection chip U1, the pin 12 of the clock chip U2 is connected to the data receiving circuit, and the pin 13 of the clock chip U2 is connected to the data receiving circuit.

[0012] Furthermore, the second clock circuit includes a clock chip U3, the model of the clock chip U3 is ADF4350BCPZ, the pin 29 of the clock chip U3 is connected to the pin 14 of the clock selection chip U1, the pin 12 of the clock chip U3 is connected to the data sending circuit, and the pin 13 of the clock chip U3 is connected to the data sending circuit.

[0013] Furthermore, the data receiving circuit includes an analog-to-digital conversion chip U4, the model of the analog-to-digital conversion chip U4 is AD9265BCPZ, pin 12 of the clock chip U2 is connected to pin 2 of the analog-to-digital conversion chip U4, and pin 13 of the clock chip U2 is connected to pin 3 of the analog-to-digital conversion chip U4.

[0014] Furthermore, the data sending circuit includes a digital-to-analog conversion chip U5, the model of the digital-to-analog conversion chip U5 is AD9779A, the pin 12 of the clock chip U3 is connected to the pin 5 of the digital-to-analog conversion chip U5, and the pin 13 of the clock chip U3 is connected to the pin 6 of the digital-to-analog conversion chip U5.

[0015] Beneficial effects of the utility model:

[0016] (1) The clock module for a data link communication processing device proposed in the utility model connects multiple clock sources through a clock selection circuit, including a first clock circuit and a second clock circuit, so that the clock module can select a suitable clock signal from different clock sources and distribute it to the data receiving and sending circuits as needed, thereby improving the flexibility and adaptability of the system, avoiding the problem of clock domain crossing, and enhancing the performance of the data link communication processing module;

[0017] (2) The clock module for a data link communication processing device proposed in the utility model provides a stable reference clock signal through an oscillation circuit, and protects and stabilizes the transmission of the clock signal through a differential clock circuit and a filter circuit, thereby ensuring the stability and reliability of the clock signal, reducing the timing error and jitter in the clock signal transmission process, and thus improving the accuracy and stability of data transmission;

[0018] (3) The utility model proposes a clock module for a data link communication processing device. A filtering and voltage stabilizing network is used in the clock circuit. The filtering and voltage stabilizing network composed of capacitors and resistors ensures the cleanliness and stability of the clock signal, reduces power supply noise and high-frequency interference, provides a good working environment, and ensures the quality and stability of the clock signal.

[0019] (4) The utility model proposes a clock module for a data link communication processing device, which uses a transient voltage suppressor to protect the differential signal line, prevents electrostatic discharge (ESD) and transient voltage from damaging the clock signal, improves the reliability and stability of the system, and reduces the impact of external interference on the clock signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 This is a system block diagram of a clock module for a data link communication processing device proposed by the utility model;

[0022] Figure 2 This is a schematic diagram of a clock selection circuit for a clock module of a data link communication processing device proposed by the utility model;

[0023] Figure 3 A first clock circuit schematic diagram of a clock module for a data link communication processing device proposed by the utility model;

[0024] Figure 4 A schematic diagram of a second clock circuit of a clock module for a data link communication processing device proposed by the utility model;

[0025] Figure 5 This is a schematic diagram of a data receiving circuit for a clock module of a data link communication processing device proposed by the utility model;

[0026] Figure 6The data transmission circuit principle of a clock module for a data link communication processing device proposed by the utility model Figure 1 ;

[0027] Figure 7 The data transmission circuit principle of a clock module for a data link communication processing device proposed by the utility model Figure 2 . DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the utility model more clearly understood, the utility model is further described in detail below in conjunction with embodiments and drawings. The schematic implementation methods of the utility model and their descriptions are only used to explain the utility model and are not intended to limit the utility model.

[0029] Example 1

[0030] refer to Figure 1-Figure 7 , this embodiment proposes a clock module for a data link communication processing device.

[0031] A clock module for a data link communication processing device comprises a clock selection circuit, a first clock circuit, a second clock circuit, an oscillation circuit, and a differential clock circuit; the clock selection circuit is electrically connected to an FPGA circuit, a first clock circuit, and a second clock circuit, respectively; the first clock circuit is connected to a data receiving circuit, the second clock circuit is connected to a data sending circuit, the oscillation circuit is electrically connected to the clock selection circuit, and the differential clock circuit is connected to the clock selection circuit.

[0032] In this embodiment, the FPGA circuit includes a main control chip, and the main control chip model is XC7Z045;

[0033] The clock selection circuit includes a clock selection chip U1, and the model of the clock selection chip U1 is 8305AGILF;

[0034] The first clock circuit includes a clock chip U2, and the model of the clock chip U2 is ADF4350BCPZ;

[0035] The second clock circuit includes a clock chip U3, and the model of the clock chip U3 is ADF4350BCPZ;

[0036] The data receiving circuit includes an analog-to-digital conversion chip U4, and the model of the analog-to-digital conversion chip U4 is AD9265BCPZ;

[0037] The data transmission circuit includes a digital-to-analog conversion chip U5, and the model of the digital-to-analog conversion chip U5 is AD9779A;

[0038] Specifically, pin 7 of the clock selection chip U1 is connected to the B13_L10_N pin of the main control chip, pin 16 of the clock selection chip U1 is connected to the first clock circuit, pin 14 of the clock selection chip is connected to the second clock circuit, pin 12 of the clock selection chip is connected to the B13_L1 pin of the main control chip, pins 5 and 6 of the clock selection chip are respectively connected to the differential clock circuit, and pin 8 of the clock selection chip is connected to the oscillation circuit.

[0039] The differential clock circuit includes a transient voltage suppressor U6, the model of the transient voltage suppressor U6 is PESD3V3X1BL, the pin 1 of the transient voltage suppressor U6 is connected to one end of the capacitor C38, the other end of the capacitor C38 is respectively connected to one end of the resistor R58, one end of the resistor R60, and the 5th pin of the clock selection chip U1, the other end of the resistor R58 is connected to one end of the resistor R59, the other end of the resistor R59 is respectively connected to the 6th pin of the clock selection chip U1, one end of the resistor R61, and one end of the capacitor C39, the other end of the capacitor C39 is connected to the other end of the resistor R61 and then grounded, wherein the transient voltage suppressor with the model PESD3V3X1BL is used to protect the differential clock signal line from damage by electrostatic discharge (ESD) and transient voltage, can quickly respond and shunt overvoltage, and protect downstream sensitive circuits. The pin 1 of the transient voltage suppressor U6 is connected to the capacitor C38, the resistor R58 and the 5th pin of the clock selection chip U1, and these components form a protection and filtering network to ensure the integrity of the transmission signal.

[0040] Capacitors C38 and C39, and resistors R58, R59, R60, and R61 form a filtering and matching network for differential signals, which is used to adjust the impedance matching of the signal and filter out high-frequency noise to ensure stable transmission of the differential signal.

[0041] Pin 1 of transient voltage suppressor U6 is connected to one end of capacitor C38, and the other end of capacitor C38 is respectively connected to one end of resistor R58, one end of resistor R60, and pin 5 of clock selection chip U1, so that capacitor C38 can filter high-frequency noise, and resistors R58 and R60 play the role of signal matching and current limiting. The other end of resistor R58 is connected to one end of resistor R59, and the other end of resistor R59 is respectively connected to pin 6 of clock selection chip U1, one end of resistor R61, and one end of capacitor C39. Resistors R59, R61, and capacitor C39 work together to further filter and match signals, ensuring that pin 6 of clock selection chip U1 receives a stable differential signal.

[0042] The oscillation circuit includes an oscillator U7 with model number AST3TQ-V-10MHz. Pin 3 of the oscillator U7 is connected to pin 8 of the clock selection chip U1. Pin 3 of the oscillator U7 is connected to pin 8 of the clock selection chip U1, and is used to provide a stable and accurate reference clock signal to the clock selection chip. The clock selection chip distributes this reference clock signal to different modules according to system requirements to ensure the synchronization and stable operation of the entire system.

[0043] In this embodiment, pin 29 of the clock chip U2 is connected to pin 16 of the clock selection chip U1, pin 7 of the clock chip U2 is respectively connected to one end of capacitor C44, one end of capacitor C45, and one end of resistor R80, the other end of resistor R80 is respectively connected to one end of capacitor C46 and pin 20 of the clock chip U2, pin 12 of the clock chip U2 is respectively connected to one end of capacitor C51 and one end of inductor L7, the other end of capacitor C51 is connected to pin 2 of the analog-to-digital conversion chip U4, the other end of inductor L7 is respectively connected to one end of capacitor C52, one end of capacitor C54, and one end of inductor L8, the other end of inductor L8 is respectively connected to pin 13 of the clock chip U2 and one end of capacitor C55, and the other end of capacitor C55 is connected to pin 3 of the analog-to-digital conversion chip U4.

[0044] The clock selection chip U1 receives the clock signal provided by the clock chip U2 through pin 16. The clock selection chip U1 can select between multiple clock sources to provide a suitable clock signal for the data link communication device.

[0045] The clock selection chip U1 selects the most appropriate clock signal from the clock chip U2 according to the system requirements and distributes it to the data receiving circuit. The 12th pin of the clock chip U2 provides a stable clock signal to drive the data receiving circuit. The data receiving circuit needs this clock signal to synchronize data sampling and processing.

[0046] Pin 7 of the clock chip U2 is connected to one end of capacitor C44, one end of capacitor C45, and one end of resistor R80. The other end of resistor R80 is connected to one end of capacitor C46 and pin 20 of U2. The above capacitors and resistors form a filtering and stabilizing network for stabilizing the power supply and signal output of U2, mainly for filtering out high-frequency noise and providing a clean power supply environment.

[0047] The 12th pin of the clock chip U2 is connected to one end of the capacitor C51 and one end of the inductor L7, the other end of the capacitor C51 is connected to the 2nd pin of the analog-to-digital conversion chip U4, the other end of the inductor L7 is connected to one end of the capacitor C52, one end of the capacitor C54, and one end of the inductor L8, the other end of the inductor L8 is connected to the 13th pin of U2, one end of the capacitor C55, and the other end of the capacitor C55 is connected to the 3rd pin of U4. The above capacitors and inductors form an LC filter circuit for filtering power supply noise and high-frequency interference to ensure the stability of the clock signal. In addition, the above circuit is also used for voltage stabilization and signal regulation to provide a stable working environment for the analog-to-digital conversion chip U4.

[0048] In this embodiment, pin 29 of the clock chip U3 is connected to pin 14 of the clock selection chip U1, pin 7 of the clock chip U3 is respectively connected to one end of capacitor C47, one end of capacitor C48, and one end of resistor R83, the other end of resistor R83 is respectively connected to one end of capacitor C49 and pin 20 of the clock chip U3, pin 12 of the clock chip U3 is respectively connected to one end of capacitor C53 and one end of inductor L33, the other end of capacitor C53 is connected to pin 5 of the digital-to-analog conversion chip U5, the other end of inductor L33 is respectively connected to one end of capacitor C56, one end of capacitor C57, and one end of inductor L35, the other end of inductor L35 is respectively connected to pin 13 of the clock chip U3 and one end of capacitor C58, and the other end of capacitor C58 is connected to pin 6 of the digital-to-analog conversion chip U5.

[0049] The clock selection chip U1 receives the clock signal provided by the clock chip U3 through its pin 14. The clock selection chip U1 can select the most suitable clock signal according to the clock chip U3 and then distribute it to the data sending circuit.

[0050] The 7th pin of the clock chip U3 is connected to one end of the capacitor C47, one end of the capacitor C48, and one end of the resistor R83. The other end of the resistor R83 is connected to one end of the capacitor C49 and the 20th pin of U2. The above capacitors and resistors form a filtering and voltage stabilizing network to stabilize the power supply and signal output of U3. They can filter out high-frequency noise and provide a clean power supply environment.

[0051] Pin 12 of the clock chip U3 is respectively connected to one end of capacitor C53 and one end of inductor L33, the other end of capacitor C53 is connected to pin 5 of the analog-to-digital conversion chip U5, the other end of inductor L33 is respectively connected to one end of capacitor C56, one end of capacitor C57, and one end of inductor L35, the other end of inductor L35 is respectively connected to pin 13 of U3 and one end of capacitor C58, the other end of capacitor C58 is connected to pin 6 of the analog-to-digital conversion chip U5. The above connection is used for transmission and synchronization of clock signals, as well as communication with the analog-to-digital conversion chip U5. Through the filtering circuit composed of capacitors and inductors, noise is reduced, the clock signal is stabilized, and the accuracy and stability of the analog-to-digital conversion are ensured.

[0052] Example 2

[0053] This embodiment proposes a working process of a clock module for a data link communication processing device based on the embodiment 1.

[0054] 1. The clock selection chip U1 selects the appropriate clock source by connecting to the B13_L10_N pin of the main control chip. The 16th pin of the clock selection chip U1 is connected to the first clock circuit, and the 14th pin of the clock selection chip U1 is connected to the second clock circuit. The clock signal is selected from the circuit and allocated to the data receiving circuit or the data sending circuit according to the system needs.

[0055] 2. The first clock circuit (clock chip U2) is connected to the data receiving circuit to provide a stable clock signal for data sampling and processing;

[0056] The second clock circuit (clock chip U3) is connected to the data transmission circuit and is used to drive the clock signal of data transmission;

[0057] The oscillation circuit (oscillator U7) provides a stable reference clock signal to the clock selection chip U1;

[0058] The differential clock circuit (transient voltage suppressor U6) is used to protect the clock signal line from damage by electrostatic discharge (ESD) and transient voltage;

[0059] The filtering and stabilization network composed of capacitors and resistors ensures the integrity of the transmitted signal and filters out high-frequency noise.

[0060] 3. The other pins of clock chip U2 and clock chip U3 are connected to the filtering and voltage stabilization network to ensure that the clock signal provided to other modules is stable and reliable.

[0061] The clock selection chip U1 selects the most suitable clock signal from the clock chips U2 and U3 and distributes it to the data sending and receiving circuits.

[0062] The above shows and describes the basic principle and main features of the utility model and the advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and the description only illustrate the principle of the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection claimed by the utility model is defined by the attached claims and their equivalents.

Claims

1. A clock module for a data link communication processing device, characterized in that: It includes a clock selection circuit, a first clock circuit, and a second clock circuit; the clock selection circuit is electrically connected to the FPGA circuit, the first clock circuit, and the second clock circuit respectively; the first clock circuit is connected to the data receiving circuit, and the second clock circuit is connected to the data sending circuit.

2. A clock module for a data link communication processing device according to claim 1, characterized in that: An oscillating circuit is also included, and the oscillating circuit is electrically connected to the clock selecting circuit.

3. A clock module for a data link communication processing device according to claim 1, characterized in that: A differential clock circuit is also included, and the differential clock circuit is connected to the clock selection circuit.

4. A clock module for a data link communication processing device according to claim 1, characterized in that: The FPGA circuit includes a main control chip, and the model of the main control chip is XC7Z045.

5. A clock module for a data link communication processing device according to claim 1, characterized in that: The clock selection circuit includes a clock selection chip U1, the model of the clock selection chip U1 is 8305AGILF, the 7th pin of the clock selection chip U1 is connected to the B13_L10_N pin of the main control chip, the 16th pin of the clock selection chip U1 is connected to the first clock circuit, the 14th pin of the clock selection chip is connected to the second clock circuit, the 12th pin of the clock selection chip is connected to the B13_L1 pin of the main control chip, the 5th and 6th pins of the clock selection chip are respectively connected to the differential clock circuit, and the 8th pin of the clock selection chip is connected to the oscillation circuit.

6. A clock module for a data link communication processing device according to claim 1, characterized in that: The first clock circuit includes a clock chip U2, the model of the clock chip U2 is ADF4350BCPZ, the pin 29 of the clock chip U2 is connected to the pin 16 of the clock selection chip U1, the pin 12 of the clock chip U2 is connected to the data receiving circuit, and the pin 13 of the clock chip U2 is connected to the data receiving circuit.

7. A clock module for a data link communication processing device according to claim 1, characterized in that: The second clock circuit includes a clock chip U3, the model of the clock chip U3 is ADF4350BCPZ, the pin 29 of the clock chip U3 is connected to the pin 14 of the clock selection chip U1, the pin 12 of the clock chip U3 is connected to the data sending circuit, and the pin 13 of the clock chip U3 is connected to the data sending circuit.

8. A clock module for a data link communication processing device according to claim 6, characterized in that: The data receiving circuit includes an analog-to-digital conversion chip U4, the model of the analog-to-digital conversion chip U4 is AD9265BCPZ, the pin 12 of the clock chip U2 is connected to the pin 2 of the analog-to-digital conversion chip U4, and the pin 13 of the clock chip U2 is connected to the pin 3 of the analog-to-digital conversion chip U4.

9. A clock module for a data link communication processing device according to claim 7, characterized in that: The data sending circuit includes a digital-to-analog conversion chip U5, the model of the digital-to-analog conversion chip U5 is AD9779A, the pin 12 of the clock chip U3 is connected to the pin 5 of the digital-to-analog conversion chip U5, and the pin 13 of the clock chip U3 is connected to the pin 6 of the digital-to-analog conversion chip U5.

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