Stacking and packaging structure for multiple flash memory chips
Through the multi-flash chip stacking packaging structure, DAF film and epoxy resin technology is used to achieve high storage density and fast transmission speed, solving the problem of low storage density of traditional chip stacking structures, and improving system performance and packaging efficiency.
Patent Information
- Application Number
- CN202420124441.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-18
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-01-18
AI Technical Summary
The traditional chip stack structure has low storage density, making it difficult to accommodate multiple chips, and the package size is large, which cannot meet the demand for high storage density in the era of the big explosion of information and data.
The multi-flash memory chip stacking package structure is adopted, and multi-layer flash memory chips are stacked step by step through DAF film, and packaged with epoxy resin to form a symmetrical dual-tower packaging structure to improve storage density and packaging efficiency.
It achieves higher storage density and faster transmission speeds, reduces package volume and circuit board number, improves system performance, and successfully achieves mass production of multi-chip stacking.
Smart Images
Figure CN222638977U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a multi-flash memory chip stacking packaging structure, belonging to the technical field of integrated circuit advanced high-stack memory packaging. Background Art
[0002] In the chip manufacturing process, the market's current reliance on traditional wire bonding packaging remains high. Traditional chip stacks are small in number, often only 4 or 8 chips, so the storage density of the final product is low. In addition, the traditional stacking structure is simple and the chip is thick, making it difficult to accommodate multiple chips. To expand storage capacity, a larger package size is required. However, with the advent of the era of information data explosion, the market demand for the use of multi-chip stacking technology to achieve high storage density in devices of the same size is also increasing, especially in mobile devices, smart homes, automotive electronics and other fields. Utility Model Content
[0003] The utility model aims to provide a multi-flash memory chip stacking packaging structure in order to overcome the deficiencies of the prior art.
[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a multi-flash memory chip stacking packaging structure, comprising a substrate, a left-side flash memory chip stacking body and a right-side flash memory chip stacking body; the left-side flash memory chip stacking body and the right-side flash memory chip stacking body are both encapsulated on the substrate by epoxy resin; the left-side flash memory chip stacking body has multiple layers, and the multiple layers of the left-side flash memory chip stacking body are stacked in sequence on the substrate by DAF film; the right-side flash memory chip stacking body is the same as the left-side flash memory chip stacking body, and the right-side flash memory chip stacking body and the left-side flash memory chip stacking body are symmetrically arranged.
[0005] Preferably, the left flash memory chip stack is divided into a first flash memory chip stacking group, a second flash memory chip stacking group, a third flash memory chip stacking group and a fourth flash memory chip stacking group; the first flash memory chip stacking group, the second flash memory chip stacking group, the third flash memory chip stacking group and the fourth flash memory chip stacking group are stacked in sequence on the substrate through a DAF film, and the stacking directions of adjacent flash memory chip stacking groups are opposite.
[0006] Preferably, the first flash memory chip stack group, the second flash memory chip stack group, the third flash memory chip stack group and the fourth flash memory chip stack group each include four layers of flash memory chips, the four layers of flash memory chips in each flash memory chip stack group are electrically connected in sequence through gold wires, and the bottom layer of flash memory chips in each flash memory chip stack group are connected to the substrate through gold wires.
[0007] Preferably, a plurality of solder balls are evenly arranged on the bottom surface of the substrate.
[0008] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0009] 1. Stacking more flash memory chips together reduces the number and size of circuit boards and improves storage integration; at the same time, the compact structure of more flash memory chips also reduces the package volume.
[0010] 2. Due to the stacking of multiple flash memory chips, higher bandwidth and faster transmission speed can be achieved, thereby improving the performance of the entire system.
[0011] 3. The application of invisible cutting technology (sDBG), multi-chip stacking picking and bonding technology, ultra-low stable arc control technology and negative pressure equipment environment foreign matter control technology enables the smooth mass production of multi-flash memory chip stacking packaging products. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:
[0013] Attached Figure 1 The present invention is a schematic structural diagram of a multi-flash memory chip stacking packaging structure.
[0014] In the figure: 1. substrate; 2. first flash memory chip stacking group; 3. DAF film; 4. gold wire; 5. second flash memory chip stacking group; 6. third flash memory chip stacking group; 7. fourth flash memory chip stacking group; 8. epoxy resin; 9. solder ball. DETAILED DESCRIPTION
[0015] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0016] As attached Figure 1 As shown, a multi-flash memory chip stacking packaging structure described in the utility model includes a substrate 1, a left flash memory chip stacking body and a right flash memory chip stacking body; the left flash memory chip stacking body and the right flash memory chip stacking body are both encapsulated on the substrate 1 by epoxy resin 8; the right flash memory chip stacking body is the same as the left flash memory chip stacking body, and the right flash memory chip stacking body and the left flash memory chip stacking body are symmetrically arranged to form a double-tower packaging structure.
[0017] The left-side flash memory chip stack has multiple layers, and the multiple layers of the left-side flash memory chip stack are stacked in sequence on the substrate 1 through the DAF film 3, wherein the left-side flash memory chip stack is divided into a first flash memory chip stacking group 2, a second flash memory chip stacking group 5, a third flash memory chip stacking group 6 and a fourth flash memory chip stacking group 7; the first flash memory chip stacking group 2, the second flash memory chip stacking group 5, the third flash memory chip stacking group 6 and the fourth flash memory chip stacking group 7 are all stacked in sequence on the substrate 1 through the DAF film 3, and the stacking directions of adjacent flash memory chip stacking groups are opposite.
[0018] The first flash memory chip stacking group 2, the second flash memory chip stacking group 5, the third flash memory chip stacking group 6 and the fourth flash memory chip stacking group 7 all include four layers of flash memory chips. The four layers of flash memory chips in each flash memory chip stacking group are electrically connected in sequence through gold wires 4, and the bottom flash memory chips in each flash memory chip stacking group are all connected to the substrate 1 through the gold wires 4. In this solution, the thickness of the flash memory chip is below 61um, and the thinnest is 36um. An invisible laser is used to first separate the middle of the chip, then thin it, and finally break the wafer. Since there is no influence of blade cutting, it is easier to control the side edge collapse. At the same time, the internal stress of the chip is smaller, and the chip thickness can be further reduced.
[0019] A plurality of solder balls are evenly arranged on the bottom surface of the substrate.
[0020] The processing process of the packaging structure of the utility model is as follows:
[0021] Step 1: Use sDBG technology to grind and cut the chip to 36um and 61um thickness.
[0022] Step 2: Lamination of the first flash memory chip stacking group:
[0023] The four layers of flash memory chips of the first flash memory chip stacking group are bonded on the substrate using a DAF film.
[0024] Step 3: Gold wire bonding of the first flash memory chip stack:
[0025] Gold wires are used to interconnect flash memory chips and flash memory chips, and flash memory chips and substrates in the first flash memory chip stacking group.
[0026] Step 4: Attach the second flash memory chip stack:
[0027] The four layers of flash memory chips of the second flash memory chip stacking group are bonded together using the DAF film.
[0028] Step 5: Gold wire bonding of the second flash memory chip stack
[0029] Gold wires are used to interconnect the flash memory chips and the flash memory chips of the second flash memory chip stacking group, and the flash memory chips and the substrate.
[0030] Step 6: Attach the third flash memory chip stack:
[0031] The four layers of flash memory chips of the third flash memory chip stacking group are bonded together using the DAF film.
[0032] Step 7: Gold wire bonding of the third flash memory chip stack:
[0033] Gold wires are used to interconnect the flash memory chips and the flash memory chips of the third flash memory chip stacking group, and the flash memory chips and the substrate.
[0034] Step 8: Attach the fourth flash memory chip stack:
[0035] The four layers of flash memory chips of the fourth flash memory chip stacking group are bonded together using the DAF film.
[0036] Step 9: Gold wire bonding of the fourth flash memory chip stack:
[0037] Gold wires are used to interconnect the flash memory chips and the flash memory chips of the fourth flash memory chip stacking group, and the flash memory chips and the substrate.
[0038] Step 10: Epoxy resin injection molding:
[0039] Injection molding using epoxy resin material.
[0040] Step 11: Planting and Slicing:
[0041] The solder balls are soldered to the ball pads on the back of the substrate; at the same time, the strip level packaged products are cut into unit level particles.
[0042] The packaging structure of the utility model adopts multi-chip stacking picking and bonding technology. Due to the limitation that the thickness of the chip is as thin as 36um, a special thin chip picking fixture is used to peel the chip from the carrier film through the protrusions of the multi-step platform. Due to the stacking of multiple chips, the chip bonding position and the distance control between chips are particularly important. The introduction of high-precision bonding machines makes it possible to bond 16 layers of chips in a stepped manner at one time. At the same time, the bonding of all double-tower chips can ensure the accuracy control within ±15um, which effectively reduces the loss of yield and can realize mass production of multi-chip stacking.
[0043] At the same time, ultra-low stable line arc control technology is used to achieve interconnection between flash memory chips and flash memory chips, and between flash memory chips and substrates in each flash memory chip stacking group; in addition, negative pressure equipment environment technology is added to the chip bonding station to prevent foreign matter or particles from falling on the chip surface. Because the chip itself is only 36um thick, foreign matter or particles falling on the surface of the chip can easily cause the chip to break during the chip stacking process. The application of negative pressure equipment technology plays an important role in foreign matter protection.
[0044] The application of the above technologies enables the product to have a higher level of integration, achieve a smaller packaging volume and higher storage performance.
[0045] The packaging structure of the present invention is not limited to the BGA type, wherein the chip grinding thickness and position are not limited, wherein the type of packaged chip is not limited to the flash memory chip.
[0046] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.
Claims
1. A multi-flash memory chip stacking packaging structure, characterized in that: It comprises a substrate (1), a left flash memory chip stack and a right flash memory chip stack; the left flash memory chip stack and the right flash memory chip stack are both encapsulated on the substrate (1) by epoxy resin (8); the left flash memory chip stack has multiple layers, and the multiple layers of the left flash memory chip stack are sequentially stacked on the substrate (1) by DAF films (3); the right flash memory chip stack is the same as the left flash memory chip stack, and the right flash memory chip stack is symmetrically arranged with the left flash memory chip stack.
2. The multi-flash memory chip stacking packaging structure according to claim 1, characterized in that: The left flash memory chip stack is divided into a first flash memory chip stack group (2), a second flash memory chip stack group (5), a third flash memory chip stack group (6) and a fourth flash memory chip stack group (7); the first flash memory chip stack group (2), the second flash memory chip stack group (5), the third flash memory chip stack group (6) and the fourth flash memory chip stack group (7) are stacked in sequence on the substrate (1) through a DAF film (3), and the stacking directions of adjacent flash memory chip stack groups are opposite.
3. The multi-flash memory chip stacking packaging structure according to claim 2, characterized in that: The first flash memory chip stack group (2), the second flash memory chip stack group (5), the third flash memory chip stack group (6) and the fourth flash memory chip stack group (7) each include four layers of flash memory chips, the four layers of flash memory chips in each flash memory chip stack group are electrically connected in sequence via gold wires (4), and the flash memory chips in the bottom layer of each flash memory chip stack group are electrically connected to the substrate (1) via the gold wires (4).
4. The multi-flash memory chip stacking packaging structure according to claim 1, characterized in that: A plurality of solder balls (9) are evenly arranged on the bottom surface of the substrate (1).