Package structure

Abstract

The embodiment of the utility model provides a packaging structure, and the structure comprises a substrate member which comprises a solder mask layer; a barrier structure disposed on the solder resist layer of the substrate member and defining a chip region of the substrate member, where the barrier structure includes a solder resist material; the chip structure is arranged on the substrate component, is positioned in the chip area, and is electrically connected with the substrate component through a conductive connecting piece; and an underfill layer filling a space between the chip structure and the substrate member and surrounding the conductive connector in a direction parallel to the main surface of the substrate member, wherein the barrier structure defines the underfill layer within the chip region and surrounds the underfill layer in a direction parallel to a major surface of the substrate member. According to the packaging structure, the bottom filling layer is limited in the chip area through the blocking structure, so that the reliability of the device can be improved, and the area of the packaging structure can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging, and in particular to a packaging structure. Background Art

[0002] In semiconductor packaging technology, compared with wire bonding packaging, flip chip (FC) packaging is widely used due to its small size, short signal transmission path, good heat dissipation performance and other advantages. In flip chip packaging, the chip structure is mounted on the substrate component through connectors such as solder balls, and a bottom fill layer can be filled between the chip structure and the substrate component. How to apply and control the formation area of ​​the bottom fill layer will affect the performance and reliability of the packaging structure to a certain extent, so it is also an important research topic in the field of semiconductor packaging. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: a substrate component, comprising a solder resist layer; a blocking structure, arranged on the solder resist layer of the substrate component and defining a chip area of ​​the substrate component, wherein the blocking structure comprises a solder resist material; a chip structure, arranged on the substrate component and located in the chip area, and electrically connected to the substrate component through a conductive connector; and a bottom filling layer, filling a space between the chip structure and the substrate component and surrounding the conductive connector in a direction parallel to a main surface of the substrate component; wherein the blocking structure confines the bottom filling layer within the chip area, and surrounds the bottom filling layer in a direction parallel to a main surface of the substrate component.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, the blocking structure is in a closed ring shape, and an inner sidewall of the blocking structure defines the chip area.

[0005] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip structure is spaced apart from the inner sidewall of the barrier structure in a direction parallel to the main surface of the substrate component, and at least a portion of the bottom filling layer contacts the inner sidewall of the barrier structure.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the bottom filling layer has a dispensing edge and an exit edge, wherein both the dispensing edge and the exit edge are in contact with the blocking structure; or the dispensing edge is in contact with the blocking structure, and the exit edge is spaced apart from the blocking structure.

[0007] In the packaging structure provided according to at least one embodiment of the present disclosure, the blocking structure includes a plurality of blocking members, and the plurality of blocking members are arranged side by side and spaced apart in a direction parallel to the main surface of the substrate member.

[0008] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip area defined by the blocking structure includes: a main body area, defined by the inner side wall of the blocking member closest to the chip structure among the multiple blocking members, and the chip structure is arranged in the main body area; and a buffer area, defined by the side walls of adjacent blocking members among the multiple blocking members facing each other.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, the bottom filling layer is entirely located in the main body area; or the bottom filling layer includes a main body filling portion and an overflow portion, the main body filling portion is located in the main body area, and the overflow portion is located in the buffer zone.

[0010] The packaging structure provided according to at least one embodiment of the present disclosure also includes a recess arranged in the buffer zone and located in the solder resist layer, the solder resist layer has a first surface located in the main area and a second surface located in the buffer zone and defining the bottom of the recess, the multiple blocking members include a first blocking member, and the first surface and the second surface are located on opposite sides of the first blocking member, wherein in a direction perpendicular to the main surface of the substrate component, the distance between the first surface and the surface of the first blocking member away from the side of the substrate component is less than the distance between the second surface and the surface of the first blocking member.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the plurality of blocking members have the same or different heights in a direction perpendicular to the main surface of the substrate member.

[0012] In the packaging structure provided according to at least one embodiment of the present disclosure, the multiple blocking members include a first blocking member and a second blocking member, and the second blocking member is located on a side of the first blocking member away from the chip structure, and a height of the first blocking member is less than a height of the second blocking member.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, the plurality of blocking members include a first blocking member and a second blocking member, and a width of the first blocking member or the second blocking member is smaller than a width of a buffer zone defined by the first blocking member and the second blocking member.

[0014] The packaging structure provided according to at least one embodiment of the present disclosure further includes: an additional device, which is arranged on the substrate component and is located in an area outside the chip area defined by the blocking structure and is separated from the bottom filling layer by the blocking structure.

[0015] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a gap region surrounding the blocking structure, and the additional device is arranged on a side of the gap region away from the blocking structure.

[0016] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip structure includes one or more chips and an interposer; the interposer is electrically connected to the substrate component through the conductive connector, and the one or more chips are arranged on a side of the interposer away from the substrate component and are electrically connected to the interposer.

[0017] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip structure includes one or more chips, and the one or more chips are electrically connected to the substrate component through the conductive connection member.

[0018] In the packaging structure provided according to at least one embodiment of the present disclosure, the substrate component is a packaging substrate or a printed circuit board.

[0019] The packaging structure of the embodiment of the present disclosure limits the bottom filling layer within the chip area through the barrier structure, which can improve the reliability of the device and is beneficial to reducing the area of ​​the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0021] Figure 1 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown.

[0022] Figure 2 A schematic cross-sectional view showing a more specific structure of a package structure according to some embodiments of the present disclosure.

[0023] FIG. 3A to FIG. 3C A schematic plan view showing a packaging structure according to some embodiments of the present disclosure is shown.

[0024] FIG. 4A to FIG. 4C Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0025] Figure 5A and Figure 5B Schematic plan views of packaging structures according to other embodiments of the present disclosure are shown.

[0026] FIG. 6A to FIG. 6C A schematic enlarged cross-sectional view showing a local area of ​​a package structure according to some embodiments of the present disclosure.

[0027] Figure 7Schematic cross-sectional views of package structures according to still other embodiments of the present disclosure are shown.

[0028] Figure 8 Schematic cross-sectional views of package structures according to further embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0031] In the packaging structure, the chip structure can be mounted to the substrate member through a conductive connector, and a bottom filling layer can be formed to fill the space between the chip structure and the substrate member, so that the chip structure can be fixed and the conductive connector can be protected. The conductive connector may include conductive materials such as metal and / or solder; for example, the chip structure can be mounted on the substrate member through a welding process, and the conductive connector can also be called a solder joint. In the packaging structure, there may be a situation where stress (for example, mechanical stress and / or thermal stress) is concentrated at the conductive connector. For example, since the thermal expansion coefficients between various material layers may be inconsistent, when the material layers are deformed by thermal expansion, stress concentration may occur in the packaging structure, which may cause the conductive connector to rupture or even fail. By applying a bottom filling layer to fill the space between the chip structure and the substrate member and surrounding the conductive connector, the bottom filling layer can support the chip structure, and can balance and / or disperse stress (including mechanical stress and / or thermal stress) to avoid stress concentration on the conductive connector, thereby avoiding the conductive connector from rupturing or failing due to concentrated stress. In this way, the device performance and reliability of the package structure can be improved, for example, the thermal cycle life of the package structure can be improved.

[0032] For example, the bottom filling layer can be formed by a dispensing process; in the dispensing process, the bottom filling material is first applied by dispensing, and then the bottom filling material is cured to form the bottom filling layer. When the bottom filling material is applied to fill the area between the chip structure and the substrate component, due to the fluidity of the bottom filling material, the bottom filling material may also overflow to other areas, that is, overflow may occur. Other components may be arranged on the substrate component. If the bottom filling material overflows to the area where other components are located, the bottom filling layer formed may adhere to or push these components, which may affect the reliability of the device. On the other hand, if too much bottom filling material overflows, it may cause insufficient filling material in the area where the bottom filling is required, and it is easy to produce air bubbles and gaps; in this case, considering the overflow of the bottom filling material, the amount of the bottom filling material can also be increased to ensure that enough bottom filling material is filled between the chip structure and the substrate component, but this will also cause a certain degree of waste of the bottom filling material. In some examples, in order to prevent the bottom filling layer from sticking or pushing against other components, the distance between the chip structure and the components can be set farther, that is, a sufficient safe overflow distance is set between the chip structure and other components to prevent the bottom filling layer from spreading to the area where other components are located. However, such a setting requires a certain substrate area, resulting in an increase in the overall area of ​​the package structure.

[0033] In view of the above problems, the embodiments of the present disclosure provide a packaging structure that can prevent the bottom filling layer from overflowing and affecting other components, thereby ensuring the reliability of the device and also helping to reduce the area of ​​the packaging structure.

[0034] For example, in an embodiment of the present disclosure, the packaging structure includes a substrate component, a barrier structure, a chip structure, and a bottom filling layer. The substrate component includes a solder resist layer; the barrier structure is disposed on the solder resist layer of the substrate component and defines a chip region of the substrate component, wherein the barrier structure includes a solder resist material; the chip structure is disposed on the substrate component and is located in the chip region and is electrically connected to the substrate component through a conductive connector; the bottom filling layer fills the space between the chip structure and the substrate component and surrounds the conductive connector in a direction parallel to the main surface of the substrate component; wherein the barrier structure confines the bottom filling layer in the chip region and surrounds the bottom filling layer in a direction parallel to the main surface of the substrate component.

[0035] In the disclosed embodiment, by setting a blocking structure to limit the bottom filling layer within the chip area, the bottom filling layer can be prevented from overflowing to the area outside the chip area, and the amount of bottom filling material can be saved, and insufficient bottom filling in the chip area due to excessive overflow of bottom filling material can be avoided, and the occurrence of bubbles and gaps in the bottom filling layer can be avoided or improved. In addition, when other devices are provided on the substrate component in the area outside the chip area, the bottom filling layer can be prevented from sticking or pushing with other devices in the area outside the chip area, thereby ensuring the reliability of the device. Moreover, since a blocking structure is provided to limit the bottom filling layer within the chip area to prevent it from overflowing, there is no need to set a large safe overflow distance, which can help reduce the overall area of ​​the packaging structure.

[0036] Figure 1 A schematic cross-sectional view showing a package structure according to some embodiments of the present disclosure is shown. Figure 2 A schematic cross-sectional view showing a more specific structure of a package structure according to some embodiments of the present disclosure. FIG. 3A to FIG. 3C A schematic plan view showing a packaging structure according to some embodiments of the present disclosure is shown.

[0037] refer to Figure 1 and Figure 2 In some embodiments, the package structure 500 includes a chip structure 120, a substrate member 200, a barrier structure 206, and a bottom filling layer 130. The barrier structure 206 is disposed on the surface of the substrate member 200 and defines the chip region DR of the substrate member. The barrier structure 206 and the surface of the substrate member 200 are in contact with each other and include the same material. The chip structure 120 is disposed on the substrate member 200 and is located in the chip region DR, and is electrically connected to the substrate member 200 through the conductive connection 115. The bottom filling layer 130 fills the space between the chip structure 120 and the substrate member 200 and surrounds the conductive connection 115 in a direction parallel to the main surface of the substrate member; the bottom filling layer 130 may also extend beyond the edge of the chip structure 120 in a direction parallel to the main surface of the substrate member. The barrier structure 206 confines the bottom filling layer 130 in the chip region DR and surrounds the bottom filling layer 130 in a direction parallel to the main surface of the substrate member 200. Herein, the chip area includes a region for arranging a chip structure and an underfill layer corresponding to the chip structure.

[0038] By limiting the bottom filling layer 130 within the chip region DR through the blocking structure 206, the bottom filling layer 130 can be prevented from overflowing to areas outside the chip region DR, thereby preventing the bottom filling layer 130 from sticking or squeezing with components (for example, the additional device 207) located in other areas outside the chip region; moreover, limiting the bottom filling layer 130 within the chip region DR can prevent the bottom filling layer 130 from overflowing to an area with a larger area, thereby saving materials and ensuring that the space between the chip structure 120 and the substrate component 200 in the chip region DR is filled with sufficient bottom filling material, and the possibility of defects such as bubbles and voids in the bottom filling layer can be avoided or reduced, so that the bottom filling layer can effectively provide support, balance and / or disperse stress, thereby improving the performance and reliability of the packaging structure.

[0039] refer to Figure 2 For example, the surface layer of the substrate component 200 may be or include a solder resist layer 204, and the barrier structure 206 may include a solder resist material. That is, the barrier structure 206 is formed on the solder resist layer 204 of the substrate component 200, and the barrier structure is formed by the solder resist material. In some embodiments, the solder resist layer 204 and the barrier structure 206 may be formed by similar processes; for example, a first solder resist material layer may be formed by a first printing process, and then the first solder resist material layer may be subjected to a curing process to form the solder resist layer 204; then a second solder resist material layer may be formed by a second printing process, and then the second solder resist material layer may be subjected to a curing process to form the barrier structure 206. The barrier structure 206 is directly formed on the solder resist layer 204 and is in contact with the solder resist layer 204; since the barrier structure 206 and the solder resist layer 204 have the same material, the adhesion between the barrier structure 206 and the solder resist layer 204 may be increased, and the structural strength of the barrier structure 206 may be improved, so that the barrier structure 206 may effectively confine the bottom filling portion 130 within the chip region DR. Furthermore, the barrier structure 206 and the solder resist layer 204 are made of the same material, which can also simplify the process to a certain extent.

[0040] In some embodiments, FIG. 3A to FIG. 3C As shown, the blocking structure 206 may be in a closed ring shape, and the inner sidewall IS of the blocking structure 206 defines the chip region DR. For example, the blocking structure 206 has an inner sidewall IS and an outer sidewall OS that are opposite to each other in a direction parallel to the main surface of the substrate member, the inner sidewall IS being the sidewall on the side close to the chip structure, and the outer sidewall OS being the sidewall on the side away from the chip structure. In other words, the blocking structure 206 limits the bottom filling layer 130 to the area within the inner sidewall IS thereof, so that the bottom filling layer 130 does not cross the blocking structure 206 and overflow to the outer sidewall OS of the blocking structure 206 and the position outside thereof. For example, the outer sidewall OS of the blocking structure 206 is separated from the bottom filling layer 130 and does not contact each other.

[0041] In some embodiments, the chip structure is spaced apart from an inner sidewall of the barrier structure in a direction parallel to a major surface of the substrate member, and at least a portion of the underfill layer contacts the inner sidewall of the barrier structure.

[0042] refer to FIG. 3A to FIG. 3C For example, the chip structure 120 is spaced apart from the inner sidewall IS of the blocking structure 206 in a direction parallel to the main surface of the substrate component, that is, in the direction, there is a non-zero distance between the edge of the chip structure 120 and the inner sidewall IS of the blocking structure 206. The chip structure 120 and the blocking structure 206 are spaced apart so that a process space for forming a bottom filling layer, such as a dispensing area, can be reserved. For example, a dispensing device can be used to form a bottom filling layer in the chip area through a dispensing process; in the dispensing process, a dispensing nozzle can be used to dispense glue in the dispensing area, so that the bottom filling material is applied to the position of the chip area near the edge of the chip structure, and the bottom filling material flows in the chip area through the capillary effect and fills the space between the chip structure and the substrate component.

[0043] In some embodiments, the bottom filling layer has a dispensing edge and an exit edge, wherein the dispensing edge contacts the barrier structure and the exit edge is spaced apart from the barrier structure; or both the dispensing edge and the exit edge contact the barrier structure.

[0044] For example, in the process of forming the bottom filling layer by the dispensing process, the dispensing equipment applies the bottom filling material at the initial dispensing position near the edge of the chip structure in the chip area, and the bottom filling material then flows and spreads in the chip area, fills between the chip structure and the substrate component, and finally flows to an end position; during the flow of the bottom filling material, the bottom filling material can flow in multiple directions parallel to the main surface of the substrate component. In this article, the edge of the bottom filling layer formed by the bottom filling material at or near the initial dispensing position is called the dispensing edge of the bottom filling layer; and the edge of the bottom filling layer formed by the bottom filling material at the end position of the flow is called the exit edge of the bottom filling layer.

[0045] In some embodiments, the initial glue dispensing position may be located between the chip structure and the blocking structure, and close to the edge of the chip structure and the inner side wall of the blocking structure; for example, the initial glue dispensing position may correspond to a single edge of the chip structure and a single inner side wall of the blocking structure, so that the bottom filling material can flow in the chip area from the initial glue dispensing position on a single side. That is, the bottom filling layer formed may have a single glue dispensing edge, and may have multiple exit edges, but the present disclosure is not limited to this. The initial glue dispensing position close to the blocking structure may also help the blocking structure to push the bottom filling material to flow in other directions. For example, in the case where the planar structure of the chip structure is square, the blocking structure may be square ring-shaped, and the initial glue dispensing position may correspond to the single side edge setting of the chip structure and the blocking structure, so that the bottom filling layer formed will have a glue dispensing edge and three exit edges.

[0046] For example, FIG. 3A to FIG. 3C As shown, the bottom filling layer 130 has a dispensing edge 130a and an exit edge 130b; Figure 3A A schematic diagram showing the flow of the bottom filling material during the formation of the bottom filling layer 130 is shown, and the arrows in the figure schematically show the direction in which the bottom filling material flows from the initial dispensing position corresponding to the dispensing edge toward the end position corresponding to the exit edge.

[0047] In some embodiments, at least a portion of the bottom filling layer contacts the barrier structure, for example, at least a portion of the bottom filling layer is in contact with the barrier structure. Figure 3B As shown, in some embodiments, each edge of the bottom filling layer 130 formed by curing the bottom filling material may contact the blocking structure 206. For example, the dispensing edge 130a and the plurality of exit edges 130b of the bottom filling layer 130 may contact the inner sidewall IS of the blocking structure 206.

[0048] In some embodiments, a portion of the edge of the bottom filling layer 130 contacts the barrier structure 206, while another portion of the edge is spaced apart from the barrier structure 206 and does not contact each other. For example, the dispensing edge 130a of the bottom filling layer 130 may contact the barrier structure 206, and the exit edge 130b of the bottom filling layer 130 may contact or not contact the barrier structure 206. Figure 3CAs shown, the glue-dispensing edge 130a of the bottom filling layer 130 contacts the inner sidewall IS of the blocking structure 206, while the partial exit edge 130b of the bottom filling layer 130 contacts the inner sidewall IS of the blocking structure 206, and the partial exit edge 130b may not contact the inner sidewall IS of the blocking structure 206. For example, the exit edge 130b closer to the glue-dispensing edge 130a may contact the blocking structure, while the exit edge 130b farther from the glue-dispensing edge 130a may not contact the blocking structure. Whether the corresponding edge of the bottom filling layer 130 contacts the inner sidewall of the blocking structure is related to the amount of the bottom filling material applied; for example, when the amount of the bottom filling material applied is relatively large, the bottom filling layer 130 may spread roughly to the entire area in the chip area, so that each edge of the bottom filling layer 130 contacts the blocking structure; when the amount of the bottom filling material applied is relatively small, the bottom filling material may stop flowing before reaching the blocking structure, so that the exit edge of the bottom filling layer formed may not contact the blocking structure.

[0049] In some embodiments, the blocking structure includes a plurality of (e.g., two or more) blocking members, and the plurality of blocking members may be arranged side by side in a direction parallel to the main surface of the substrate member. In this embodiment, the chip area defined by the blocking structure may include a main body area and a buffer area, the main body area is defined by the inner side wall of the blocking member closest to the chip structure among the plurality of blocking members, and the chip structure is arranged in the main body area; the buffer area is defined by the side walls of adjacent blocking members facing each other among the plurality of blocking members, that is, the gap area between adjacent blocking members. The chip area may include one or more buffer areas. In this embodiment, the inner side wall of the blocking structure defining the chip described above may be the inner side wall of the blocking member farthest from the chip structure among the plurality of blocking members (i.e., the outermost blocking member). By setting a plurality of blocking members, it is further ensured that the bottom filling layer is confined within the area enclosed by the blocking structure, and the bottom filling layer is prevented from overflowing into the area outside the blocking structure. For example, in some embodiments, even if a large amount of bottom filling material is applied during the dispensing process, resulting in the bottom filling material overflowing beyond the blocking member closest to the chip structure (i.e., overflowing beyond the main body area), the bottom filling material may be confined within the buffer area by other blocking members, and will not overflow into the area outside the outer side wall of the outermost blocking member of the blocking structure.

[0050] In an embodiment where the blocking structure includes multiple blocking members, the bottom filling layer may be entirely located within the main area; or the bottom filling layer may also extend into the buffer area, for example, the bottom filling layer may include a main filling portion and an overflow portion, the main filling portion being located within the main area, and the overflow portion being located within the buffer area.

[0051] Figure 4A Schematic cross-sectional views showing a package structure 500 according to other embodiments of the present disclosure; Figure 5A Schematic plan views of packaging structures according to other embodiments of the present disclosure are shown.

[0052] refer to Figure 4A and Figure 5A In some embodiments, the blocking structure 206 includes a plurality of blocking members, for example, a first blocking member 206a and a second blocking member 206b, the first blocking member 206a and the second blocking member 206b are arranged side by side and spaced apart in a direction parallel to the main surface of the substrate member, and the second blocking member 206b is located on a side of the first blocking member 206a away from the chip structure 120. For example, the first blocking member 206a is the blocking member closest to the chip structure 120 among the plurality of blocking members, and the second blocking member 206b may be the blocking member farthest from the chip structure 120 among the plurality of blocking members. In this example, the blocking structure includes two blocking members, but it should be understood that this is only an example, and the present disclosure is not limited thereto.

[0053] For example, the chip region DR defined by the blocking structure 206 includes a main region R1 and a buffer region R2; the main region R1 may be defined by the inner sidewall of the first blocking member 206a, that is, the sidewall thereof away from the second blocking member 206b; the buffer region R2 may be defined by the sidewalls of the first blocking member 206a and the second blocking member 206b facing each other. The chip structure 120 is disposed in the main region R1. In the process of dispensing glue to form the bottom filling layer, the initial dispensing position is located in the main region R1.

[0054] like Figure 5A As shown, in some embodiments, the first blocking member 206a and the second blocking member 206b may both be annular, for example, a closed annular shape. In a direction parallel to the main surface of the substrate member, the first blocking member 206a surrounds the main region R1, and the second blocking member 206b surrounds the first blocking member 206a and is spaced apart from the first blocking member 206a. The buffer region R2 is an annular region located between the first blocking member 206a and the second blocking member 206b.

[0055] In some embodiments, Figure 4A and Figure 5A As shown, the bottom filling layer 130 may be entirely located in the main region R1 , that is, the bottom filling layer 130 may be completely confined within the main region R1 by the first barrier 206 a and may not overflow into the buffer region.

[0056] Figure 4B and Figure 5B The schematic diagram exemplarily shows that the bottom filling layer 130 is limited in the chip area and overflows from the main area into the buffer area.

[0057] like Figure 4B and Figure 5BAs shown, in some embodiments, the bottom filling layer 130 includes a main filling portion P1 and an overflow portion P2. The main filling portion P1 is located in the main region R1, fills the space between the chip structure 120 and the substrate member 200, and surrounds the plurality of conductive connectors 115 in a direction parallel to the main surface of the substrate member. The overflow portion P2 is located outside the main region R1 and in the buffer region P2. In some embodiments, the overflow portion P2 may or may not cover the surface of the first barrier 206 away from the substrate member.

[0058] For example, the first blocking member 206a and the second blocking member 206b each have a first side wall (or referred to as an inner side wall) and a second side wall (or referred to as an outer side wall) opposite to each other in a direction parallel to the main surface of the substrate member; the first side wall of the first blocking member 206a is its side wall away from the second blocking member 206b, and defines the main region R1; the second side wall of the first blocking member 206a and the first side wall of the second blocking member 206b face each other and jointly define the buffer region R2. The second side wall of the second blocking member 206b is its side wall away from the first blocking member.

[0059] In some embodiments, the bottom filling layer 130 is entirely located within the main body region, and may contact the first sidewall of the first barrier 206a, and may not contact the second sidewall of the first barrier or the opposite sidewall of the second barrier. In some embodiments, a portion of the bottom filling layer 130 overflows into the buffer region, and the bottom filling layer 130 may contact the first sidewall and the second sidewall of the first barrier 206a, or may also contact the first sidewall of the second barrier 206a. In embodiments where the barrier structure includes a plurality of barrier members, at least the outer sidewall of the outermost barrier member (i.e., the barrier member farthest from the chip structure) among the plurality of barrier members will not contact the bottom filling layer. For example, in an example where the plurality of barrier members only include the first barrier 206a and the second barrier 206b, at least the second sidewall of the second barrier 206b will not contact the bottom filling layer 130.

[0060] In some embodiments, the heights of the plurality of blocking members of the blocking structure in a direction perpendicular to the main surface of the substrate member may be substantially the same or different. The height of the blocking member refers to the distance between the surface of the blocking member contacting the surface layer of the substrate member and the surface of the blocking member away from the substrate member in a direction perpendicular to the main surface of the substrate member. For example, the height of the blocking member farther away from the chip structure among the plurality of blocking members may be higher.

[0061] For example, the heights of the first blocking member and the second blocking member in a direction perpendicular to the main surface of the substrate member may be the same or different. Figure 4B As shown, the heights of the first blocking member 206a and the second blocking member 206b in a direction perpendicular to the main surface of the substrate member may be substantially the same. Figure 4CAn example is shown in which a plurality of blocking members have different heights. Figure 4C As shown, in the direction perpendicular to the main surface of the substrate member, the height of the first barrier 206a can be less than the height of the second barrier 206b. Setting the second barrier farther from the chip structure to have a higher height can fully ensure that the bottom filling layer is prevented from overflowing to areas outside the chip area.

[0062] In some embodiments, in a direction parallel to the main surface of the substrate member, the widths of the plurality of blocking members may be the same or different from each other; the widths of the buffer zones between different adjacent blocking members may be the same or different from each other; the width of the buffer zone may be greater than the width of the blocking member. For example, the width of the first blocking member or the second blocking member is less than the width of the buffer zone defined by the first blocking member and the second blocking member. In some examples, the widths of the first blocking member and the second blocking member may be substantially the same. In this way, when using a blocking member of a smaller width to reduce the occupied area of ​​the blocking structure, the volume of the bottom fill layer that can be accommodated in the buffer zone is larger, thereby being more conducive to preventing the bottom fill zone from overflowing into the area where other components are located.

[0063] Return to reference Figure 2 In some embodiments, the substrate component 200 may be a packaging substrate, and may include a core layer 201, a buildup layer 202, a buildup layer 203, a solder resist layer 204, and a solder resist layer 205. In a direction perpendicular to the main surface of the packaging substrate, the buildup layer 202 and the buildup layer 203 are arranged on opposite sides of the core layer 201, the solder resist layer 204 is arranged on a side of the buildup layer 202 away from the core layer 201, and the solder resist layer 205 is arranged on a side of the buildup layer 203 away from the core layer 201.

[0064] In some embodiments, the core layer 201 includes a core dielectric layer and a conductive member; the buildup layer 202 and the buildup layer 203 may each include a dielectric layer and a conductive structure. For example, the conductive member in the core layer 201 may include a conductive via penetrating the core dielectric layer and / or a conductive wire located on opposite sides of the core dielectric layer, and the conductive wire and the conductive via are connected to each other and electrically connected to the conductive structure in the buildup layer.

[0065] For example, in each stacked layer, the conductive structure may be at least partially embedded in the dielectric layer and may include one or more layers of conductive wires, conductive vias and / or conductive pads, etc. The conductive vias may be used to provide electrical connections between conductive wires located in different layers, electrical connections between the conductive wires and the conductive components of the core layer, etc. The conductive components in the core layer and the conductive structures of each stacked layer are electrically connected to each other.

[0066] In some embodiments, the solder resist layer 204 covers the buildup layer 202 and has a plurality of openings to expose a portion of the conductive structure (e.g., conductive pads) in the buildup layer 202 for connection with the conductive connector 115. For example, the conductive connector 115 may be or include a metal and / or solder material, such as a controlled collapsed chip connection (C4) bump.

[0067] In some embodiments, a conductive connector 210 is further provided on the side of the package substrate away from the chip structure 120, and the conductive connector 210 is electrically connected to the package substrate and electrically connected to the chip structure 120 through the package substrate. For example, the solder resist layer 205 covers the surface of the buildup layer 203 away from the core layer, and a plurality of openings are provided in the solder resist layer 205 to expose part of the conductive structure (e.g., conductive pads) in the buildup layer 203 for electrical connection with the conductive connector 210. The conductive connector 210 can be used to connect the outside of the package structure, and can connect the package structure to other package components, such as a printed circuit board. The conductive connector 210 can also be referred to as a conductive terminal. The conductive connector 210 can be or include a solder ball, such as a ball grid array (BGA).

[0068] In some embodiments, the package structure further includes an additional device disposed on the substrate member, and the additional device is located in an area outside the chip area defined by the blocking structure, wherein in a direction parallel to the main surface of the substrate member, the distance between the chip structure and the blocking structure is smaller than the distance between the chip structure and the additional device. That is, the blocking structure is located between the chip structure and the additional device in a direction parallel to the main surface of the substrate member. In this way, the bottom filling layer is confined within the chip area by the blocking structure, and the bottom filling layer can be prevented from overflowing into the area where the additional device is located, thereby separating the bottom filling layer and the additional device, and preventing adhesion or squeezing between the bottom filling layer and the additional device.

[0069] For example, Figures 1 to 5B As shown, the package structure further includes an additional device 207 disposed on the substrate member 200. The additional device 207 is located in an area outside the chip area defined by the blocking structure, and is located on a side of the blocking structure 206 away from the chip structure 120. In a direction parallel to the main surface of the substrate member, the distance between the chip structure 120 and the blocking structure 206 is smaller than the distance between the chip structure 120 and the additional device 207. The additional device 207 may be or include a capacitor, etc.

[0070] In some embodiments, the package structure further includes a gap region, wherein the gap region surrounds the barrier structure, and the additional device is disposed on a side of the gap region away from the barrier structure.

[0071] refer to FIG. 3A to FIG. 3C or Figure 5A and Figure 5B For example, a gap region GR is provided on the side of the blocking structure 206 away from the chip region DR, the gap region GR surrounds the blocking structure 206 in a direction parallel to the main surface of the substrate member, and the additional device 207 can be provided on the side of the gap region GR away from the blocking structure 206. In other words, the additional device 207 and the blocking structure 206 are spaced apart and may not contact each other. Such a configuration can further ensure that the additional device 207 does not contact the bottom filling layer in the chip region.

[0072] In some embodiments, the additional device 207 passes through the opening of the solder resist layer and is electrically connected to the conductive structure in the package substrate, such as the conductive structure in the buildup layer 202. In some embodiments, the barrier structure is disposed on a side of the solder resist layer away from the buildup layer and may not contact the conductive structure in the buildup layer.

[0073] Fig. 6A Show Figure 2 A schematic enlarged cross-sectional view of region A of the package structure shown; Figure 6B and Figure 6C According to some embodiments of the present disclosure, Figure 4A A schematic enlarged cross-sectional view of region B of the package structure shown. Specifically, FIG. 6A to FIG. 6C Schematic diagrams showing a barrier structure and a surface layer of a substrate component, and for the sake of simplicity of the drawings, the bottom filling layer is not shown in these schematic diagrams.

[0074] refer to FIG. 6A to FIG. 6C In some embodiments, the barrier structure 206 and the solder resist layer 204 of the substrate component 200 are in contact with each other and include the same solder resist material, and an interface may exist between the barrier structure 206 and the substrate component 200. In the substrate component 200, the solder resist layer 204 may cover the conductive structure 202b (i.e., the conductive structure of the buildup layer), the barrier structure 206 is located on a side of the solder resist layer 204 away from the buildup layer, and a portion of the solder resist layer 204 is located between the barrier structure 206 and the conductive structure 202b, so that the barrier structure 206 and the conductive structure 202b are separated from each other.

[0075] In some embodiments, the solder resist layer 204 may have a substantially flat surface; for example, the surface of the solder resist layer 204 in contact with the barrier structure 206 and the surface of the solder resist layer 204 located in the chip region DR may be substantially flush in a direction parallel to the main surface of the substrate member. In some embodiments where the barrier structure has a plurality of barrier members; for example, Figure 6BAs shown, the surface of the solder resist layer 204 located in the main region R1 of the chip region and the surface thereof located in the buffer region R2 may be substantially flush in a direction parallel to the main surface of the substrate member.

[0076] In some embodiments, the packaging structure also includes a recess arranged in the buffer zone and located in the solder resist layer; for example, the solder resist layer has a first surface located in the main area and a second surface located in the buffer zone and defining the bottom of the recess; for example, in a direction perpendicular to the main surface of the substrate component, the first surface of the solder resist layer is at a distance from a surface of the first barrier member on the side away from the substrate component that is smaller than the distance of its second surface from the surface of the first barrier member.

[0077] For example, Figure 6C As shown, a recess 204r located in the solder resist layer 204 is provided in the buffer area R2 between the first barrier 206a and the second barrier 206b. The solder resist layer 204 has a first surface S1 and a second surface S2; the first surface S1 is located in the main area R1, and the second surface S2 is located in the buffer area R2 and defines the bottom of the recess 204r. The first surface S1 and the second surface S2 may be located on opposite sides of the first barrier 206a. In a direction perpendicular to the main surface of the substrate component, the distance d1 between the first surface S1 of the solder resist layer 204 and the surface of the first barrier 206a away from the substrate component is smaller than the distance d2 between the second surface S2 and the surface of the first barrier 206a. In this embodiment, by providing a recess in the buffer area, the volume of the bottom filling layer that can be accommodated in the buffer area can be increased, which is more conducive to preventing the bottom filling layer from overflowing to the area outside the blocking structure. In some embodiments, the solder resist layer 204 has a thinner thickness in the area where the recess is provided, but the solder resist layer in this area can still cover the conductive structure 202 b to prevent the conductive structure of the substrate component from being exposed in the buffer area.

[0078] In some embodiments, the chip structure may be a chip packaging structure including one or more chips. For example, the chip structure may be a chip packaging structure, and may include one or more chips and an interposer, the chip structure is arranged on a packaging substrate, wherein the interposer is electrically connected to a substrate component through a conductive connector, and one or more chips are arranged on a side of the interposer away from the substrate component and are electrically connected to the interposer; the interposer can realize the interconnection between multiple chips and / or the electrical connection between the chip arranged thereon and the substrate component. In some embodiments, the chip structure may also be one or more chips, and the one or more chips are directly electrically connected to the substrate component through a conductive connector. In some embodiments, the substrate component may be a packaging substrate or a printed circuit board.

[0079] For example, refer to Figures 1 to 4CIn some embodiments, the package structure 500 is a chip-on-wafer-on-substrate (CoWoS) package, the chip structure 120 is a chip-on-wafer (CoW) package, and the substrate component 200 is a package substrate.

[0080] In some embodiments, the chip structure 120 includes one or more chips 100 and an interposer 110, the interposer 110 is electrically connected to the package substrate 200 through a conductive connector 115, and the one or more chips 100 are arranged on a side of the interposer 110 away from the package substrate 200 and are electrically connected to the interposer 110. For example, a plurality of chips 100 are arranged on the interposer 110 and can be electrically connected to the interposer 110 through a conductive connector 101; a plurality of chips 100 can be interconnected with each other through the interposer 110 and can be electrically connected to the package substrate 200 through the interposer 110. For example, the conductive connector 101 can be or include a micro-bump.

[0081] In some embodiments, one or more chips 100 may select a suitable chip type according to product requirements, and each may be a system on chip (SoC), a digital signal processor (DSP) chip, a graphic processing unit (GPU), an application specific integrated circuit (ASIC) chip, a memory chip, a central processing unit (CPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), a general-purpose graphics processing unit (GPGPU), etc. For example, a plurality of chips 100 are arranged on an intermediate layer, and may include chips of the same type or different types. For example, one of the plurality of chips 100 may be a system chip, and another of the plurality of chips 100 may be a memory chip, such as a high bandwidth memory (HBM) chip. It should be understood that the number of chips shown in the figure is only for illustration, and the present disclosure is not limited thereto.

[0082] In some embodiments, the chip 100 may include a substrate, a device layer, and conductive pads and / or conductive bumps, etc.; the substrate may be or include a semiconductor substrate such as a silicon substrate; the device layer is disposed on one side of the substrate, and may include active devices (e.g., transistors), passive devices (e.g., capacitors, inductors, etc.) or a combination thereof, and an interconnection structure, and each device may be connected through the interconnection structure; the conductive pads and / or conductive bumps are located on the side of the device layer away from the substrate, and may be electrically connected to various devices on the substrate through the interconnection structure; the conductive pads and / or conductive bumps may be used as external connection points of the chip for electrical connection between the chip and other components (e.g., the conductive connector 101 and the interposer), and may be referred to as input / output (I / O) contacts of the chip. The side of the chip close to the device layer (e.g., the side with the conductive pads and / or conductive bumps) may be referred to as the front side or active side of the chip, and the side of the chip where the substrate is located (i.e., the side opposite to the front side) may be referred to as the back side. For example, each chip may be flip-chip mounted on the interposer 210 , such that the front side thereof faces the interposer, and may be electrically connected to the interposer 210 via the conductive connector 101 .

[0083] In some embodiments, one or more dummy chips may be further disposed on the interposer 110, for example, including a dummy chip 100a, which is, for example, a blank chip that does not include a device and may include a silicon substrate. For example, the interposer 110 has a chip bonding area, and multiple chips 100 are mounted to the chip bonding area of ​​the interposer 110, and the dummy chip can fill the empty area of ​​the chip bonding area that is not bonded to the chip, thereby preventing the warping of the package structure. It should be understood that in some embodiments, if the sizes of the multiple chips on the interposer can match each other, it is not necessary to set a dummy chip.

[0084] In some embodiments, the package structure may further include an encapsulation layer 105 to encapsulate the plurality of chips. For example, the encapsulation layer 105 is disposed on a side of the interposer 110 away from the substrate component, and surrounds and encapsulates the plurality of chips 100 and the dummy chip 100a. For example, the encapsulation layer 105 may include a molding compound, such as an epoxy molding compound (EMC).

[0085] In some embodiments, the interposer may be or include a silicon-based interposer, a redistribution layer (RDL), a bridge chip, etc.

[0086] like Figures 1 to 4CIn some embodiments, the interposer 110 is a redistribution structure and may include a dielectric structure and one or more redistribution layers; the dielectric structure includes an organic dielectric material, such as a suitable polymer material including epoxy resin, polyimide, etc., and may be a single-layer or multi-layer structure. One or more redistribution layers are embedded in the dielectric structure and may include conductive wires and conductive vias. The redistribution layer may include metal materials such as titanium and copper.

[0087] In other embodiments, the interposer 110 may also be a silicon-based adapter plate, and include a silicon substrate, an interconnect structure disposed on the silicon substrate, and a through substrate via (TSV) disposed in the silicon substrate. In alternative embodiments, the interposer 110 may also include a bridge chip, which may be embedded in an organic dielectric structure, such as a dielectric structure of a rewiring structure. It should be understood that any type of interposer may be selected based on product design and requirements, and the present disclosure is not limited thereto.

[0088] In other embodiments, the chip structure may also be other types of chip packages, such as a CoWoS package structure. For example, the package structure 500 may also be used as a chip structure. The substrate component may also be a circuit board such as a printed circuit board (PCB). For example, a bottom filling layer may be provided between the chip structure and the circuit board as the substrate component, and a blocking structure may be provided on the circuit board to prevent the bottom filling layer from overflowing to an area outside the blocking structure.

[0089] Figure 7 Schematic cross-sectional views of package structures according to other embodiments of the present disclosure are shown.

[0090] refer to Figure 7 In some embodiments, the package structure 500 may be mounted on a circuit board 300. For example, the package structure 500 may be connected to the circuit board 300 via a conductive connector 210. The package structure 500 may also be referred to as a chip structure; the circuit board 300 may be, for example, a printed circuit board, and may also be referred to as a substrate component.

[0091] In some embodiments, the package structure 500 may be disposed on the surface layer of the circuit board 300, and a barrier structure 306 is disposed on the surface layer of the circuit board 300, and the barrier structure 306 is used to define the chip area of ​​the circuit board (i.e., the area for disposing the package structure 500 including the chip 100). For example, the surface layer of the circuit board 300 includes a solder resist layer 301, and the barrier structure 306 is disposed on the solder resist layer 301 and contacts the solder resist layer 301. The barrier structure 306 and the solder resist layer 301 include the same solder resist material.

[0092] In some embodiments, an underfill layer 212 may be disposed between the package structure 500 and the circuit board 301 to fill the space between the package structure 500 and the circuit board 301 and surround the conductive connector 210 in a direction parallel to the main surface of the circuit board. The underfill layer 212 may extend beyond the edge of the package structure 500 in a direction parallel to the main surface of the circuit board and may cover a portion of the sidewall of the package structure 500 (e.g., a portion of the sidewall of the package substrate). At least a portion of the edge of the underfill layer 212 contacts the barrier structure 306 and is confined in a region defined by the inner sidewall of the barrier structure 306.

[0093] In some embodiments, the solder resist layer 301 of the circuit board 300 has a plurality of openings (not shown), and the conductive connector 210 is electrically connected to the conductive member (not shown) in the circuit board 300 through the openings. A solder resist layer may also be provided on one side of the circuit board 300 away from the package structure 500.

[0094] In some embodiments, other electronic devices 307 (or additional devices) may be further disposed on the circuit board 300. The electronic device 307 is disposed on the side of the blocking structure 306 away from the packaging structure 500. By setting the blocking structure to restrict the bottom filling layer 212 within the chip area, the bottom filling layer 212 can be prevented from overflowing into the area where other devices (for example, the electronic device 307) are located on the circuit board, thereby preventing the bottom filling layer 212 from sticking to or squeezing other electronic devices.

[0095] In this embodiment, the structural positional relationship between the circuit board 300 (i.e., substrate component), the package structure 500 (i.e., chip structure), the blocking structure 306, the bottom filling layer 210, and the electronic device 307 (i.e., additional device) is substantially the same as the structural positional relationship between the substrate component 200, the chip structure 120, the blocking structure 206, the bottom filling layer 130, and the additional device 207 described above, and will not be described in detail. In some embodiments, the chip structure 120 may also be directly disposed on the circuit board as the substrate component, and the package substrate may be omitted.

[0096] Figure 8 A schematic cross-sectional view of a packaging structure according to another embodiment of the present disclosure is shown. Figure 1 The package structure shown omits the interposer.

[0097] refer to Figure 8In some embodiments, the package structure is a FCBGA package, wherein the chip structure 120 includes one or more chips 100, and the one or more chips 100 can be directly electrically connected to the package substrate 200 through the conductive connector 101. The bottom filling layer 102 fills the space between the one or more chips 100 and the package substrate 200 and surrounds the plurality of conductive connectors 101. The barrier structure 206 limits the bottom filling layer 102 within the chip area, thereby preventing the bottom filling layer 102 from overflowing to the area outside the chip area, thereby preventing the bottom filling layer 102 from contacting other devices, such as the additional device 207. In this embodiment, the structural position relationship among the substrate component 200, the chip structure 120, the barrier structure 206, the bottom filling layer 102, and the additional device 207 is substantially the same as the structural position relationship among the substrate component 200, the chip structure 120, the barrier structure 206, the bottom filling layer 130, and the additional device 207 in the aforementioned embodiment, and will not be repeated here.

[0098] In the packaging structure of the embodiment of the present disclosure, the chip structure may be one or more chips, or a chip package including one or more chips, and the substrate component may be a packaging substrate or a circuit board, and the bottom filling layer fills the space between the chip structure and the substrate component; by setting a blocking structure on the substrate component to confine the bottom filling layer to the chip area, the bottom filling layer can be effectively prevented from overflowing to the area of ​​other components, thereby avoiding the bottom filling layer affecting the device reliability of other components, and it is beneficial to reduce the overall size of the packaging structure.

[0099] There are a few points to note:

[0100] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0101] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0102] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: include: a substrate component including a solder mask; a blocking structure disposed on the solder resist layer of the substrate component and defining a chip area of ​​the substrate component, wherein the blocking structure comprises a solder resist material; A chip structure is disposed on the substrate component and is located in the chip area and is electrically connected to the substrate component through a conductive connector; as well as a bottom filling layer filling the space between the chip structure and the substrate member and surrounding the conductive connection member in a direction parallel to the main surface of the substrate member; The barrier structure confines the underfill layer within the chip region and surrounds the underfill layer in a direction parallel to the main surface of the substrate member.

2. The packaging structure according to claim 1, characterized in that: The blocking structure is in a closed ring shape, and the inner sidewall of the blocking structure defines the chip area.

3. The packaging structure according to claim 2, characterized in that: The chip structure is spaced apart from the inner sidewall of the barrier structure in a direction parallel to the main surface of the substrate member, and at least a portion of the underfill layer is in contact with the inner sidewall of the barrier structure.

4. The packaging structure according to any one of claims 1 to 3, characterized in that: The bottom filling layer has a glue dispensing edge and an exit edge, wherein both the glue dispensing edge and the exit edge are in contact with the blocking structure; or the glue dispensing edge is in contact with the blocking structure, and the exit edge is spaced apart from the blocking structure.

5. The packaging structure according to any one of claims 1 to 3, characterized in that: The blocking structure includes a plurality of blocking members, and the plurality of blocking members are arranged side by side and spaced apart in a direction parallel to a main surface of the substrate member.

6. The packaging structure according to claim 5, characterized in that: The chip area defined by the blocking structure includes: a main body region defined by an inner sidewall of a blocking member among the plurality of blocking members that is closest to the chip structure, and the chip structure is disposed in the main body region; and A buffer zone is defined by side walls of adjacent blocking members among the plurality of blocking members facing each other.

7. The packaging structure according to claim 6, characterized in that: The bottom filling layer is entirely located within the main body region; or The bottom filling layer includes a main filling portion and an overflow portion, the main filling portion is located in the main area, and the overflow portion is located in the buffer area.

8. The packaging structure according to claim 6, characterized in that: It also includes a recess arranged in the buffer zone and located in the solder resist layer, the solder resist layer having a first surface located in the main area and a second surface located in the buffer zone and defining the bottom of the recess, the multiple blocking members include a first blocking member, and the first surface and the second surface are located on opposite sides of the first blocking member, wherein in a direction perpendicular to the main surface of the substrate component, the distance between the first surface and the surface of the first blocking member away from the side of the substrate component is less than the distance between the second surface and the surface of the first blocking member.

9. The packaging structure according to claim 5, characterized in that: The plurality of stoppers may have the same or different heights in a direction perpendicular to the main surface of the substrate member.

10. The packaging structure according to claim 5, characterized in that: The plurality of blocking members include a first blocking member and a second blocking member, wherein the second blocking member is located at a side of the first blocking member away from the chip structure, and a height of the first blocking member is smaller than a height of the second blocking member.

11. The packaging structure according to claim 5, characterized in that: The plurality of stoppers include a first stopper and a second stopper, and a width of the first stopper or the second stopper is smaller than a width of a buffer zone defined by the first stopper and the second stopper.

12. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: The additional device is arranged on the substrate component and is located in a region outside the chip region defined by the blocking structure and is separated from the bottom filling layer by the blocking structure.

13. The packaging structure according to claim 12, characterized in that: The packaging structure further includes: A gap region surrounds the blocking structure, and the additional device is arranged on a side of the gap region away from the blocking structure.

14. The packaging structure according to claim 1, characterized in that: The chip structure includes one or more chips and an interposer; The interposer is electrically connected to the substrate component through the conductive connection member, and the one or more chips are disposed on a side of the interposer away from the substrate component and are electrically connected to the interposer.

15. The packaging structure according to claim 1, characterized in that: The chip structure includes one or more chips, and the one or more chips are electrically connected to the substrate component through the conductive connection.

16. The packaging structure according to any one of claims 12 to 15, characterized in that: The substrate component is a packaging substrate or a printed circuit board.

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