Sampling hold circuit and switch thereof
By designing a switch structure including a first transmission switch module, a second transmission switch module and an auxiliary switch module in the sampling and holding circuit, the problem of switch leakage in the traditional sampling and holding circuit is solved, and the charge holding stability and ADC performance are significantly improved.
Patent Information
- Application Number
- CN202420660511.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-01
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-04-01
AI Technical Summary
Switch leakage is prone to traditional sampling and holding circuits, which causes the output potential to change during a long period of maintenance, affecting the performance of the later ADC.
A switch of a sampling and holding circuit is designed, including a first transmission switch module, a second transmission switch module and an auxiliary switch module. By setting an auxiliary switch module between the preset node and the voltage control terminal, the charge of the preset node is avoided to move to both ends and the leakage situation is improved.
It effectively improves the leakage condition and crosstalk problems after the signal transmission switch is turned off, and improves the performance of the later ADC.
Smart Images
Figure CN222814471U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of circuit technology, and in particular to a sample-and-hold circuit and a switch thereof. Background Art
[0002] The sample-and-hold circuit can convert analog signals into stable level signals, so that the level signals can be sampled by the subsequent ADC (analog-to-digital converter). It can be seen that the sample-and-hold circuit is a bridge for converting analog signals into digital signals.
[0003] The inventor studied the working process of the sample-and-hold circuit and found that switch leakage is prone to occur in the sample-and-hold circuit. The switch leakage can easily cause the output potential to change during a long holding period, which can easily affect the performance of the subsequent ADC. Utility Model Content
[0004] In view of this, the present application provides a sample-and-hold circuit and a switch thereof to solve the problem that switch leakage is prone to occur in traditional sample-and-hold circuits. The switch leakage can easily cause the output potential to change during a long holding period, which can easily affect the performance of the subsequent ADC.
[0005] The present application provides a switch of a sample-and-hold circuit, wherein the switch of the sample-and-hold circuit comprises a first transmission switch module, a second transmission switch module and an auxiliary switch module;
[0006] The first end of the first transmission switch module is connected to the first preset end of the sampling and holding circuit, and the second end is connected to the preset node; the first end of the second transmission switch module is connected to the preset node, and the second end is connected to the second preset end of the sampling and holding circuit; the first end of the auxiliary switch module is connected to the preset node, and the second end is connected to the voltage control end to access the voltage provided by the voltage control end, and the voltage control end is used to provide a voltage to the preset node to prevent the charge of the preset node from moving to both ends;
[0007] The auxiliary switch module is used to close after the first transmission switch module and the second transmission switch module are disconnected, so that the preset node is connected to the voltage control end to prevent the charge from moving to the two ends.
[0008] Optionally, the switch of the sampling and holding circuit also includes a control logic module; the control logic module is respectively connected to the control ends of the first transmission switch module, the second transmission switch module and the auxiliary switch module to control the on and off of the first transmission switch module, the second transmission switch module and the auxiliary switch module.
[0009] Optionally, the first transmission switch module includes a first PMOS tube and a first NMOS tube; the second transmission switch module includes a second PMOS tube and a second NMOS tube; the preset node includes a first node and a second node; the gate of the first PMOS tube is used to access the first control signal, the first end is connected to the first preset end, and the second end is connected to the first node; the gate of the first NMOS tube is used to access the second control signal, the first end is connected to the first preset end, and the second end is connected to the second node; the gate of the second PMOS tube is used to access the first control signal, the first end is connected to the first node, and the second end is connected to the second preset end; the gate of the second NMOS tube is used to access the second control signal, the first end is connected to the second node, and the second end is connected to the second preset end; the first control signal and the second control signal are a pair of opposite control signals.
[0010] Optionally, the auxiliary switch module includes a first switch and a second switch; the first end of the first switch is connected to the first node, and the second end is connected to the first end of the second switch, and is used to access the voltage provided by the voltage control end; the second end of the second switch is the second node; the first switch and the second switch are respectively closed when the first control signal is at a high level, and opened when the first control signal is at a low level.
[0011] Optionally, the switches of the sampling and holding circuit also include a third switch, a fourth switch, a fifth switch and a sixth switch; the first end of the third switch is used to access the power supply voltage, and the second end is respectively connected to the first end of the fourth switch, the substrate end of the first PMOS tube and the substrate end of the second PMOS tube; the second end of the fourth switch is respectively connected to the first end of the fifth switch and the second end of the first switch; the second end of the fifth switch is respectively connected to the first end of the sixth switch, the substrate end of the first NMOS tube and the substrate end of the second NMOS tube; the second end of the sixth switch is grounded; the third switch and the sixth switch are respectively closed when the first control signal is at a high level, and are opened when the first control signal is at a low level; the fourth switch and the fifth switch are respectively closed when the second control signal is at a high level, and are opened when the second control signal is at a low level.
[0012] The present application also provides a sample-and-hold circuit, comprising a switch of any of the above-mentioned sample-and-hold circuits.
[0013] Optionally, the sampling and holding circuit also includes a seventh switch, an eighth switch, a capacitor and an operational amplifier; the first end of the eighth switch is used to access the input voltage, and the second end is respectively connected to the first end of the capacitor and the first end of the seventh switch; the second end of the seventh switch is respectively connected to the second preset end and the output end of the operational amplifier; the second end of the capacitor is respectively connected to the first preset end and the inverting input end of the operational amplifier; the non-inverting input end of the operational amplifier is used to access the reference voltage.
[0014] The above-mentioned sampling and holding circuit and its switch of the present application are provided with a first transmission switch module between the first preset end and the preset node, a second transmission switch module between the second preset end and the preset node, and an auxiliary switch module between the preset node and the voltage control end. After the first transmission switch module and the second transmission switch module are disconnected, the auxiliary switch module is closed, and the voltage of the preset node is the voltage of the voltage control end, which can prevent the charge of the preset node from moving to both ends and improve the leakage condition of the first preset end or the second preset end. It can be seen that the present application can effectively improve the leakage condition after each signal transmission switch is turned off, as well as the crosstalk problem, and improve the performance of the subsequent ADC. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0016] Figure 1 is a schematic diagram of a switch structure of a sample-and-hold circuit according to an embodiment of the present application;
[0017] Figure 2 is a schematic diagram of a switch structure of a sample-and-hold circuit according to another embodiment of the present application;
[0018] Figure 3 is a schematic diagram of a switch structure of a sample-and-hold circuit according to another embodiment of the present application;
[0019] Figure 4 is a schematic diagram of a switch structure of a sample-and-hold circuit according to another embodiment of the present application;
[0020] Figure 5 is a schematic diagram of a sample-and-hold circuit according to an embodiment of the present application;
[0021] Figure 6 It is a simulation comparison analysis schematic diagram of an embodiment of the present application. DETAILED DESCRIPTION
[0022] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0023] The present application provides a switch of a sample-and-hold circuit according to a first aspect. Figure 1 As shown, the switches of the sample-and-hold circuit include a first transmission switch module 110 , a second transmission switch module 120 and an auxiliary switch module 130 .
[0024] The first end of the first transmission switch module 110 is connected to the first preset terminal VA of the sampling and holding circuit, and the second end is connected to the preset node A; the first end of the second transmission switch module 120 is connected to the preset node A, and the second end is connected to the second preset terminal VB of the sampling and holding circuit; the first end of the auxiliary switch module 120 is connected to the preset node A, and the second end is connected to the voltage control terminal VM to access the voltage provided by the voltage control terminal VM, and the voltage control terminal VM is used to provide voltage to the preset node A to prevent the charge of the preset node A from moving to both ends. The auxiliary switch module 130 is used to close after the first transmission switch module 120 and the second transmission switch module 130 are disconnected, so that the preset node A is connected to the voltage control terminal VM to prevent the charge from moving to both ends.
[0025] Optionally, the voltage control terminal VM may provide a preset voltage, where the preset voltage is the voltage of the first preset terminal VA or the second preset terminal VB.
[0026] Specifically, when the first transmission switch module 110 and the second transmission switch module 120 are closed, the auxiliary switch module 130 is disconnected, and signal transmission is performed between the first preset terminal VA and the second preset terminal VB, that is, Figure 1 The signal between VA and VB is transmitted normally. When the first transmission switch module 110 and the second transmission switch module 120 are disconnected, the auxiliary switch module 130 is closed, and the voltage of the preset node A is the preset voltage.
[0027] like Figure 1The voltage of point A (preset node) is set to the preset voltage (i.e., the voltage VM provided by the voltage control terminal VM), and the voltage of the first preset terminal VA is VA. If VM=VA is set at this time, the voltage of the first preset terminal VA is close to that of point A. At this time, the charge of the first preset terminal VA will not move to point A, which can ensure that the first preset terminal VA has a small leakage. Similarly, if the voltage of the second preset terminal VB is VB, VM=VB is set at this time, VB is close to the voltage of point A, and the charge of the second preset terminal VB will not move to point A, which can ensure that the second preset terminal VB has a small leakage. It can be seen that the switch of the above-mentioned sampling and holding circuit can reduce the leakage problem after the signal transmission switch is turned off, as well as the crosstalk problem.
[0028] In one embodiment, reference Figure 2 As shown, the switch of the sampling and holding circuit also includes a control logic module 140; the control logic module 140 is respectively connected to the control ends of the first transmission switch module 110, the second transmission switch module 120 and the auxiliary switch module 130 to control the on and off of the first transmission switch module 110, the second transmission switch module 120 and the auxiliary switch module 130; for example, the control logic module 140 can control the auxiliary switch module 130 to be turned on when controlling the first transmission switch module 110 and the second transmission switch module 120 to be turned off, so that the preset node A is connected to the preset voltage, so as to avoid the charge of the first preset terminal VA or the second preset terminal VB from moving to the preset node A, and reduce the mutual interference between the first preset terminal VA and the second preset terminal VB.
[0029] Specifically, the control logic module 140 may include a first output terminal for outputting a first control signal CLKN and a second output terminal for outputting a second control signal CLK, so as to respectively connect the respective control terminals of the respective devices and / or switches, so as to input the first control signal CLKN and / or the second control signal CLK into the corresponding devices and / or switches.
[0030] In one embodiment, reference Figure 3 As shown, the first transmission switch module 110 includes a first PMOS transistor MP1 and a first NMOS transistor MN1; the second transmission switch module 120 includes a second PMOS transistor MP2 and a second NMOS transistor MN2. The preset node A includes a first node VMP and a second node VMN.
[0031] The gate of the first PMOS transistor MP1 is used to access the first control signal CLKN, the first end is connected to the first preset end VA, and the second end is connected to the first node VMP; the gate of the first NMOS transistor MN1 is used to access the second control signal CLK, the first end is connected to the first preset end VA, and the second end is connected to the second node VMN. The gate of the second PMOS transistor MP2 is used to access the first control signal CLKN, the first end is connected to the first node VMP, and the second end is connected to the second preset end VB; the gate of the second NMOS transistor MN2 is used to access the second control signal CLK, the first end is connected to the second node VMN, and the second end is connected to the second preset end VB. The first end of the first PMOS transistor MP1 can be its source or its drain; if the first end of the first PMOS transistor MP1 is its source, the second end is its drain. Similarly, in the first NMOS transistor MN1, the second PMOS transistor MP2 and the second NMOS transistor MN2, the first end can be the source or drain of the corresponding MOS transistor, and the second end is the other pole of the corresponding MOS transistor. Specifically, the source and drain connection characteristics of the above-mentioned MOS tubes can be determined according to the potential characteristics of the first preset terminal VA and the second preset terminal VB; for example, in the first PMOS tube MP1 and the second PMOS tube MP2, the source is used to access the high potential signal, and the drain is connected to the low potential node; in the first NMOS tube MN1 and the second NMOS tube MN2, the drain is used to access the high potential signal, and the source is connected to the low potential node.
[0032] The first control signal CLKN and the second control signal CLK are a pair of opposite control signals. The first control signal CLKN and the second control signal CLK may be issued by the control logic module 140 . Figure 3 The first transmission switch module 110 and the second transmission switch module 120 form a composite switch. Specifically, the second control signal CLK is at a high level, the first control signal CLKN is at a low level, and the entire composite switch is turned on.
[0033] In one example, if Figure 3 As shown, the auxiliary switch module 130 includes a first switch S30 and a second switch S31. The first end of the first switch S30 is connected to the first node VMP, and the second end is connected to the first end of the second switch S31, and is used to access the voltage provided by the voltage control end; the second end of the second switch S31 is the second node VMN. The first switch S30 and the second switch S31 are respectively closed when the first control signal CLKN is at a high level, and are opened when the first control signal CLKN is at a low level.
[0034] Optionally, refer to Figure 4As shown, the switches of the sampling and holding circuit further include a third switch S10, a fourth switch S20, a fifth switch S21 and a sixth switch S11. The first end of the third switch S10 is used to access the power supply voltage VDD, and the second end is respectively connected to the first end of the fourth switch S20, the substrate end of the first PMOS transistor MP1 and the substrate end of the second PMOS transistor MP2; the second end of the fourth switch S20 is respectively connected to the first end of the fifth switch S21 and the second end of the first switch S30; the second end of the fifth switch S21 is respectively connected to the first end of the sixth switch S11, the substrate end of the first NMOS transistor MN1 and the substrate end of the second NMOS transistor MN2; the second end of the sixth switch S11 is grounded. The third switch S10 and the sixth switch S11 are respectively closed when the first control signal CLKN is at a high level, and are opened when the first control signal CLKN is at a low level; the fourth switch S20 and the fifth switch S21 are respectively closed when the second control signal CLK is at a high level, and are opened when the second control signal CLK is at a low level.
[0035] Specifically, for Figure 4 The switch of the sample-and-hold circuit shown in the figure, when the first control signal CLKN is at a low level and the second control signal CLK is at a high level, the composite switch is turned on, the substrate terminals Vbulkp of the PMOS switch tubes MP1 and MP2 are connected to the voltage control terminal VM, and the substrate terminals Vbulkn of the NMOS switch tubes MN1 and MN2 are connected to the voltage control terminal VM, so that when the voltage of the first preset terminal VA and the second preset terminal VB is close to the voltage VM provided by the voltage control terminal VM, the conduction impedance of the composite switch is smaller (compared to the connection method in which the substrate terminal of the PMOS is connected to the power supply and the substrate terminal of the NMOS is connected to the ground). When the second control signal CLK is at a low level and the first control signal CLKN is at a high level, the composite switch is turned off, the substrate terminals Vbulkp of the PMOS switch tubes MP1 and MP2 are connected to the power supply voltage VDD, the substrate terminals Vbulkn of the NMOS switch tubes MN1 and MN2 are connected to the ground, and at the same time, VMP and VMN are connected to the voltage VM provided by the voltage control terminal VM. If VM=VA (the voltage provided by the first preset terminal VA) is set at this time, VA is close to the voltage at the first node VMP and the second node VMN, and the charge of the first preset terminal VA will not move to the first node VMP and the second node, which can improve the leakage condition of the first preset terminal VA. Similarly, if VM=VB (the voltage provided by the second preset terminal VB) is set at this time, VB is close to the voltage at the first node VMP and the second node VMN, respectively, and the charge of the second preset terminal VB will not move to the first node VMP and the second node VMN, which can improve the leakage condition of the second preset terminal VB.
[0036] In the switch of the above sampling and holding circuit, a first transmission switch module 110 is arranged between the first preset terminal VA and the preset node A, a second transmission switch module 120 is arranged between the second preset terminal VB and the preset node A, and an auxiliary switch module 130 is arranged between the preset node A and the voltage control terminal VM. When the first transmission switch module 110 and the second transmission switch module 120 are closed, the auxiliary switch module 130 is disconnected, and signal transmission is performed between the first preset terminal VA and the second preset terminal VB. When the first transmission switch module 110 and the second transmission switch module 120 are disconnected, the auxiliary switch module 130 is closed, and the voltage of the preset node A is the preset voltage; if the voltage VM of the voltage control terminal VM is the voltage VA provided by the first preset terminal VA, the voltage of the first preset terminal VA and the preset node A are close, and at this time, the charge of the first preset terminal VA will not move to point A, which can improve the leakage condition of the first preset terminal VA; if the voltage VM of the voltage control terminal VM is the voltage VB provided by the second preset terminal VB, the voltage of the second preset terminal VB and the preset node A are close, and at this time, the charge of the second preset terminal VB will not move to the preset node A, which can improve the leakage condition of the second preset terminal VB. It can be seen that the switch of the above-mentioned sampling and holding circuit can effectively improve the leakage condition and crosstalk problem after each signal transmission switch is turned off.
[0037] A first aspect of the present application provides a sample-and-hold circuit, wherein the sample-and-hold circuit comprises a switch of the sample-and-hold circuit described in any one of the above embodiments.
[0038] Specifically, refer to Figure 5 As shown, the switch of the sampling and holding circuit described in any of the above embodiments is denoted as SW1. The sampling and holding circuit also includes a seventh switch SW2, an eighth switch SW3, a capacitor C1 and an operational amplifier OP. The first end of the eighth switch SW3 is used to access the input voltage Vin, and the second end can be denoted as M, which is respectively connected to the first end of the capacitor C1 and the first end of the seventh switch SW2; the second end of the seventh switch SW2 is respectively connected to the second preset end VB and the output end of the operational amplifier OP; the second end of the capacitor C1 can be denoted as N, which is respectively connected to the first preset end VA and the inverting input end (also called the negative input end) of the operational amplifier OP; the non-inverting input end (also called the positive input end) of the operational amplifier OP; used to access the reference voltage Vref, and the output end outputs the voltage Vout. Optionally, in the switch SW1 of the sampling and holding circuit, the voltage control end VM can be connected to the reference voltage Vref, that is, the preset voltage is the reference voltage Vref.
[0039] Figure 5The working modes of the sample-and-hold circuit shown include a sampling mode and a holding mode. In the sampling mode, SW1 and SW3 are turned on, and SW2 is turned off. The operational amplifier OP is in a unit gain negative feedback form, and the input signal Vin charges the capacitor C1. After stabilization, the voltage at the N terminal of the capacitor C1 and the output voltage Vout are equal to Vref. At this time, the substrate terminal Vbulkp of each PMOS tube in SW1 is connected to Vref, the substrate terminal Vbulkn of the NMOS is connected to the reference voltage Vref terminal, the voltage at the VA terminal (the first preset terminal VA) and the VB terminal (the second preset terminal VB) are close to Vref, and the switch conduction impedance is smaller.
[0040] In the hold mode, SW1 is disconnected first, followed by SW3, and finally SW2 is closed. At this time, there is no path to the N-terminal of capacitor C1, the charge in capacitor C1 is in a hold state, the voltage of the inverting input terminal of the operational amplifier OP is equal to Vref, and the voltages of VMP and VMN of SW1 are also equal to Vref, that is, there is no voltage difference between the source and drain of the first PMOS tube MP1 and the first NMN1 in SW1, and the leakage of the first PMOS tube MP1 and the first NMN1 will be extremely small, that is, the leakage of the N-terminal will also be extremely small. VMP and VMN are set to a fixed voltage Vref, and the change of the voltage at the VB terminal will not interfere with the VA terminal. At the same time, during the hold period, the substrate terminal Vbulkp of each PMOS tube in SW1 is connected to the power supply (power supply voltage VDD), and the substrate terminal Vbulkn of each NMOS tube is connected to the ground. When the output voltage Vout changes in the range between the ground and the power supply voltage VDD, it will not cause the conduction of the parasitic diodes of the second PMOS tube MP2 and the second NMOS tube MN2 in SW1, which will cause leakage of the N-terminal of capacitor C1.
[0041] The inventors conducted a comparative simulation analysis on a switch using a sample-and-hold circuit provided by any of the above embodiments (i.e., the switch of the present invention) and a conventional complementary switch. The simulation results can be referred to as Figure 6 As shown, Figure 6 Indicates that if Figure 5 The operational amplifier OP shown uses a conventional complementary MOS tube between the N-terminal and the output terminal. The voltage change during the hold phase (duration 427us) is approximately 14.7mV ( Figure 6 The dotted line portion shows that the voltage change in the holding phase (duration 427us) of the switch of the present invention is about 4.5mV. It can be seen that the voltage change in the holding phase of the switch of the present invention is small, and the leakage state is effectively improved.
[0042] The above sample-and-hold circuit, including the switch of the sample-and-hold circuit described in any of the above embodiments, has all the beneficial effects of the switch of the sample-and-hold circuit described in any of the above embodiments, which will not be described in detail here.
[0043] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementation of this specification shown herein.
[0044] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.
[0045] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0046] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.
Claims
1. A switch of a sample-and-hold circuit, characterized in that: The switch of the sample-and-hold circuit includes a first transmission switch module, a second transmission switch module and an auxiliary switch module; The first end of the first transmission switch module is connected to the first preset end of the sampling and holding circuit, and the second end is connected to the preset node; the first end of the second transmission switch module is connected to the preset node, and the second end is connected to the second preset end of the sampling and holding circuit; the first end of the auxiliary switch module is connected to the preset node, and the second end is connected to the voltage control end to access the voltage provided by the voltage control end, and the voltage control end is used to provide a voltage to the preset node to prevent the charge of the preset node from moving to both ends; The auxiliary switch module is used to close after the first transmission switch module and the second transmission switch module are disconnected, so that the preset node is connected to the voltage control end to prevent the charge from moving to the two ends.
2. The switch of the sample-and-hold circuit according to claim 1, characterized in that: The switch of the sampling and holding circuit also includes a control logic module; the control logic module is respectively connected to the control ends of the first transmission switch module, the second transmission switch module and the auxiliary switch module to control the on and off of the first transmission switch module, the second transmission switch module and the auxiliary switch module.
3. The switch of the sample-and-hold circuit according to claim 1, characterized in that: The first transmission switch module includes a first PMOS tube and a first NMOS tube; the second transmission switch module includes a second PMOS tube and a second NMOS tube; the preset node includes a first node and a second node; The gate of the first PMOS transistor is used to access the first control signal, the first end is connected to the first preset end, and the second end is connected to the first node; the gate of the first NMOS transistor is used to access the second control signal, the first end is connected to the first preset end, and the second end is connected to the second node; The gate of the second PMOS transistor is used to access the first control signal, the first end is connected to the first node, and the second end is connected to the second preset end; the gate of the second NMOS transistor is used to access the second control signal, the first end is connected to the second node, and the second end is connected to the second preset end; The first control signal and the second control signal are a pair of opposite control signals.
4. The switch of the sample-and-hold circuit according to claim 3, characterized in that: The auxiliary switch module includes a first switch and a second switch; The first end of the first switch is connected to the first node, and the second end is connected to the first end of the second switch and is used to access the voltage provided by the voltage control end; the second end of the second switch is the second node; The first switch and the second switch are respectively closed when the first control signal is at a high level, and opened when the first control signal is at a low level.
5. The switch of the sample-and-hold circuit according to claim 4, characterized in that: The switches of the sample-and-hold circuit further include a third switch, a fourth switch, a fifth switch and a sixth switch; The first end of the third switch is used to access the power supply voltage, and the second end is respectively connected to the first end of the fourth switch, the substrate end of the first PMOS tube and the substrate end of the second PMOS tube; the second end of the fourth switch is respectively connected to the first end of the fifth switch and the second end of the first switch; the second end of the fifth switch is respectively connected to the first end of the sixth switch, the substrate end of the first NMOS tube and the substrate end of the second NMOS tube; the second end of the sixth switch is grounded; The third switch and the sixth switch are respectively closed when the first control signal is at a high level, and are opened when the first control signal is at a low level; the fourth switch and the fifth switch are respectively closed when the second control signal is at a high level, and are opened when the second control signal is at a low level.
6. A sample-and-hold circuit, characterized in that: A switch comprising the sample-and-hold circuit according to any one of claims 1 to 5.
7. The sample-and-hold circuit according to claim 6, characterized in that: The sample-and-hold circuit further includes a seventh switch, an eighth switch, a capacitor and an operational amplifier; The first end of the eighth switch is used to access the input voltage, and the second end is respectively connected to the first end of the capacitor and the first end of the seventh switch; the second end of the seventh switch is respectively connected to the second preset end and the output end of the operational amplifier; the second end of the capacitor is respectively connected to the first preset end and the inverting input end of the operational amplifier; the non-inverting input end of the operational amplifier is used to access the reference voltage.