Switchable impedance matching circuit and plasma generating device

Abstract

The utility model discloses a switchable impedance matching circuit and a plasma generating device, and relates to the technical field of electrical control. The switchable impedance matching circuit is provided with a signal access end and a load access end, and comprises a main control circuit; the sampling circuit is used for collecting electric signals and feeding back to the main control circuit; the first impedance matching circuit is used for impedance matching of the first signal; the second impedance matching circuit is used for impedance matching of a second signal; the switch switching circuit is used for switching on a path between the first impedance matching circuit and the load access end and switching off a path between the second impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit; or the switching circuit is used for switching on the path between the second impedance matching circuit and the load access end and switching off the path between the first impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit. The utility model aims to improve the impedance matching speed and reduce the circuit volume.

Description

Technical Field

[0001] The utility model relates to the technical field of electrical control, in particular to a switchable impedance matching circuit and a plasma generating device. Background Art

[0002] RF power is the supporting power supply of plasma chamber, which is widely used in PECVD chemical vapor deposition, reactive ion etching and other fields. The overall architecture of RF plasma system includes RF power supply, impedance matcher and load. RF power supply outputs power signal to load after impedance matching through impedance matcher. However, the impedance matcher has the problems of slow matching speed and large size. Utility Model Content

[0003] The main purpose of the utility model is to provide a switchable impedance matching circuit, aiming to improve the speed of impedance matching and reduce the volume of the circuit.

[0004] To achieve the above-mentioned purpose, the utility model proposes a switchable impedance matching circuit, which is applied to a plasma generating device. The switchable impedance matching circuit is provided with a signal access terminal and a load access terminal, and the switchable impedance matching circuit includes:

[0005] Main control circuit;

[0006] A sampling circuit, wherein the input end of the sampling circuit is electrically connected to the signal access end and the load access end, the output end of the sampling circuit is electrically connected to the main control circuit, and the sampling circuit is used to collect electrical signals and feed them back to the main control circuit;

[0007] a first impedance matching circuit, wherein an input end of the first impedance matching circuit is electrically connected to the signal access end, and an output end of the first impedance matching circuit is electrically connected to the load access end; the first impedance matching circuit is used for impedance matching of a first signal;

[0008] a second impedance matching circuit, wherein an input end of the second impedance matching circuit is electrically connected to the signal access end, and an output end of the second impedance matching circuit is electrically connected to the load access end; the second impedance matching circuit is used for impedance matching of a second signal;

[0009] A switch switching circuit, wherein the input end of the switch switching circuit is electrically connected to the signal access end, the output end of the switch switching circuit is electrically connected to the first impedance matching circuit and the second impedance matching circuit, and the controlled end of the switch switching circuit is electrically connected to the main control circuit. The switch switching circuit is used to connect the path between the first impedance matching circuit and the load access end and disconnect the path between the second impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit; or to connect the path between the second impedance matching circuit and the load access end and disconnect the path between the first impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit.

[0010] In one embodiment, the sampling circuit includes:

[0011] a first sampling circuit, wherein an input end of the first sampling circuit is electrically connected to the signal access end, and an output end of the first sampling circuit is electrically connected to the main control circuit; the first sampling circuit is used to collect an electrical signal from the signal access end;

[0012] The second sampling circuit has an input terminal electrically connected to the load access terminal, and an output terminal electrically connected to the main control circuit; the second sampling circuit is used to collect an electrical signal from the load access terminal.

[0013] In one embodiment, the first sampling circuit and the second sampling circuit respectively include:

[0014] a first current sampling circuit, wherein an input end of the first current sampling circuit is electrically connected to the signal access end, and an output end of the first current sampling circuit is electrically connected to the main control circuit; the first current sampling circuit is used to collect a current signal at the signal access end;

[0015] a first voltage sampling circuit, wherein an input end of the first voltage sampling circuit is electrically connected to the signal access end, and an output end of the first voltage sampling circuit is electrically connected to the main control circuit; the first voltage sampling circuit is used to collect a voltage signal at the signal access end;

[0016] a second current sampling circuit, wherein the input end of the second current sampling circuit is electrically connected to the load access end, and the output end of the second current sampling circuit is electrically connected to the main control circuit; the second current sampling circuit is used to collect the current signal of the load access end;

[0017] A second voltage sampling circuit, wherein the input end of the second voltage sampling circuit is electrically connected to the load access end, and the output end of the second voltage sampling circuit is electrically connected to the main control circuit; the second voltage sampling circuit is used to collect the voltage signal of the load access end.

[0018] In one embodiment, the first current sampling circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a first operational amplifier; the second current sampling circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a second operational amplifier;

[0019] Wherein, the first end of the first resistor is electrically connected to the signal access end, and the second end of the first resistor is grounded; the first end of the second resistor is electrically connected to the first end of the first resistor, and the second end of the second resistor is electrically connected to the first end of the third resistor and the positive phase input end of the first operational amplifier; the second end of the third resistor is grounded; the first end of the fourth resistor is electrically connected to the second end of the first resistor, and the second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the inverting input end of the first operational amplifier; the second end of the fifth resistor is electrically connected to the output end of the first operational amplifier and the main control circuit; the first end of the sixth resistor is electrically connected to the load access end, and the second end of the sixth resistor is grounded; the first end of the seventh resistor is electrically connected to the first end of the sixth resistor, and the second end of the seventh resistor is electrically connected to the first end of the eighth resistor and the positive phase input end of the second operational amplifier; the second end of the eighth resistor is grounded; the first end of the ninth resistor is electrically connected to the second end of the sixth resistor, and the second end of the ninth resistor is electrically connected to the first end of the tenth resistor and the inverting input end of the second operational amplifier; the second end of the tenth resistor is electrically connected to the output end of the second operational amplifier and the main control circuit.

[0020] In one embodiment, the first voltage sampling circuit includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a third operational amplifier, a first capacitor, and a second capacitor; the second voltage sampling circuit includes a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a fourth operational amplifier, a third capacitor, and a fourth capacitor;

[0021] Wherein, the first end of the eleventh resistor is electrically connected to the signal access end, the second end of the eleventh resistor is electrically connected to the first end of the twelfth resistor and the first end of the thirteenth resistor; the second end of the twelfth resistor is grounded; the second end of the thirteenth resistor is electrically connected to the first end of the first capacitor and the non-inverting input end of the third operational amplifier; the second end of the first capacitor is grounded; the inverting input end of the third operational amplifier is electrically connected to the output end of the third operational amplifier and the first end of the fourteenth resistor; the second end of the fourteenth resistor is electrically connected to the first end of the second capacitor and the main control circuit; the second end of the second capacitor is connected to the ground; the first end of the fifteenth resistor is electrically connected to the load access end, the second end of the fifteenth resistor is electrically connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor; the second end of the sixteenth resistor is grounded; the second end of the seventeenth resistor is electrically connected to the first end of the third capacitor and the non-inverting input end of the fourth operational amplifier; the second end of the third capacitor is grounded; the inverting input end of the fourth operational amplifier is electrically connected to the output end of the fourth operational amplifier and the first end of the eighteenth resistor; the second end of the eighteenth resistor is electrically connected to the first end of the fourth capacitor and the main control circuit; the second end of the fourth capacitor is grounded.

[0022] In one embodiment, the first impedance matching circuit is an L-type impedance matching network; and the second impedance matching circuit is a π-type impedance matching network.

[0023] In one embodiment, the switch switching circuit includes:

[0024] a first switch circuit, wherein an input end of the first switch circuit is electrically connected to the signal access end, an output end of the first switch circuit is electrically connected to the first impedance matching circuit, and a controlled end of the first switch circuit is electrically connected to the main control circuit;

[0025] a second switch circuit, wherein an input end of the second switch circuit is electrically connected to the signal access end, an output end of the second switch circuit is electrically connected to the second impedance matching circuit, and a controlled end of the second switch circuit is electrically connected to the main control circuit;

[0026] Among them, the first switching circuit is used to turn on or off the path between the first impedance matching circuit and the signal access end according to the first switching signal output by the main control circuit; the second switching circuit is used to turn on or off the path between the second impedance matching circuit and the signal access end according to the second switching signal output by the main control circuit.

[0027] In one embodiment, the switch switching circuit also includes an inverting circuit, the input end of the inverting circuit is electrically connected to the output end of the main control circuit, and the output end of the inverting circuit is electrically connected to the controlled end of the first switch circuit or the second switch circuit; the inverting circuit is used to output an inverting signal to make the first switch circuit and the second switch circuit be in an on state and an off state respectively.

[0028] The utility model also provides a plasma generating device, wherein the plasma generating device comprises a switchable impedance matching circuit as described in any one of the above items.

[0029] The technical solution of the utility model effectively improves the speed of impedance matching and reduces the volume of the circuit by adopting a switchable impedance matching circuit. The signal access terminal and the load access terminal are sampled by a sampling circuit, and the sampled signal is fed back to the main control circuit. The main control circuit identifies the sampled signal and outputs a control signal to the switch switching circuit, thereby controlling whether the path between the signal access terminal and the load access terminal is through the first impedance matching circuit or the second impedance matching circuit, thereby achieving impedance matching between the signal access terminal and the load access terminal under different conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0031] Figure 1 It is a module schematic diagram of the switchable impedance matching circuit of the utility model;

[0032] Figure 2 A schematic diagram of a module of an embodiment of a switchable impedance matching circuit of the utility model;

[0033] Figure 3 This is a circuit structure diagram of an embodiment of a switchable impedance matching circuit of the utility model;

[0034] Figure 4 This is a circuit structure diagram of another embodiment of the switchable impedance matching circuit of the utility model;

[0035] Figure 5 This is a circuit structure diagram of another embodiment of the switchable impedance matching circuit of the utility model;

[0036] Figure 6 This is a circuit structure diagram of another embodiment of the switchable impedance matching circuit of the utility model.

[0037] 10. Main control circuit; 20. Sampling circuit; 21. First voltage sampling circuit; 22. First current sampling circuit; 23. Second current sampling circuit; 24. Second voltage sampling circuit; 30. First impedance matching circuit; 40. Second impedance matching circuit; 50. Switching circuit; 51. First switch circuit; 52. Second switch circuit; R1-R18, first resistor to eighteenth resistor; C1-C4, first capacitor to fourth capacitor.

[0038] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0040] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0041] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.

[0042] refer to Figures 1 to 6 The utility model proposes a switchable impedance matching circuit, which is applied to a plasma generating device. The switchable impedance matching circuit is provided with a signal access terminal and a load access terminal. The switchable impedance matching circuit includes:

[0043] Main control circuit 10;

[0044] A sampling circuit 20, wherein the input end of the sampling circuit 20 is electrically connected to the signal access end and the load access end, and the output end of the sampling circuit 20 is electrically connected to the main control circuit 10. The sampling circuit 20 is used to collect electrical signals and feed them back to the main control circuit 10;

[0045] A first impedance matching circuit 30, wherein an input end of the first impedance matching circuit 30 is electrically connected to a signal access end, and an output end of the first impedance matching circuit 30 is electrically connected to a load access end; the first impedance matching circuit 30 is used for impedance matching of a first signal;

[0046] A second impedance matching circuit 40, wherein an input end of the second impedance matching circuit 40 is electrically connected to the signal access end, and an output end of the second impedance matching circuit 40 is electrically connected to the load access end; the second impedance matching circuit 40 is used for impedance matching of a second signal;

[0047] A switch switching circuit 50, wherein the input end of the switch switching circuit 50 is electrically connected to the signal access end, the output end of the switch switching circuit 50 is electrically connected to the first impedance matching circuit 30 and the second impedance matching circuit 40, and the controlled end of the switch switching circuit 50 is electrically connected to the main control circuit 10. The switch switching circuit 50 is used to connect the path between the first impedance matching circuit 30 and the load access end and disconnect the path between the second impedance matching circuit 40 and the load access end according to the switch switching signal output by the main control circuit 10; or to connect the path between the second impedance matching circuit 40 and the load access end and disconnect the path between the first impedance matching circuit 30 and the load access end according to the switch switching signal output by the main control circuit 10.

[0048] In this embodiment, the main control circuit 10 can be implemented by PLC (Programmable Logic Controller), MCU (Microcontroller Unit), DSP (Digital Signal Process), FPGA (Field Programmable Gate Array), SOC (System On Chip), etc. Among them, the main control circuit 10 outputs a corresponding control signal to the switch switching circuit 50 by acquiring the output electrical signal of the sampling circuit 20, so that the switch switching circuit 50 performs a corresponding action. Specifically, the main control circuit 10 acquires the output electrical signal of the sampling circuit 20, and determines the state of the current signal access terminal and the load access terminal through digital-to-analog conversion, and outputs a corresponding control signal to the switch switching circuit 50, thereby controlling the conduction and disconnection of the switch switching circuit 50. The main control circuit 10 controls the conduction and disconnection of the switch switching circuit 50, thereby controlling whether the path between the signal access terminal and the load access terminal is through the first impedance matching circuit 30 or the second impedance matching circuit 40.

[0049] In this embodiment, the sampling circuit 20 includes a first sampling circuit, the input end of the first sampling circuit is electrically connected to the signal access end, and the output end of the first sampling circuit is electrically connected to the main control circuit 10; the first sampling circuit is used to collect the electrical signal of the signal access end; the second sampling circuit, the input end of the second sampling circuit is electrically connected to the load access end, and the output end of the second sampling circuit is electrically connected to the main control circuit 10; the second sampling circuit is used to collect the electrical signal of the load access end. The first sampling circuit and the second sampling circuit respectively include:

[0050] A first current sampling circuit 22, the input end of the first current sampling circuit 22 is electrically connected to the signal access end, and the output end of the first current sampling circuit 22 is electrically connected to the main control circuit 10; the first current sampling circuit 22 is used to collect the current signal of the signal access end; a first voltage sampling circuit 21, the input end of the first voltage sampling circuit 21 is electrically connected to the signal access end, and the output end of the first voltage sampling circuit 21 is electrically connected to the main control circuit 10; the first voltage sampling circuit 21 is used to collect the voltage signal of the signal access end.

[0051] A second current sampling circuit 23, the input end of the second current sampling circuit 23 is electrically connected to the load access end, and the output end of the second current sampling circuit 23 is electrically connected to the main control circuit 10; the second current sampling circuit 23 is used to collect the current signal of the load access end; a second voltage sampling circuit 24, the input end of the second voltage sampling circuit 24 is electrically connected to the load access end, and the output end of the second voltage sampling circuit 24 is electrically connected to the main control circuit 10; the second voltage sampling circuit 24 is used to collect the voltage signal of the load access end.

[0052] Further, the first current sampling circuit 22 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first operational amplifier; the second current sampling circuit 23 includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a second operational amplifier;

[0053] Among them, the first end of the first resistor R1 is electrically connected to the signal access end, and the second end of the first resistor R1 is grounded; the first end of the second resistor R2 is electrically connected to the first end of the first resistor R1, and the second end of the second resistor R2 is electrically connected to the first end of the third resistor R3 and the positive input end of the first operational amplifier; the second end of the third resistor R3 is grounded; the first end of the fourth resistor R4 is electrically connected to the second end of the first resistor R1, and the second end of the fourth resistor R4 is electrically connected to the first end of the fifth resistor R5 and the inverting input end of the first operational amplifier; the second end of the fifth resistor R5 is electrically connected to the output end of the first operational amplifier and the main control circuit 10 ; The first end of the sixth resistor R6 is electrically connected to the load access end, and the second end of the sixth resistor R6 is grounded; the first end of the seventh resistor R7 is electrically connected to the first end of the sixth resistor R6, and the second end of the seventh resistor R7 is electrically connected to the first end of the eighth resistor R8 and the non-inverting input end of the second operational amplifier; the second end of the eighth resistor R8 is grounded; the first end of the ninth resistor R9 is electrically connected to the second end of the sixth resistor R6, and the second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10 and the inverting input end of the second operational amplifier; the second end of the tenth resistor R10 is electrically connected to the output end of the second operational amplifier and the main control circuit 10.

[0054] The first voltage sampling circuit 21 includes an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a third operational amplifier, a first capacitor C1, and a second capacitor C2; the second voltage sampling circuit 24 includes a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a fourth operational amplifier, a third capacitor C3, and a fourth capacitor C4;

[0055] Among them, the first end of the eleventh resistor R11 is electrically connected to the signal access end, the second end of the eleventh resistor R11 is electrically connected to the first end of the twelfth resistor R12 and the first end of the thirteenth resistor R13; the second end of the twelfth resistor R12 is grounded; the second end of the thirteenth resistor R13 is electrically connected to the first end of the first capacitor C1 and the positive input end of the third operational amplifier; the second end of the first capacitor C1 is grounded; the inverting input end of the third operational amplifier is electrically connected to the output end of the third operational amplifier and the first end of the fourteenth resistor R14; the second end of the fourteenth resistor R14 is electrically connected to the first end of the second capacitor C2 and the main control circuit 10; the second end of the second capacitor C2 is connected to ground; the first end of the fifteenth resistor R15 is electrically connected to the load access end, the second end of the fifteenth resistor R15 is electrically connected to the first end of the sixteenth resistor R16 and the first end of the seventeenth resistor R17; the second end of the sixteenth resistor R16 is grounded; the second end of the seventeenth resistor R17 is electrically connected to the first end of the third capacitor C3 and the non-inverting input end of the fourth operational amplifier; the second end of the third capacitor C3 is grounded; the inverting input end of the fourth operational amplifier is electrically connected to the output end of the fourth operational amplifier and the first end of the eighteenth resistor R18; the second end of the eighteenth resistor R18 is electrically connected to the first end of the fourth capacitor C4 and the main control circuit 10; the second end of the fourth capacitor C4 is grounded.

[0056] It can be understood that the structures of the first current sampling circuit 22 and the first voltage sampling circuit 21 in the first sampling circuit 20 are consistent with the second current sampling circuit 23 and the second voltage sampling circuit 24 in the second sampling circuit 20, thereby effectively avoiding the accuracy deviation of the sampling result caused by the inconsistent circuit structure. Take the first current sampling circuit as an example. When the signal access end is turned on, when the current starts to flow through the first resistor R1, a voltage drop V1 will be generated between the first end of the first resistor R1 and the first end of the second resistor. Among them, the positive input terminal of the first operational amplifier is connected to the second end of the second resistor R2, so it will detect the voltage of V1. After the current starts to flow through the first resistor R1, a voltage drop V2 will be generated between the second end of the first resistor R1 and the first end of the fourth resistor R4. Among them, the inverting input terminal of the second operational amplifier is connected to the second end of the fourth resistor R4, so it will detect the voltage of V2. The operational amplifier is a high-gain device, and its output voltage VOUT is set to minimize the voltage difference between the positive input terminal and the negative input terminal. In this way, the operational amplifier can adjust its output to keep the voltage difference between the positive input terminal and the negative input terminal to a minimum. Among them, VOUT=R3 / R2(V1-V2), and V1-V2=I*R1, and the current in the circuit can be sampled by conversion.

[0057] Take the first voltage sampling circuit 21 as an example. After the input signal is divided by the eleventh resistor R11, it is connected in parallel with the thirteenth resistor R13 to adjust the size of the input signal so as to adapt to the input range of the operational amplifier. The adjusted input signal enters the non-inverting input terminal of the third operational amplifier through the thirteenth resistor R13. Among them, the third operational amplifier is a non-inverting operational amplifier, and its output voltage is in phase and equal to the input voltage. Therefore, the output voltage of the operational amplifier is in phase and equal to the input voltage. After the output voltage passes through the second filtering, it is output to the main control circuit 10. The function of the second capacitor C2 is to filter out high-frequency noise and ensure the accuracy of the sampling of the main control circuit 10. The fourteenth resistor R14 and the second capacitor C2 constitute an RC low-pass filter, which can further filter out high-frequency noise and improve signal quality. The fourteenth resistor R14 and the second capacitor C2 also constitute an RC time constant, which determines the cut-off frequency of the filter. The lower the cut-off frequency, the better the filtering effect, but the response speed will also be slower. The value of the fourteenth resistor R14 and the second capacitor C2 can be adjusted according to actual needs to achieve the best filtering effect and response speed. The twelfth resistor R12 and the first capacitor C1 form an RC filter for suppressing power supply noise. Power supply noise may affect the performance of the operational amplifier, so it needs to be suppressed. The values ​​of the twelfth resistor R12 and the first capacitor C1 can also be adjusted according to actual needs to achieve the best filtering effect and response speed.

[0058] In this embodiment, the first impedance matching circuit 30 is an L-type impedance matching network; the second impedance matching circuit 40 is a π-type impedance matching network. Among them, the L-type impedance matching network consists of a series element (usually an inductor) and a parallel element (usually a capacitor), and its shape is similar to the letter "L". This type of network usually contains two degrees of freedom, and the impedance matching characteristics of the network can be changed by adjusting the values ​​of the inductor and the capacitor. However, the L-type impedance matching network is only suitable for applications with a relatively single frequency or a narrow bandwidth. The π-type matching network consists of two series elements (usually the first one is a capacitor, and the second one is an inductor L or a capacitor) and a middle parallel element (usually a capacitor or an inductor), and its shape is similar to the Greek letter "π". It has one more degree of freedom than the L-type and provides adjustment of three elements. It is suitable for wider frequency bands or situations where more precise matching is required. The main control circuit 10 determines whether the impedance matching effect of the currently turned-on circuit meets the circuit requirements through the electrical signal output by the sampling circuit 20. When the electrical signal output by the sampling circuit 20 indicates that the impedance matching effect between the signal source and the load is poor, the main control circuit 10 will output a control signal to the switch circuit 50 to change the path between the signal access terminal and the load access terminal, thereby changing the impedance matching effect between the signal source and the load.

[0059] In this embodiment, the switch switching circuit 50 can be implemented by a single-pole double-throw switch or multiple switch tubes. Specifically, the switch switching circuit 50 includes: a first switch circuit 51, the input end of the first switch circuit 51 is electrically connected to the signal access end, the output end of the first switch circuit 51 is electrically connected to the first impedance matching circuit 30, and the controlled end of the first switch circuit 51 is electrically connected to the main control circuit 10; a second switch circuit 52, the input end of the second switch circuit 52 is electrically connected to the load access end, the output end of the second switch circuit 52 is electrically connected to the second impedance matching circuit 40, and the controlled end of the second switch circuit 52 is electrically connected to the main control circuit 10; wherein the first switch circuit 51 is used to turn on or off the path between the first impedance matching circuit 30 and the signal access end according to the first switch signal output by the main control circuit 10; the second switch circuit 52 is used to turn on or off the path between the second impedance matching circuit 40 and the load access end according to the second switch signal output by the main control circuit 10. The first switch circuit 51 and the second switch circuit 52 can both be implemented by multiple switch tubes, such as MOS tubes, IGBT tubes, thyristors, triodes, power tubes, etc. The controlled ends of the first switch circuit 51 and the second switch circuit 52 are electrically connected to the main control circuit 10, and the path between the first impedance matching circuit 30 and the signal access end is turned on or off when the first switch signal is received, and the path between the second impedance matching circuit 40 and the signal access end is turned on or off when the second switch signal is received, thereby realizing the switching between the first impedance matching circuit 30 and the second impedance matching circuit 40.

[0060] Furthermore, the switch switching circuit 50 also includes an inverting circuit, the input end of the inverting circuit is electrically connected to the output end of the main control circuit 10, and the output end of the inverting circuit is electrically connected to the controlled end of the first switch circuit 51 or the second switch circuit 52; the inverting circuit is used to output an inverting signal to make the first switch circuit 51 and the second switch circuit 52 in the on state and the off state respectively.

[0061] In this embodiment, the inverting circuit can be implemented by an inverter. The inverter is electrically connected to the controlled end of the first switch circuit 51 or the second switch circuit 52, so that the control signals received by the first switch circuit 51 and the second switch circuit 52 are a set of opposite and synchronous signals, so that when the first switch circuit 51 is in the on state, the second switch circuit 52 is in the off state, effectively ensuring that only one set of the first switch circuit 51 and the second switch circuit 52 is in the on state.

[0062] The signal access terminal and the load access terminal are sampled by the sampling circuit 20, and the sampled signal is fed back to the main control circuit 10. The main control circuit 10 identifies the sampled signal and outputs a control signal to the switch circuit 40, thereby controlling whether the path between the signal access terminal and the load access terminal passes through the first impedance matching circuit 30 or the second impedance matching circuit 40, thereby achieving impedance matching between the signal access terminal and the load access terminal under different conditions, improving the speed of impedance matching and reducing the circuit volume.

[0063] The utility model also provides a plasma generating device, which includes a switchable impedance matching circuit as described above. It is worth noting that since the plasma generating device of the utility model is based on the switchable impedance matching circuit described above, the embodiments of the plasma generating device of the utility model include all technical solutions of all embodiments of the switchable impedance matching circuit described above, and the technical effects achieved are also exactly the same, which will not be repeated here.

[0064] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A switchable impedance matching circuit, wherein the switchable impedance matching circuit is applied to a plasma generating device, characterized in that: The switchable impedance matching circuit is provided with a signal access terminal and a load access terminal, and the switchable impedance matching circuit comprises: Main control circuit; A sampling circuit, wherein the input end of the sampling circuit is electrically connected to the signal access end and the load access end, the output end of the sampling circuit is electrically connected to the main control circuit, and the sampling circuit is used to collect electrical signals and feed them back to the main control circuit; a first impedance matching circuit, wherein an input end of the first impedance matching circuit is electrically connected to the signal access end, and an output end of the first impedance matching circuit is electrically connected to the load access end; the first impedance matching circuit is used for impedance matching of a first signal; a second impedance matching circuit, wherein an input end of the second impedance matching circuit is electrically connected to the signal access end, and an output end of the second impedance matching circuit is electrically connected to the load access end; the second impedance matching circuit is used for impedance matching of a second signal; A switch switching circuit, wherein the input end of the switch switching circuit is electrically connected to the signal access end, the output end of the switch switching circuit is electrically connected to the first impedance matching circuit and the second impedance matching circuit, and the controlled end of the switch switching circuit is electrically connected to the main control circuit. The switch switching circuit is used to connect the path between the first impedance matching circuit and the load access end and disconnect the path between the second impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit; or to connect the path between the second impedance matching circuit and the load access end and disconnect the path between the first impedance matching circuit and the load access end according to the switch switching signal output by the main control circuit.

2. The switchable impedance matching circuit according to claim 1, wherein: The sampling circuit comprises: a first sampling circuit, wherein an input end of the first sampling circuit is electrically connected to the signal access end, and an output end of the first sampling circuit is electrically connected to the main control circuit; the first sampling circuit is used to collect an electrical signal from the signal access end; The second sampling circuit has an input terminal electrically connected to the load access terminal, and an output terminal electrically connected to the main control circuit; the second sampling circuit is used to collect an electrical signal from the load access terminal.

3. The switchable impedance matching circuit according to claim 2, wherein: The first sampling circuit and the second sampling circuit respectively include: a first current sampling circuit, wherein an input end of the first current sampling circuit is electrically connected to the signal access end, and an output end of the first current sampling circuit is electrically connected to the main control circuit; the first current sampling circuit is used to collect a current signal at the signal access end; a first voltage sampling circuit, wherein an input end of the first voltage sampling circuit is electrically connected to the signal access end, and an output end of the first voltage sampling circuit is electrically connected to the main control circuit; the first voltage sampling circuit is used to collect a voltage signal at the signal access end; a second current sampling circuit, wherein the input end of the second current sampling circuit is electrically connected to the load access end, and the output end of the second current sampling circuit is electrically connected to the main control circuit; the second current sampling circuit is used to collect the current signal of the load access end; A second voltage sampling circuit, wherein the input end of the second voltage sampling circuit is electrically connected to the load access end, and the output end of the second voltage sampling circuit is electrically connected to the main control circuit; the second voltage sampling circuit is used to collect the voltage signal of the load access end.

4. The switchable impedance matching circuit according to claim 3, wherein: The first current sampling circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a first operational amplifier; the second current sampling circuit includes a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a second operational amplifier; Wherein, the first end of the first resistor is electrically connected to the signal access end, and the second end of the first resistor is grounded; the first end of the second resistor is electrically connected to the first end of the first resistor, and the second end of the second resistor is electrically connected to the first end of the third resistor and the positive phase input end of the first operational amplifier; the second end of the third resistor is grounded; the first end of the fourth resistor is electrically connected to the second end of the first resistor, and the second end of the fourth resistor is electrically connected to the first end of the fifth resistor and the inverting input end of the first operational amplifier; the second end of the fifth resistor is electrically connected to the output end of the first operational amplifier and the main control circuit; the first end of the sixth resistor is electrically connected to the load access end, and the second end of the sixth resistor is grounded; the first end of the seventh resistor is electrically connected to the first end of the sixth resistor, and the second end of the seventh resistor is electrically connected to the first end of the eighth resistor and the positive phase input end of the second operational amplifier; the second end of the eighth resistor is grounded; the first end of the ninth resistor is electrically connected to the second end of the sixth resistor, and the second end of the ninth resistor is electrically connected to the first end of the tenth resistor and the inverting input end of the second operational amplifier; the second end of the tenth resistor is electrically connected to the output end of the second operational amplifier and the main control circuit.

5. The switchable impedance matching circuit according to claim 3, wherein: The first voltage sampling circuit includes an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a third operational amplifier, a first capacitor, and a second capacitor; the second voltage sampling circuit includes a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a fourth operational amplifier, a third capacitor, and a fourth capacitor; Wherein, the first end of the eleventh resistor is electrically connected to the signal access end, the second end of the eleventh resistor is electrically connected to the first end of the twelfth resistor and the first end of the thirteenth resistor; the second end of the twelfth resistor is grounded; the second end of the thirteenth resistor is electrically connected to the first end of the first capacitor and the non-inverting input end of the third operational amplifier; the second end of the first capacitor is grounded; the inverting input end of the third operational amplifier is electrically connected to the output end of the third operational amplifier and the first end of the fourteenth resistor; the second end of the fourteenth resistor is electrically connected to the first end of the second capacitor and the main control circuit; the second end of the second capacitor is connected to the ground; the first end of the fifteenth resistor is electrically connected to the load access end, the second end of the fifteenth resistor is electrically connected to the first end of the sixteenth resistor and the first end of the seventeenth resistor; the second end of the sixteenth resistor is grounded; the second end of the seventeenth resistor is electrically connected to the first end of the third capacitor and the non-inverting input end of the fourth operational amplifier; the second end of the third capacitor is grounded; the inverting input end of the fourth operational amplifier is electrically connected to the output end of the fourth operational amplifier and the first end of the eighteenth resistor; the second end of the eighteenth resistor is electrically connected to the first end of the fourth capacitor and the main control circuit; the second end of the fourth capacitor is grounded.

6. The switchable impedance matching circuit according to claim 1, wherein: The first impedance matching circuit is an L-type impedance matching network; the second impedance matching circuit is a π-type impedance matching network.

7. The switchable impedance matching circuit according to claim 1, wherein: The switch switching circuit comprises: a first switch circuit, wherein an input end of the first switch circuit is electrically connected to the signal access end, an output end of the first switch circuit is electrically connected to the first impedance matching circuit, and a controlled end of the first switch circuit is electrically connected to the main control circuit; a second switch circuit, wherein an input end of the second switch circuit is electrically connected to the signal access end, an output end of the second switch circuit is electrically connected to the second impedance matching circuit, and a controlled end of the second switch circuit is electrically connected to the main control circuit; Among them, the first switching circuit is used to turn on or off the path between the first impedance matching circuit and the signal access end according to the first switching signal output by the main control circuit; the second switching circuit is used to turn on or off the path between the second impedance matching circuit and the signal access end according to the second switching signal output by the main control circuit.

8. The switchable impedance matching circuit according to claim 7, wherein: The switch switching circuit also includes an inverting circuit, the input end of the inverting circuit is electrically connected to the output end of the main control circuit, and the output end of the inverting circuit is electrically connected to the controlled end of the first switch circuit or the second switch circuit; the inverting circuit is used to output an inverting signal to make the first switch circuit and the second switch circuit in an on state and an off state respectively.

9. A plasma generating device, characterized in that: The plasma generating device comprises the switchable impedance matching circuit according to any one of claims 1 to 8.

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