Pulse signal self-locking circuit

Abstract

The utility model discloses a pulse signal self-locking circuit. The pulse signal self-locking circuit comprises a signal input device and a comparator, wherein the signal input device is provided with two input ends and one output end; the output end of the signal input device is connected with one input end of the comparator, and one input end of the signal input device is connected with the output end of the comparator. In the signal input device, the input end connected with the output end of the comparator is connected with a comparison signal, the other input end is connected with a pulse signal, and the output end outputs a setting signal. In the comparator, the input end connected with the output end of the signal input device is connected with a setting signal, the other input end is connected with a reference voltage, and the output end outputs a comparison signal. The circuit supports the comparator to keep level output in one state according to the setting signal, and self-locking is achieved. And when the reset signal is received, the comparator changes the state of the output level. Compared with a trigger, the cost is lower, the required space is smaller, and the logic is simpler.

Description

Technical Field

[0001] The present application relates to the technical field of self-locking circuits, and in particular to a pulse signal self-locking circuit. Background Art

[0002] Self-locking means that after pressing the start button, the contactor coil is continuously energized to keep the contact point connected. In layman's terms, pressing the button makes the motor run, and when the button is released, the motor is still in operation.

[0003] The self-locking circuit in the prior art is mostly composed of a trigger, which has two stable states: set and clear. When the input end of the trigger receives a set signal, its output end will maintain a high level state until a clear signal is received. When the input end of the trigger receives a clear signal, its output end will maintain a low level state until a set signal is received. In a self-locking circuit, a trigger is usually used to store the output state of the circuit and feed it back to the input end of the circuit to achieve a self-locking function. However, the self-locking circuit using a trigger is costly, requires a large space, and has complex logic. Therefore, a low-cost, small-space, and simple-logic self-locking circuit is urgently needed to achieve a self-locking function. Utility Model Content

[0004] Based on the above problems, the present application provides a pulse signal self-locking circuit to achieve the self-locking function through a low-cost, small-space, and simple-logic self-locking circuit.

[0005] The present application discloses a pulse signal self-locking circuit, comprising: a signal input device having two input terminals and one output terminal and a comparator;

[0006] The output end of the signal input device is connected to an input end of the comparator, and one input end of the signal input device is connected to the output end of the comparator;

[0007] In the signal input device, the input terminal connected to the output terminal of the comparator receives the comparison signal, the other input terminal receives the pulse signal, and the output terminal outputs the set signal; the signal input device obtains the set signal according to the voltage values ​​of the comparison signal and the pulse signal;

[0008] In the comparator, the input terminal connected to the output terminal of the signal input device is connected to the setting signal, the other input terminal is connected to the reference voltage, and the output terminal outputs the comparison signal; the comparator outputs the comparison signal according to the voltage values ​​of the setting signal and the reference voltage;

[0009] The pulse signal self-locking circuit also includes:

[0010] A zeroing device, one input end of which is connected to a first node between the output end of the comparator and the input end of the signal input device, the other input end is connected to a zeroing signal, and the output end is grounded; the zeroing device is turned on in response to the zeroing signal to clear the comparison signal.

[0011] Optionally, the signal input device is used for:

[0012] In response to a voltage value of the comparison signal being greater than a voltage value of the pulse signal, using the comparison signal as the set signal;

[0013] In response to the voltage value of the comparison signal being smaller than the voltage value of the pulse signal, the pulse signal is used as the set signal.

[0014] Optionally, the comparison signal is a high level signal or a low level signal, and the comparator is used to:

[0015] In response to the voltage value of the set signal being greater than the voltage value of the reference voltage, outputting a high level signal;

[0016] In response to the voltage value of the set signal being lower than the voltage value of the reference voltage, a low level signal is output.

[0017] Optionally, the pulse signal self-locking circuit further includes: a reference voltage circuit composed of a first resistor and a second resistor;

[0018] One end of the first resistor is connected to the power supply voltage, and the other end is connected to the second resistor via a second node;

[0019] One end of the second resistor is grounded, and the other end is connected to the second node;

[0020] The first resistor and the second resistor are used to adjust the reference voltage;

[0021] The reference voltage circuit provides the reference voltage to the comparator through the second node.

[0022] Optionally, the reference voltage circuit further includes a first capacitor, one end of the first capacitor is grounded, and the other end is connected to the second node;

[0023] There is also a third node and a second capacitor between the output end of the signal input device and the input end of the comparator, one end of the second capacitor is grounded, and the other end is connected to the third node;

[0024] The first capacitor and the second capacitor are used to make the reference voltage enter the comparator later than the set signal.

[0025] Optionally, a first current limiting resistor is connected in series between the output end of the signal input device and the input end of the comparator.

[0026] Optionally, a fourth node and a pull-up resistor are provided between the output end of the comparator and the first node;

[0027] One end of the pull-up resistor is connected to the power supply voltage, and the other end is connected to the fourth node, for adjusting the comparison signal.

[0028] Optionally, a second current limiting resistor is connected in series between the fourth node and the first node.

[0029] Optionally, the signal input device is a dual-channel diode, or two diodes connected in parallel.

[0030] Optionally, the clearing device is a PDTC143ZT digital transistor.

[0031] The present application discloses a pulse signal self-locking circuit, including a signal input device with two input terminals and one output terminal and a comparator. The output terminal of the signal input device is connected to an input terminal of the comparator, and one input terminal of the signal input device is connected to the output terminal of the comparator. In the signal input device, the input terminal connected to the output terminal of the comparator is connected to the comparison signal, the other input terminal is connected to the pulse signal, and the output terminal outputs the set signal. In the comparator, the input terminal connected to the output terminal of the signal input device is connected to the set signal, the other input terminal is connected to the reference voltage, and the output terminal outputs the comparison signal. The circuit described in the present application supports the comparator to maintain a level output of a state according to the set signal to achieve self-locking. And when a reset signal is received, the comparator will change the state of the output level. The cost is lower than that of a trigger, the space required is smaller, and the logic is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of the structure of a pulse signal self-locking circuit disclosed in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the structure of a signal input device disclosed in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of the structure of a reference voltage circuit disclosed in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of the structure of the zeroing circuit disclosed in the embodiment of the present application;

[0037] Figure 5 This is a schematic diagram of the structure of another pulse signal self-locking circuit disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] Embodiment 1: The present application discloses a pulse signal self-locking circuit.

[0040] For details, please refer to Figure 1 A pulse signal self-locking circuit disclosed in this embodiment includes: a signal input device 101 having two input terminals and one output terminal and a comparator 102.

[0041] An output terminal c of the signal input device 101 is connected to an input terminal d of the comparator 102 , and an input terminal a of the signal input device 101 is connected to an output terminal f of the comparator 102 .

[0042] In the signal input device 101, the input terminal a connected to the output terminal f of the comparator 102 receives the comparison signal, the other input terminal b receives the pulse signal, and the output terminal c outputs the set signal. The signal input device 101 obtains the set signal according to the voltage values ​​of the comparison signal and the pulse signal.

[0043] In the circuit described in this embodiment, the signal input device 101 is used to: in response to the voltage value of the comparison signal being greater than the voltage value of the pulse signal, use the comparison signal as a set signal; in response to the voltage value of the comparison signal being less than the voltage value of the pulse signal, use the pulse signal as a set signal.

[0044] In actual operation, the signal input device 101 described in this embodiment will only receive a pulse signal in the initial state, and the signal input device 101 will use the pulse signal as a set signal. It should be noted that the pulse signal is a single high-level signal or a low-level signal, that is, the input terminal b only has this pulse signal this time, and there is no continuous pulse signal. Then the input terminal a will receive a comparison signal, and there is no signal at the input terminal b, so the signal input device 101 uses the comparison signal as a set signal. It should be noted that the comparison signal is a continuous high-level signal or a low-level signal, that is, the input terminal a always has the comparison signal. When the input terminal b receives a new pulse signal again, the signal input device 101 compares the new pulse signal with the comparison signal from the input terminal a, and selects the signal with the higher voltage value of the two signals as the set signal.

[0045] In the comparator 102, the input terminal d connected to the output terminal c of the signal input device 101 receives the setting signal, the other input terminal e receives the reference voltage, and the output terminal f outputs the comparison signal. The comparator 102 outputs the comparison signal according to the voltage values ​​of the setting signal and the reference voltage.

[0046] In the circuit described in this embodiment, the comparator 102 is used to: output a high level signal in response to the voltage value of the set signal being greater than the voltage value of the reference voltage, and output a low level signal in response to the voltage value of the set signal being less than the voltage value of the reference voltage.

[0047] In addition, the circuit described in this embodiment also includes a zeroing device 103. Figure 1 As shown, one input terminal h of the zeroing device 103 is connected to the first node between the output terminal f of the comparator 102 and the input terminal a of the signal input device 101, the other input terminal g is connected to the zeroing signal, and the output terminal i is grounded. The zeroing device 103 is turned on in response to the zeroing signal to clear the comparison signal.

[0048] Normally, the signal input device 101 and the comparator 102 are used in a self-locking circuit, and the reference voltage needs to be higher than the low-level pulse signal and the low-level comparison signal, and lower than the high-level pulse signal and the high-level comparison signal. For example, a low-level pulse signal (such as 1V) is input once, and the signal input device 101 outputs it as a set signal. Then the comparator 102 compares it with the reference voltage (such as 2v), determines that the voltage of the set signal is smaller, and outputs a low-level comparison signal (such as 1.5V). When the signal input device 101 receives a low-level comparison signal, it continues to output the comparison signal as a set signal, and the output of the comparator 102 always remains in a low-level state. A high-level pulse signal (such as 3V) is input again, and the signal input device 101 compares it with the low-level comparison signal, determines that the voltage of the high-level pulse signal is larger, and therefore outputs it as a new set signal. Then the comparator 102 compares it with the reference voltage, determines that the voltage of the set signal is larger, and outputs a high-level comparison signal (such as 2.5V). When the signal input device 101 receives a high-level comparison signal, it continues to output the comparison signal as a set signal, and the output of the comparator 102 always maintains a high-level state. When the zeroing device 103 receives a zeroing signal, it will be turned on, so that a part of the high-level comparison signal is output to the ground terminal i through the first node and the zeroing device 103, thereby reducing the voltage of the high-level comparison signal. The zeroing device 103 can reduce the voltage of the comparison signal received by the signal input device 101, and use it as a set signal, so that the output of the comparator 102 always maintains a low-level state. So far, the self-locking circuit described in this embodiment realizes the self-locking function through the signal input device 101 and the comparator 102, and realizes the unlocking function through the zeroing device 103.

[0049] Embodiment 2: The present application discloses a signal input device in a pulse signal self-locking circuit. Figure 2 Schematic diagram of the structure of the signal input device disclosed in the embodiment of the present application. Figure 2 As shown:

[0050] In the circuit described in this embodiment, the signal input device is a dual-channel diode, or two diodes in parallel. The two input ends of the dual-channel diode, or the input ends of the two diodes, are a and b respectively. The output end of the dual-channel diode, or the node where the output ends of the two diodes are connected in parallel, is c. The signal input device described in this embodiment can isolate the input of the two groups of signals to prevent interference between them, and can also compare the voltage values ​​of the signals in the input ends a and b, and output the signal with the larger voltage value from the output end (or node) c.

[0051] Embodiment 3: This application discloses a reference voltage circuit in a pulse signal self-locking circuit. Figure 3Schematic diagram of the structure of the reference voltage circuit disclosed in the embodiment of the present application. Figure 3 As shown:

[0052] In the circuit described in this embodiment, the reference voltage circuit is composed of a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the power supply voltage VCC, and the other end is connected to the second resistor R2 through the second node P2. One end of the second resistor R2 is grounded GND, and the other end is connected to the second node P2. In the reference voltage circuit described in this embodiment, the first resistor R1 and the second resistor R2 are used to adjust the reference voltage, and the reference voltage circuit provides a reference voltage for the comparator through the second node P2.

[0053] Embodiment 4: This application discloses a zeroing circuit in a pulse signal self-locking circuit. Figure 4 Schematic diagram of the structure of the zeroing circuit disclosed in the embodiment of the present application. Figure 4 As shown:

[0054] In the zeroing circuit described in this embodiment, a zeroing device and a voltage-dividing resistor are included, which are used to adjust the comparison signal. An input terminal h of the zeroing device is connected to the first node P1, and another input terminal g is connected to the voltage-dividing resistor through the fifth node P5. One end of the voltage-dividing resistor is connected to the fifth node P5, and the other end is grounded. The fifth node P5 receives a high-level signal for turning on the zeroing device. The zeroing device can be a PDTC143ZT digital transistor.

[0055] Embodiment 5: This application discloses another pulse signal self-locking circuit. Figure 5 FIG. 1 is a schematic diagram of another pulse signal self-locking circuit disclosed in an embodiment of the present application. Figure 5 As shown:

[0056] In the reference voltage circuit A, a first resistor R1, a second resistor R2 and a first capacitor C1 are included. One end of R1 is connected to VCC, and the other end is connected to R2 through the second node P2. One end of R2 is grounded, and the other end is connected to P2. One end of C1 is grounded, and the other end is connected to P2. Among them, R1 and R2 can flexibly adjust the reference voltage, C1 is used to make the reference voltage enter the comparator later than the set signal, and the reference voltage circuit provides the reference voltage to the comparator through P2. Among them, R1 can be a 15KΩ resistor with an accuracy of 1%. R2 can be a 10KΩ resistor with an accuracy of 5%. C1 can be a 10nF capacitor with a withstand voltage of 50V.

[0057] In the signal input device part B, a first current limiting resistor R3 is connected in series between the output terminal c and the input terminal d of the comparator. There is a node connected to the voltage divider resistor R4 between the output terminal c and R3. There is also a third node P3 and a second capacitor C2 between the output terminal c of the signal input device and the input terminal d of the comparator. Specifically, P3 exists between the input terminal d and R3. One end of C2 is grounded and the other end is connected to P3. Its function is also to make the reference voltage enter the comparator later than the set signal. Among them, R3 can be a 10KΩ resistor with an accuracy of 5%. R4 can be a 200KΩ resistor with an accuracy of 5%. C2 can be a 47nF capacitor with a withstand voltage of 50V.

[0058] In the comparator part C, since the output of the comparator is in open-drain mode, it is impossible to truly output a high level, that is, there is no driving capability at a high level, so it is necessary to use a pull-up resistor to complete the external drive. There is also a fourth node P4 and a pull-up resistor R5 between the output terminal f of the comparator and the input terminal a of the signal input device. Specifically, there are P4 and R5 between the output terminal f and the first node P1. One end of R5 is connected to VCC (this power supply can be selected as the same power supply as the power supply), and the other end is connected to P4 for adjusting the comparison signal. There is also a second current limiting resistor R6 connected in series between P4 and the input terminal a, specifically, R6 is connected in series between P4 and P1. Among them, R5 can be a 4.7KΩ resistor with an accuracy of 5%. R6 can be a 1KΩ resistor with an accuracy of 5%.

[0059] In the zeroing circuit D, there is also P1 between R6 and the input terminal a, the input terminal h of the zeroing device is connected to P1, the input terminal g is connected to the zeroing signal, and the output terminal i is grounded, which is used to adjust the high-level comparison signal. When the comparator always outputs a high-level comparison signal, the zeroing device receives the zeroing signal (for example, a high-level signal) through the input terminal g, and the zeroing device is turned on in response to the zeroing signal. The input terminal h is connected to the high-level comparison signal and outputs it through the ground terminal i, thereby clearing (or reducing) the comparison signal to release the comparator output. In the circuit where the input terminal g is connected to the zeroing signal, there is also a node connected to the voltage divider resistor R7. Among them, R7 can be a 4.7KΩ resistor with an accuracy of 5%.

[0060] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0061] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0062] The features described in the embodiments of this specification can be replaced or combined with each other, so that professional and technical personnel in this field can implement or use the present application.

[0063] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse signal self-locking circuit, characterized in that: include: A signal input device and a comparator having two input terminals and one output terminal; The output end of the signal input device is connected to an input end of the comparator, and one input end of the signal input device is connected to the output end of the comparator; In the signal input device, the input terminal connected to the output terminal of the comparator receives the comparison signal, the other input terminal receives the pulse signal, and the output terminal outputs the set signal; the signal input device obtains the set signal according to the voltage values ​​of the comparison signal and the pulse signal; In the comparator, the input terminal connected to the output terminal of the signal input device is connected to the setting signal, the other input terminal is connected to the reference voltage, and the output terminal outputs the comparison signal; The comparator outputs the comparison signal according to the voltage value of the setting signal and the reference voltage; The pulse signal self-locking circuit also includes: A zeroing device, one input end of which is connected to a first node between the output end of the comparator and the input end of the signal input device, the other input end is connected to a zeroing signal, and the output end is grounded; the zeroing device is turned on in response to the zeroing signal to clear the comparison signal.

2. The pulse signal self-locking circuit according to claim 1, characterized in that: The signal input device is used for: In response to a voltage value of the comparison signal being greater than a voltage value of the pulse signal, using the comparison signal as the set signal; In response to the voltage value of the comparison signal being smaller than the voltage value of the pulse signal, the pulse signal is used as the set signal.

3. The pulse signal self-locking circuit according to claim 1, characterized in that: The comparison signal is a high level signal or a low level signal, and the comparator is used for: In response to the voltage value of the set signal being greater than the voltage value of the reference voltage, outputting a high level signal; In response to the voltage value of the set signal being lower than the voltage value of the reference voltage, a low level signal is output.

4. The pulse signal self-locking circuit according to claim 1, characterized in that: Also includes: A reference voltage circuit composed of a first resistor and a second resistor; One end of the first resistor is connected to the power supply voltage, and the other end is connected to the second resistor via a second node; One end of the second resistor is grounded, and the other end is connected to the second node; The first resistor and the second resistor are used to adjust the reference voltage; The reference voltage circuit provides the reference voltage to the comparator through the second node.

5. The pulse signal self-locking circuit according to claim 4, characterized in that: The reference voltage circuit further includes a first capacitor, one end of which is grounded and the other end of which is connected to the second node; There is also a third node and a second capacitor between the output end of the signal input device and the input end of the comparator, one end of the second capacitor is grounded, and the other end is connected to the third node; The first capacitor and the second capacitor are used to make the reference voltage enter the comparator later than the set signal.

6. The pulse signal self-locking circuit according to claim 1, characterized in that: A first current limiting resistor is also connected in series between the output end of the signal input device and the input end of the comparator.

7. The pulse signal self-locking circuit according to claim 1, characterized in that: There is also a fourth node and a pull-up resistor between the output end of the comparator and the first node; One end of the pull-up resistor is connected to the power supply voltage, and the other end is connected to the fourth node, for adjusting the comparison signal.

8. The pulse signal self-locking circuit according to claim 7, characterized in that: A second current limiting resistor is also connected in series between the fourth node and the first node.

9. The pulse signal self-locking circuit according to claim 1, characterized in that: The signal input device is a dual-channel diode, or two diodes connected in parallel.

10. The pulse signal self-locking circuit according to claim 1, characterized in that: The zeroing device is a PDTC143ZT digital transistor.

Images