Integrated circuit structure with efficient heat dissipation

Abstract

The utility model relates to the technical field of chip packaging, and particularly discloses an integrated circuit structure with efficient heat dissipation, which comprises a BT substrate, a plurality of units are arranged on the BT substrate, each unit comprises a metal carrier, a bonding wire pad, an SMT pad and a heat dissipation sheet, the metal carrier and the bonding wire pad are arranged on the front surface of the BT substrate, and the SMT pad and the heat dissipation sheet are arranged on the back surface of the BT substrate. Each unit further comprises a plurality of outer via holes and inner via holes which are arranged in the BT substrate, the outer via holes are used for realizing communication between a bonding wire bonding pad and an SMT bonding pad, the inner via holes are used for realizing communication between a cooling fin and a metal carrier, and cooling lines are arranged on the cooling fin; according to the utility model, through the via holes on the BT substrate, communication between the radiating fins and the metal carrier on the front surface of the substrate is realized. The via holes are like small bridges, and the radiating fins are connected with the metal carrier on the front side of the substrate, so that a continuous radiating path is formed.

Description

Technical Field

[0001] The utility model belongs to the technical field of chip packaging, and in particular relates to an integrated circuit structure with high-efficiency heat dissipation. Background Art

[0002] With the rapid development of electronic technology, the integration and operating frequency of integrated circuits continue to increase, resulting in an increase in power consumption. The high heat problem caused by high power consumption has become a key factor restricting the further improvement of integrated circuit performance. In order to solve this problem, efficient heat dissipation technology has become an important research field in integrated circuit design.

[0003] The existing integrated circuit packaging process is complex, has low heat dissipation efficiency, and has certain limitations in use. Utility Model Content

[0004] The purpose of the utility model is to provide an integrated circuit structure with high efficiency in heat dissipation, so as to solve the problems raised in the above-mentioned background technology.

[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0006] An integrated circuit structure with high efficiency in heat dissipation, comprising:

[0007] A BT substrate, wherein a plurality of units are arranged on the BT substrate, each unit includes a metal carrier arranged on the front side of the BT substrate, a wire bonding pad, an SMT pad and a heat sink arranged on the back side of the BT substrate, each unit also includes a plurality of external vias and internal vias arranged inside the BT substrate, the external vias are used to achieve connectivity between the wire bonding pad and the SMT pad, the internal vias are used to achieve connectivity between the heat sink and the metal carrier, and the heat sink is provided with heat dissipation patterns.

[0008] Preferably, solder resist ink is provided on the front and back of the BT substrate, and a direction mark is also provided on the back of the BT substrate.

[0009] Preferably, a chip is arranged on the metal carrier via a die bonding adhesive, and electrodes of the chip are connected to wire bonding pads via bonding wires.

[0010] Preferably, an electrical connection line is provided between the wire bonding pad and the SMT pad.

[0011] Compared with the prior art, the beneficial effects of the utility model are:

[0012] The heat sink is connected to the metal carrier on the front of the substrate through the vias on the BT substrate. These vias are like small "bridges" that connect the heat sink to the metal carrier on the front of the substrate, forming a continuous heat dissipation path. In this way, heat can be transferred from the electronic components to the heat sink more quickly and further dissipated to the external environment through the metal carrier, which not only improves the heat dissipation efficiency but also enhances the stability and reliability of the device. Under high load or long-term operation, an effective heat dissipation system can prevent the device from overheating, thereby protecting the electronic components from damage. At the same time, it also helps to extend the service life of the device and reduce performance degradation or failures caused by overheating. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the overall structure of the utility model;

[0014] Figure 2 This is a schematic diagram of the front structure of the overall unit structure of the utility model;

[0015] Figure 3 This is a schematic diagram of the back structure of the overall unit structure of the utility model;

[0016] Figure 4 This is a schematic diagram of the internal structure of the overall unit structure of the utility model;

[0017] In the figure: 1. BT substrate; 2. Metal carrier; 3. Wire pad; 4. SMT pad; 5. Heat sink; 6. External via; 7. Internal via; 8. Solder resist ink; 9. Direction mark; 10. Chip; 11. Bonding wire; 12. Electrical connection line. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0019] Embodiment 1:

[0020] See also Figure 1-Figure 4 As shown, an integrated circuit structure with high efficiency in heat dissipation comprises:

[0021] A BT substrate 1 is provided with a plurality of units, each of which includes a metal carrier 2, a wire bonding pad 3, an SMT bonding pad 4 and a heat sink 5 provided on the front side of the BT substrate 1, and each of which includes a plurality of external vias 6 and internal vias 7 provided inside the BT substrate 1, wherein the external vias 6 are used to connect the wire bonding pad 3 and the SMT bonding pad 4, and the internal vias 7 are used to connect the heat sink 5 and the metal carrier 2, and a heat dissipation pattern 13 is provided on the heat sink 5.

[0022] In one embodiment of the utility model, solder resist ink 8 is provided on the front and back of the BT substrate 1, and a direction mark 9 is also provided on the back of the BT substrate 1. The non-welding area and the heat sink 5 are covered with solder resist ink 8 to prevent short circuit caused by the flow of solder paste during the SMT process.

[0023] In one embodiment of the present invention, a chip 10 is disposed on the metal carrier 2 by means of a die bonding adhesive, and electrodes of the chip 10 are connected to the wire bonding pads 3 by means of bonding wires 11 .

[0024] In one embodiment of the present invention, an electrical connection line 12 is provided between the wire bonding pad 3 and the SMT pad 4 , and the number of the SMT pads is one of 3, 5, 6, 7, 8, 14, 16, 20, and 24.

[0025] The preparation method comprises the following steps:

[0026] S1. Thinning: Grind the back of the wafer to thin it to the required thickness;

[0027] S2, Slicing: Use cutting equipment to accurately slice the thinned wafer according to the preset cutting lines;

[0028] S3, chip placement: placing the single chip unit obtained after dicing on the BT substrate 1, and fixing the chip 10 on the BT substrate 1 using a die bonding adhesive;

[0029] S4, pressure welding: connecting the chip 10 to the wire bonding pad 3 by pressure welding technology;

[0030] S5, plastic encapsulation: encapsulate the front structure of the BT substrate 1, and cure the plastic encapsulation material at high temperature. The length and width of the package are exactly the same as the existing package dimensions. The product thickness can be packaged according to the requirements, making the packaging more flexible.

[0031] S6. Cutting: Cut the cured plastic package body to separate it into individual integrated circuit packaging units.

[0032] In one embodiment of the utility model, the front side of the BT substrate 1 is processed by a special process, and the surface is rougher, thereby strengthening the bonding force between the plastic packaging material and the BT substrate 1, making the product reliability better. The thickness of the BT substrate 1 can be one of 0.12mm, 0.16mm, 0.18mm, 0.28mm, and 0.48mm. The thickness can be selected according to demand, and the packaging specifications are diversified to meet more markets, making the application process more convenient and quick.

[0033] As can be seen from the above, the traditional pure metal frame is replaced by the BT substrate structure. The front functional area of ​​the BT substrate is provided with a metal carrier and a wire bonding pad. The wire bonding pad is connected to the SMT pad on the back of the substrate through a via hole to achieve electrical interconnection between the front and back of the substrate. The remaining non-functional areas are covered with solder mask ink, which reduces the use of precious metals: Au and Ag, and reduces costs.

[0034] The integrated circuit packaging process is simplified. The original integrated circuit packaging process is: thinning-slicing-core mounting-pressing welding-plastic sealing-electroplating-rib cutting and forming separation. The packaging process of the new integrated circuit packaging structure is changed to: thinning-slicing-core mounting-pressing welding-plastic sealing-cutting;

[0035] In the traditional integrated circuit plastic encapsulation process, the front and back sides of the frame need to be completely encapsulated. However, in the plastic encapsulation process of this packaging structure, only the chip and the bonding wire need to be encapsulated, which reduces the use of encapsulation materials and reduces costs.

[0036] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An integrated circuit structure with high heat dissipation efficiency, characterized in that: include: A BT substrate (1), wherein a plurality of units are arranged on the BT substrate (1), each unit comprising a metal carrier (2) arranged on the front side of the BT substrate (1), a wire bonding pad (3), an SMT bonding pad (4) arranged on the back side of the BT substrate (1), and a heat sink (5), each unit further comprising a plurality of external vias (6) and internal vias (7) arranged inside the BT substrate (1), the external vias (6) being used to achieve connectivity between the wire bonding pad (3) and the SMT bonding pad (4), the internal vias (7) being used to achieve connectivity between the heat sink (5) and the metal carrier (2), and the heat sink (5) being provided with heat dissipation patterns (13).

2. The integrated circuit structure with high heat dissipation efficiency according to claim 1, characterized in that: The front and back of the BT substrate (1) are both provided with solder resist ink (8), and the back of the BT substrate (1) is also provided with a direction mark (9).

3. The integrated circuit structure with high heat dissipation efficiency according to claim 1, characterized in that: A chip (10) is arranged on the metal carrier (2) via a chip adhesive, and an electrode of the chip (10) is electrically connected to a wire bonding pad (3) via a bonding wire (11).

4. The integrated circuit structure with high heat dissipation efficiency according to claim 1, characterized in that: An electrical connection line (12) is provided between the wire bonding pad (3) and the SMT bonding pad (4).

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