Anti-integral saturation PID (Proportion Integration Differentiation) digital circuit

Abstract

The utility model discloses an anti-integral saturation PID (proportion integration differentiation) digital circuit, which particularly relates to the technical field of PID circuits, and is technically characterized in that an integral loop unit comprises a first integral loop unit, a second integral loop unit, a multiplexer, a shifter, a first logic unit and a data selector, the first output end of the demultiplexer is connected with the first integral loop unit, and the second output end of the demultiplexer is connected with the second integral loop unit; the first output end of the first integral loop unit is connected with the first summator, and the second output end of the first integral loop unit is connected with the integral saturation resisting unit; the first output end of the second integral loop unit is connected with the shifter, and the output end of the shifter is connected with the first input end of the data selector; the first output end of the data selector is connected with the first integral loop unit, the second output end of the data selector is connected with the first logic unit, and the first logic unit is connected with the second integral loop unit.

Description

Technical Field

[0001] The utility model relates to the technical field of PID circuits, in particular to an anti-integral saturation PID digital circuit. Background Art

[0002] PID circuit algorithm (Proportion, Integration, Differentiation algorithm) is a classic control algorithm widely used in the field of closed-loop control. It is mainly used to adjust and control physical quantities in real time in continuous control systems to ensure that the output of the controlled system can track the expected set value as quickly and accurately as possible. The core functions of the PID algorithm are reflected in the following aspects:

[0003] 1. Proportional (P) control: The proportional link generates a control signal in proportion to the current error (i.e. the difference between the set value and the actual measured value). The larger the error, the stronger the control effect, thereby quickly responding to system changes and reducing steady-state errors.

[0004] 2. Integral (I) control: The integral link integrates the accumulated error over time. When there is a persistent error, the integral term will gradually increase until the error is eliminated. This helps to eliminate steady-state errors and ensure that the system can stabilize at the set value after long-term operation without generating static deviations.

[0005] 3. Differential (D) control: The differential link produces a control effect based on the rate of change of the error (i.e., the derivative of the error). It can foresee future error trends and respond in advance to reduce the overshoot and oscillation of the system and improve the dynamic performance and stability of the system.

[0006] Through the coordinated work of these three basic components, the PID algorithm can effectively take into account the system's rapid response, zero static error and stability requirements, making it play an important role in many industrial process control, robot motion control, temperature control, liquid level control and other scenarios. With the development of computer technology, digital PID controllers are widely used due to their flexibility and easy implementation. They can dynamically adjust PID parameters according to different system characteristics to achieve better control effects.

[0007] Integral saturation is a phenomenon that a PID controller may encounter when implementing integral control, especially when there is a large deviation for a long time or the integral gain of the controller is set too large. Integral saturation can cause several problems: 1. Decreased stability: As the integral effect weakens or disappears, the system may not be able to eliminate steady-state errors. 2. Deterioration of control quality: The system may have large overshoot or oscillation, affecting control accuracy and response speed.

[0008] In the prior art, in order to deal with the problem of integral saturation, the methods generally adopted are integral limiting and integral separation. Integral limiting directly limits the output of the integrator. When the integrator output reaches the upper or lower limit, integration is stopped to prevent the output from exceeding the range. However, this method may result in errors that cannot be completely eliminated. Integral separation temporarily freezes the operation of the integrator when output saturation is detected, and only allows the proportional and differential parts to work until the saturation state is released and then the integral action is restored. This can avoid subsequent instability caused by excessive integral accumulation. However, these two schemes will actually lose the integral information exceeding the saturated part during the integration process of the integral branch, and may weaken the effect of the integral branch.

[0009] Therefore, the utility model aims to provide an anti-integral saturation PID digital circuit to solve the above-mentioned related problems. Utility Model Content

[0010] The technical problem to be solved by the utility model is that the existing technical solution will lose the integral information exceeding the saturation part during the integration process of the integral branch, and will weaken the function of the integral branch. The purpose is to provide an anti-integral saturation PID digital circuit, by setting two integral loop units on the integral control branch, and using a multiplexer to select and control the inputs of the two integral loop units, and at the same time using the integral accumulated value output by one of the integral loop units to compare with the anti-integral saturation unit, and output a selection signal to control the selection of the multiplexer, so as to achieve the purpose of dynamic feedback control of the entire integral loop unit, prevent a single integral loop unit from losing the integral information exceeding the saturation part after saturation, and solve the problem that the existing technical solution will lose the integral information exceeding the saturation part during the integration process of the integral branch, and will weaken the function of the integral branch.

[0011] The utility model is realized by the following technical solutions:

[0012] An anti-integral saturation PID digital circuit, the circuit includes a proportional adjustment unit, an integral adjustment unit, a first adder and a differential adjustment unit, the integral adjustment unit includes a first multiplier, an integral loop unit and an anti-integral saturation unit;

[0013] The integrating loop unit comprises a first integrating loop unit, a second integrating loop unit, a multiplexer, a shifter, a first logic unit and a data selector, wherein the first output end of the multiplexer is connected to the first integrating loop unit, and the second output end of the multiplexer is connected to the second integrating loop unit; the first output end of the first integrating loop unit is connected to the first adder, and the second output end of the first integrating loop unit is connected to the anti-integration saturation unit; the first output end of the second integrating loop unit is connected to the shifter, and the output end of the shifter is connected to the first input end of the data selector; the first output end of the data selector is connected to the first integrating loop unit, the second output end of the data selector is connected to the first logic unit, and the first logic unit is connected to the second integrating loop unit;

[0014] The input end of the first multiplier is connected to the circuit input end, the first output end of the first multiplier is connected to the demultiplexer, and the second output end of the first multiplier is connected to the anti-integration saturation unit;

[0015] The first output end of the anti-integration saturation unit is connected to the multiplexer, and the second output end of the anti-integration saturation unit is connected to the data selector.

[0016] Further, the anti-integration saturation unit includes a second logic unit, a first comparator and a sign bit comparison unit;

[0017] The second output end of the first multiplier is connected to the first input end of the sign bit comparison unit, the second output end of the first integrating loop unit is connected to the first input end of the first comparator and the second input end of the sign bit comparison unit, the output end of the first comparator is connected to the first input end of the second logic unit and the data selector, the output end of the sign bit comparison unit is connected to the second input end of the second logic unit, and the output end of the second logic unit is connected to the multiplexer.

[0018] Furthermore, a preset first threshold value is input to the second input terminal of the first comparator.

[0019] Furthermore, the first integrating loop unit includes a second adder and a first register, the first output end of the multiplexer and the first output end of the data selector are both connected to the second adder, the output end of the second adder is connected to the first register, the first output end of the first register is connected to the second adder, the second output end of the first register is connected to the first input end of the first comparator, and the third output end of the first register is connected to the first adder.

[0020] Furthermore, the second integrating loop unit includes a third adder and a second register, the second output end of the multiplexer and the output end of the first logic unit are both connected to the third adder, the output end of the third adder is connected to the second register, the first output end of the second register is connected to the shifter, and the second output end of the second register is connected to the third adder.

[0021] Furthermore, the second integrating loop unit is also connected to a second comparator, a first input terminal of the second comparator is connected to a second output terminal of the register, and an output terminal of the second comparator is connected to a host computer.

[0022] Furthermore, a preset second threshold value is input to the second input terminal of the second comparator.

[0023] Furthermore, the input ends of the proportional adjustment unit, the integral adjustment unit and the differential adjustment unit are all connected to the circuit input end, the output ends of the proportional adjustment unit, the integral adjustment unit and the differential adjustment unit are all connected to the first adder, and the output end of the first adder is connected to the circuit output end.

[0024] Furthermore, the ratio adjustment unit includes a second multiplier, an input end of the second multiplier is connected to the circuit input end, and an output end of the second multiplier is connected to the first adder.

[0025] Furthermore, the differential adjustment unit includes a first subtractor, a third multiplier and a third register, the input end of the first subtractor is connected to the circuit input end, the output end of the first subtractor is connected to the third multiplier, the output end of the third multiplier is connected to the first adder, the input end of the third register is connected to the circuit input end, and the output end of the third register is connected to the first subtractor.

[0026] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0027] In the utility model, two integral loop units are arranged on the integral control branch, and a multiplexer is used to select and control the inputs of the two integral loop units. At the same time, the integral accumulated value output by one of the integral loop units is compared with the anti-integral saturation unit, and a selection signal for controlling the selection of the multiplexer is output, thereby achieving the purpose of dynamic feedback control of the entire integral loop unit, preventing the loss of integral information exceeding the saturation part after a single integral loop unit is saturated, and solving the related problems of the prior art solution that the integral information exceeding the saturation part is lost during the integration process of the integral branch and the effect of the integral branch is weakened. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present utility model, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0029] Figure 1 Schematic diagram of the structure of an anti-integral saturation PID digital circuit in this embodiment;

[0030] Figure 2 Schematic diagram of the structure of an integral adjustment unit in an anti-integral saturation PID digital circuit in this embodiment;

[0031] Figure 3 The figure is a detailed structural diagram of each unit in an anti-integral windup PID digital circuit in this embodiment.

[0032] Marks and corresponding parts names in the attached drawings:

[0033] 1. Proportional adjustment unit; 101. Second multiplier;

[0034] 2. Integral adjustment unit;

[0035] 3. The first adder;

[0036] 4. Differential adjustment unit; 401. First subtractor; 402. Third multiplier; 403. Third register;

[0037] 5. The first multiplier;

[0038] 6. Integrating loop unit; 601. First integrating loop unit; 6011. Second adder; 6012. First register; 602. Second integrating loop unit; 6021. Third adder; 6022. Second register; 603. Demultiplexer; 604. Shifter; 605. First logic unit; 606. Data selector;

[0039] 7. Anti-integration saturation unit; 701. Second logic unit; 702. First comparator; 703. Sign bit comparison unit;

[0040] 8. A second comparator;

[0041] 9. Host computer. DETAILED DESCRIPTION

[0042] In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent to those skilled in the art that these specific details are not necessary to implement the present invention. In other embodiments, in order to avoid confusing the present invention, well-known structures, circuits, materials or methods are not specifically described.

[0043] Throughout the specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "one embodiment," "an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily all refer to the same embodiment or example. In addition, particular features, structures, or characteristics may be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. In addition, it will be appreciated by those of ordinary skill in the art that the figures provided herein are for illustrative purposes and that the figures are not necessarily drawn to scale. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] In the description of the present invention, the terms "front", "rear", "left", "right", "up", "down", "vertical", "horizontal", "high", "low", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the scope of protection of the present invention.

[0045] It should be explained that the PID digital circuit includes a proportional control branch, an integral control branch and a differential control branch. The proportional (P) control branch generates a control signal in proportion to the current error (i.e., the difference between the set value and the actual measured value). The larger the error, the stronger the control effect, which can quickly respond to system changes and reduce steady-state errors. The integral (I) control branch integrates the accumulated error over time. When there is a persistent error, the integral term will gradually increase until the error is eliminated, which helps to eliminate steady-state errors and ensure that the system can stabilize at the set value after long-term operation without generating static deviations. The differential (D) control branch generates a control effect based on the rate of change of the error (i.e., the derivative of the error). It can foresee future error trends and respond in advance to reduce the overshoot and oscillation of the system and improve the dynamic performance and stability of the system.

[0046] The innovation of the utility model is that two integral loop units are set on the integral control branch, and a multiplexer is used to select and control the inputs of the two integral loop units. At the same time, the integral accumulated value output by one of the integral loop units is compared with the anti-integral saturation unit, and a selection signal for controlling the selection of the multiplexer is output, so as to achieve the purpose of dynamic feedback control of the entire integral loop unit, prevent the loss of integral information exceeding the saturation part after a single integral loop unit is saturated, and solve the related problems that the existing technical solution will lose the integral information exceeding the saturation part during the integration process of the integral branch, and at the same time will weaken the function of the integral branch. For specific and detailed technical content, please refer to the following embodiments.

[0047] Example

[0048] See also Figure 1-3 As shown, an anti-integral saturation PID digital circuit includes a proportional adjustment unit 1, an integral adjustment unit 2, a first adder 3 and a differential adjustment unit 4, and the integral adjustment unit 2 includes a first multiplier 5, an integral loop unit 6 and an anti-integral saturation unit 7;

[0049] The integration loop unit 6 includes a first integration loop unit 6016, a second integration loop unit 6026, a multiplexer 603, a shifter 604, a first logic unit 605 and a data selector 606. The first output end of the multiplexer 603 is connected to the first integration loop unit 6016, and the second output end of the multiplexer 603 is connected to the second integration loop unit 6026; the first output end of the first integration loop unit 6016 is connected to the first adder 3, and the second output end of the first integration loop unit 6016 is connected to the anti-integration saturation unit 7; the first output end of the second integration loop unit 6026 is connected to the shifter 604, and the shifter 604 is connected to the first logic unit 605. The output end of the selector 604 is connected to the first input end of the data selector 606; the first output end of the data selector 606 is connected to the first integral loop unit 6016, the second output end of the data selector 606 is connected to the first logic unit 605, the second input end of the data selector 606 is also input with a value of 0, and the first logic unit 605 is connected to the second integral loop unit 6026. It should be noted that, in this embodiment, the first logic unit 605 is a logic NOT gate circuit for logic NOT gate operation, the logic NOT gate circuit is a prior art, and can be a CMOS gate circuit. The technical solution is a conventional technical means in the art and will not be described in detail here.

[0050] The input end of the first multiplier 5 is connected to the circuit input end, the first output end of the first multiplier 5 is connected to the demultiplexer 603, the second output end of the first multiplier 5 is connected to the anti-integral saturation unit 7, and the input end of the first multiplier 5 is also input with a preset integral branch coefficient. Specifically, in this embodiment, the integral saturation rate of the PID circuit is controlled by multiplying the integral branch coefficient by the first multiplier 5. The value of the integral branch coefficient can be 0.2, 0.25, 0.5, or other reasonable values, and the specific value depends on the actual situation;

[0051] Specifically, in the present embodiment, the output of the first integral loop unit 6016 is used for the output of the integral control branch; the second integral loop unit 6026 is used as a reserve unit of the first integral loop unit 6016, and will temporarily store the integral accumulated value when the first integral loop unit 6016 is saturated; the multiplexer 603 is used to select the output to the first integral loop unit 6016 or the second integral loop unit 6026 based on the selection signal; the shifter 604 is used to reduce the integral accumulated value of the second integral loop unit 6026; a logical negation operation is performed through the first logic unit 605; and the integral accumulated value of the second integral loop unit 6026 reduced by the shifter 604 is selected to be output through the data selector 606, or the input value 0 of the data selector 606 is selected to be output.

[0052] The first output end of the anti-integral saturation unit 7 is connected to the multiplexer 603, and the second output end of the anti-integral saturation unit 7 is connected to the data selector 606; the anti-integral saturation unit 7 includes a second logic unit 701, a first comparator 702 and a sign bit comparison unit 703; the second output end of the first multiplier 5 is connected to the first input end of the sign bit comparison unit 703, the second output end of the first integral loop unit 6016 is connected to the first input end of the first comparator 702 and the second input end of the sign bit comparison unit 703, the output end of the first comparator 702 is connected to the first input end of the second logic unit 701 and the data selector 606, the second input end of the first comparator 702 is input with a preset first threshold value, the output end of the sign bit comparison unit is connected to the second input end of the second logic unit 701, and the output end of the second logic unit 701 is connected to the multiplexer 603.

[0053] It should be noted that, in the present embodiment, the second logic unit 701 is a logic AND gate circuit, which is used for logic AND gate operation. The logic AND gate circuit is a prior art and can be a CMOS gate circuit. This technical solution is a conventional technical means in this field and will not be described in detail here. The sign bit comparison unit 703 is used to determine whether the integral accumulation value output by the first integral loop unit 6016 and the product result output by the first multiplier 5 are both positive or negative. If they are both positive or negative, the two values ​​are in the same direction. If one is positive and the other is negative, the two values ​​are in opposite directions. Note: 1. The highest bit of a binary signed number is the sign bit, 1 represents a negative number, and 0 represents a positive number. The entire circuit should use signed number operations; 2. The sign bit comparison unit 703 only determines whether they are equal through the "==" sign, and outputs 1 if they are equal, otherwise 0. This technical content is a conventional technical means in this field and will not be described in detail here.

[0054] At the same time, in this embodiment, since the integral accumulation value output by the first integral loop unit 6016 and the product result output by the first multiplier 5 are both positive and negative, the preset first threshold value includes a first lower threshold and a first upper threshold. The first lower threshold refers to the minimum limit value that the first integral loop unit 6016 can accumulate, and the first upper threshold refers to the maximum limit value that the first integral loop unit 6016 can accumulate. The value of the first lower threshold can be -80%, -90%, or -95%, and the value of the first upper threshold can be 80%, 90%, or 95%. The specific values ​​of the two depend on the actual situation. The first comparator 702 is used to detect whether the integral accumulation of the first integral loop unit 6016 will produce saturation.

[0055] Specifically, in this embodiment, the first integral loop unit 6016 outputs the integral accumulated value of the first integral loop unit 6016 to the first comparator 702, and the first comparator 702 compares the integral accumulated value with the preset first threshold value, and outputs the saturation judgment result to the second logic unit 701 and the data selector 606, wherein the saturation judgment result includes: 1. If the integral accumulated value does not exceed the first threshold value, the first integral loop unit 6016 does not reach the saturation state, and the saturation judgment result is 0; 2. If the integral accumulated value exceeds the first threshold value, the first integral loop unit 6016 reaches the saturation state, and the saturation judgment result is 1;

[0056] The integral accumulated value output by the first integral loop unit 6016 is simultaneously input into the sign bit comparison unit 703, and the first multiplier 5 inputs the product result into the sign bit comparison unit 703, the sign bit comparison unit 703 compares and determines whether the directions of the integral accumulated value and the product result are reversed, obtains the direction determination result and inputs it into the second logic unit 701, wherein the direction determination result includes: 1. If the direction of the integral accumulated value is reversed to the direction of the product result, the direction determination result is 0; 2. If the direction of the integral accumulated value is the same as the direction of the product result, the direction determination result is 1;

[0057] The second logic unit 701 performs logic AND gate processing based on the direction judgment result and the saturation judgment result, as follows: 1. If the saturation judgment result is 0 and the direction judgment result is 0, the obtained logic result is 0, indicating that the first integral loop unit 6016 has not reached the saturation state at this time, and the product result is reducing the integral cumulative value; 2. If the saturation judgment result is 1 and the direction judgment result is 0, the obtained logic result is 0, indicating that the first integral loop unit 6016 has reached the saturation state at this time, but the product result is reducing the integral cumulative value; 3. If the saturation judgment result is 0 and the direction judgment result is 1, the obtained logic result is 0, indicating that the first integral loop unit 6016 has not reached the saturation state at this time, but the product result is increasing the integral cumulative value; 4. If the saturation judgment result is 1 and the direction judgment result is 1, the obtained logic result is 1, indicating that the first integral loop unit 6016 has reached the saturation state at this time, and the product result is continuing to increase the integral cumulative value;

[0058] The processed logic result is sent to the demultiplexer 603 as a selection signal of the demultiplexer 603 to select the product result to be input to one of the two integration loop units 6. If the selection signal sent by the second logic unit 701 is 0, the product result is input to the first integration loop unit 6016 for accumulation; if the selection signal sent by the second logic unit 701 is 1, the product result is input to the second integration loop unit 6026 for accumulation;

[0059] At the same time, the data selector 606 receives the saturation judgment result output by the first comparator 702 as the selection signal of the data selector 606. If the saturation judgment result is 1, the data selector 606 selects to output the integrated accumulated value after being reduced by the shifter 604 to the first integrated loop unit 6016 from the second integral loop unit 6026. If the comparison result is 0, the data selector 606 selects to output 0.

[0060] Furthermore, the first integrating loop unit 6016 includes a second adder 6011 and a first register 6012, the first output end of the multiplexer 603 and the first output end of the data selector 606 are both connected to the second adder 6011, the output end of the second adder 6011 is connected to the first register 6012, the first output end of the first register 6012 is connected to the second adder 6011, the second output end of the first register 6012 is connected to the first input end of the first comparator 702, and the third output end of the first register 6012 is connected to the first adder 3.

[0061] Specifically, in this embodiment, the second adder 6011 is used to accumulate the product results input to the first integration loop unit 6016; the first register 6012 is used to store the product results accumulated by the second adder 6011 and output an integral accumulation value.

[0062] Furthermore, the second integrating loop unit 6026 includes a third adder 6021 and a second register 6022, the second output end of the multiplexer 603 and the output end of the first logic unit 605 are both connected to the third adder 6021, the output end of the third adder 6021 is connected to the second register 6022, the first output end of the second register 6022 is connected to the shifter 604, and the second output end of the second register 6022 is connected to the third adder 6021.

[0063] Specifically, in this embodiment, the third adder 6021 is used to accumulate the product results input to the second integration loop unit 6026; the second register 6022 is used to store the product results accumulated by the third adder 6021 and output an integral accumulation value.

[0064] Furthermore, the second integrating loop unit 6026 is also connected to a second comparator 8, a first input terminal of the second comparator 8 is connected to the second output terminal of the register, a second input terminal of the second comparator 8 inputs a preset second threshold value, and an output terminal of the second comparator 8 is connected to the host computer.

[0065] It should be noted that, in the present embodiment, the preset second threshold value includes a second lower threshold and a second upper threshold. The second lower threshold refers to the minimum limit value that the second integral loop unit 6026 can accumulate, and the second upper threshold refers to the maximum limit value that the second integral loop unit 6026 can accumulate. The value of the second lower threshold can be -85%, -90%, or -95%, and the value of the second upper threshold can be 85%, 90%, or 95%. The specific values ​​of the two depend on the actual situation. The second comparator 8 is used to detect whether the integral accumulation of the second integral loop unit 6026 will produce saturation.

[0066] Specifically, in the present embodiment, the second comparator 8 is used to detect whether the integral accumulation of the second integral loop unit 6026 will produce saturation. When the second comparator 8 detects that the integral accumulation value output by the second integral loop unit 6026 exceeds the second threshold value, indicating that the first integral loop unit 6016 and the second integral loop unit 6026 have both reached saturation, the second comparator 8 will output an "error" signal to the host computer, which may be a control terminal such as a CPU.

[0067] Furthermore, the input ends of the proportional adjustment unit 1, the integral adjustment unit 2 and the differential adjustment unit 4 are all connected to the circuit input end, the output ends of the proportional adjustment unit 1, the integral adjustment unit 2 and the differential adjustment unit 4 are all connected to the first adder 3, and the output end of the first adder 3 is connected to the circuit output end.

[0068] Furthermore, the ratio adjustment unit 1 comprises a second multiplier 101 , an input end of the second multiplier 101 is connected to the circuit input end, and an output end of the second multiplier 101 is connected to the first adder 3 .

[0069] Specifically, in this embodiment, the input end of the second multiplier 101 also inputs a proportional branch coefficient. After the input and the proportional recognition coefficient are multiplied by the second multiplier 101, a proportional branch output is obtained, which is output to the first adder 3. This technical means is a prior art and will not be elaborated here.

[0070] Furthermore, the differential adjustment unit 4 includes a first subtractor 401, a third multiplier 402 and a third register 403, the input end of the first subtractor 401 is connected to the circuit input end, the output end of the first subtractor 401 is connected to the third multiplier 402, the output end of the third multiplier 402 is connected to the first adder 3, the input end of the third register 403 is connected to the circuit input end, and the output end of the third register 403 is connected to the first subtractor 401.

[0071] Specifically, in this embodiment, the third multiplier 402 also inputs a differential branch coefficient. The input is first subtracted from the output of the first subtractor 401 and the third register 403 (the output value is the temporarily stored input of the previous PID). The result of the subtraction is the difference between the current input and the previous input. The difference is then multiplied by the differential branch coefficient to obtain the differential branch output, which is output to the first adder 3. This technical means is a prior art and will not be elaborated on here.

[0072] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only the specific implementation method of the utility model and is not used to limit the protection scope of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. An anti-integral saturation PID digital circuit, characterized in that: The circuit includes a proportional adjustment unit, an integral adjustment unit, a first adder and a differential adjustment unit, and the integral adjustment unit includes a first multiplier, an integral loop unit and an anti-integral saturation unit; The integrating loop unit comprises a first integrating loop unit, a second integrating loop unit, a multiplexer, a shifter, a first logic unit and a data selector, wherein the first output end of the multiplexer is connected to the first integrating loop unit, and the second output end of the multiplexer is connected to the second integrating loop unit; the first output end of the first integrating loop unit is connected to the first adder, and the second output end of the first integrating loop unit is connected to the anti-integration saturation unit; the first output end of the second integrating loop unit is connected to the shifter, and the output end of the shifter is connected to the first input end of the data selector; the first output end of the data selector is connected to the first integrating loop unit, the second output end of the data selector is connected to the first logic unit, and the first logic unit is connected to the second integrating loop unit; The input end of the first multiplier is connected to the circuit input end, the first output end of the first multiplier is connected to the demultiplexer, and the second output end of the first multiplier is connected to the anti-integration saturation unit; The first output end of the anti-integration saturation unit is connected to the multiplexer, and the second output end of the anti-integration saturation unit is connected to the data selector.

2. The anti-integral windup PID digital circuit according to claim 1, characterized in that: The anti-integration saturation unit includes a second logic unit, a first comparator and a sign bit comparison unit; The second output end of the first multiplier is connected to the first input end of the sign bit comparison unit, the second output end of the first integrating loop unit is connected to the first input end of the first comparator and the second input end of the sign bit comparison unit, the output end of the first comparator is connected to the first input end of the second logic unit and the data selector, the output end of the sign bit comparison unit is connected to the second input end of the second logic unit, and the output end of the second logic unit is connected to the multiplexer.

3. The anti-integral windup PID digital circuit according to claim 2, characterized in that: A preset first threshold value is inputted into the second input terminal of the first comparator.

4. The anti-integral windup PID digital circuit according to claim 3 is characterized in that: The first integrating loop unit includes a second adder and a first register, the first output end of the multiplexer and the first output end of the data selector are both connected to the second adder, the output end of the second adder is connected to the first register, the first output end of the first register is connected to the second adder, the second output end of the first register is connected to the first input end of the first comparator, and the third output end of the first register is connected to the first adder.

5. The anti-integral windup PID digital circuit according to claim 3 is characterized in that: The second integrating loop unit includes a third adder and a second register, the second output end of the multiplexer and the output end of the first logic unit are both connected to the third adder, the output end of the third adder is connected to the second register, the first output end of the second register is connected to the shifter, and the second output end of the second register is connected to the third adder.

6. The anti-integral windup PID digital circuit according to claim 5, characterized in that: The second integral loop unit is also connected to a second comparator, a first input end of the second comparator is connected to a second output end of the register, and an output end of the second comparator is connected to a host computer.

7. The anti-integral windup PID digital circuit according to claim 6, characterized in that: A preset second threshold value is inputted into the second input terminal of the second comparator.

8. The anti-integral windup PID digital circuit according to claim 1, characterized in that: The input ends of the proportional adjustment unit, the integral adjustment unit and the differential adjustment unit are all connected to the circuit input end, the output ends of the proportional adjustment unit, the integral adjustment unit and the differential adjustment unit are all connected to the first adder, and the output end of the first adder is connected to the circuit output end.

9. The anti-integral windup PID digital circuit according to claim 8, characterized in that: The ratio adjustment unit comprises a second multiplier, an input end of the second multiplier is connected to the circuit input end, and an output end of the second multiplier is connected to the first adder.

10. The anti-integral windup PID digital circuit according to claim 8, characterized in that: The differential adjustment unit includes a first subtractor, a third multiplier and a third register, the input end of the first subtractor is connected to the circuit input end, the output end of the first subtractor is connected to the third multiplier, the output end of the third multiplier is connected to the first adder, the input end of the third register is connected to the circuit input end, and the output end of the third register is connected to the first subtractor.

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