Wafer protection structure in wafer bump manufacturing process for manufacturing silicon photonic wafer

Abstract

A wafer protection structure in a wafer bump manufacturing process for manufacturing a silicon photonic wafer comprises a first protection layer which covers a first surface of a silicon photonic wafer substrate, and the silicon photonic wafer substrate comprises a light leading-in groove and an aluminum pad which are distributed on the first surface, the first protection layer exposes the light leading-in groove and a part of the surface of the aluminum pad; the under-ball metal layer is arranged on the first protection layer, the light leading-in groove and the aluminum pad; the second protection structure is arranged on the light leading-in groove and is in contact with a part of the under-ball metal layer; and a patterned first photoresist layer disposed on the first surface, the patterned first photoresist layer covering the second protection structure and exposing a portion of the under-ball metal layer on the aluminum pad.

Description

Technical Field

[0001] The present utility model relates to the field of silicon photonics wafer packaging, and particularly to a wafer protection structure in the process of fabricating wafer bumps on a side-light input silicon photonics wafer. Background Art

[0002] Silicon photonics utilizes CMOS process technology to support the semiconductor industry, integrating components such as optical receivers, optical modulators, optical waveguides, and electronic circuits on a silicon substrate. The hybrid of optical transceivers responsible for converting optical signals and electrical signals with integrated circuit chips has gradually evolved into Near-package Optics (NPO) and Co-package Optics (CPO). Therefore, optoelectronic integration based on silicon photonics will be a key technology for future computing systems and information networks.

[0003] To achieve high-density optical input / output, an efficient fiber coupling structure must be adopted. The coupling structure is divided into two types: grating couplers and edge couplers. Grating couplers usually use a relatively simple etching process to achieve vertical optical coupling, while edge couplers require undercut and deep etching technologies during the manufacturing process, and these technologies affect the stability and reliability of the components. In most current CPO solutions, edge couplers are mostly used in the paths of optical input and output. A carefully designed edge coupler can simultaneously meet the requirements of high alignment tolerance and low insertion loss. When fabricating a passive alignment V-groove structure for side-light input on the side of a silicon photonics wafer, the typical fiber-to-chip loss can be controlled at -1.5 dB. With the development of the trend towards high integration, standard silicon photonics manufacturing technology must adapt to the development of packaging. To meet the requirements of CPO, it is urgent to develop advanced silicon photonics manufacturing technology and component structures. Summary of the Utility Model

[0004] The present utility model provides a wafer protection structure in the process of fabricating wafer bumps on a silicon photonics wafer. By forming a protection structure and covering the optical input groove of the side-light input silicon photonics wafer, the optical input groove is protected from damage during the formation of wafer bumps, and the silicon photonics wafer is protected by patterning a photoresist layer during the formation of wafer bumps.

[0005] According to the above, the present utility model provides a wafer protection structure in a wafer bumping process for fabricating a silicon photonics wafer, comprising: a first protective layer covering a first surface of a silicon photonics wafer substrate, wherein the silicon photonics wafer substrate includes an optical waveguide trench and aluminum pads distributed on the first surface, and the first protective layer exposes partial surfaces of the optical waveguide trench and the aluminum pads; a under-bump metal layer disposed on the first protective layer, the optical waveguide trench, and the aluminum pads; a second protection structure disposed on the optical waveguide trench and contacting a part of the under-bump metal layer; and a patterned first photoresist layer disposed on the first surface, the patterned first photoresist layer covering the second protection structure and exposing a part of the under-bump metal layer on the aluminum pads.

[0006] Preferably, the first protective layer includes a silicon nitride or a silicon dioxide layer, and the second protection structure is formed by a dry film.

[0007] Preferably, the under-bump metal layer includes a titanium / copper alloy with a thickness in the range of 600 to 1300 nanometers.

[0008] Preferably, the second protection structure includes a dry film with a thickness of 40 micrometers.

[0009] Preferably, the second protection structure is located directly above the optical waveguide trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0011] Figure 2 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0012] Figure 3 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0013] Figure 4 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0014] Figure 5 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0015] Figure 6 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0016] Figure 7 It is a schematic cross-sectional view of the structure for fabricating a silicon photonics wafer with metal bumps according to the present utility model.

[0017] Figure 8 It is a flowchart schematic diagram of a method for forming wafer bumps of a silicon photonics wafer of the present utility model.

[0018] List of reference numerals

[0019] 10 Substrate

[0020] 11 First surface

[0021] 12 Aluminum pad

[0022] 13 Directly above position

[0023] 14 Optical waveguide trench

[0024] 16 First protective layer

[0025] 22 Under-bump metal layer

[0026] 24 Second protection structure

[0027] 26 Patterning first photoresist layer

[0028] 32 Bump

[0029] 34 Bump metal layer

[0030] Steps 41, 43, 45, 46, 47, 49. Detailed implementation manners

[0031] Taking the following embodiments as examples, although one, a single or some embodiments are involved in the following description, it does not mean that every such reference is the same (identical) embodiment, nor does it mean that such features are only applicable to a single embodiment. The single features of different embodiments can be combined to provide other embodiments. In the following, the features of the present utility model will be described by simple examples of various implementation device architectures that can implement the present utility model, and only the relevant components of the examples will be described in detail. However, the structures and processes of silicon photonics wafers that are well known to those skilled in the art may not be specifically described herein.

[0032] In the present utility model, the following-mentioned Under Bump Metallization layer (UBM layer) has functions including signal connection, preventing mutual diffusion and contamination between metal pads and bumps, and serving as a mechanical connection between solder joints and chips. Secondly, generally from the perspective of functions, the Under Bump Metallization layer is composed of three layers of metals, including an Adhesion Layer, a Diffusion Barrier Layer, a Wetting Layer or an Oxidation Resistant Layer. By way of example but not limitation, the materials of the Adhesion Layer include chromium and titanium series metals, the materials of the Diffusion Barrier Layer include metals such as nickel, copper, molybdenum, tungsten, etc., and the Wetting Layer or the Oxidation Resistant Layer includes gold or palladium metals. The forming process can be methods such as electron beam evaporation (E-Beam Evaporator), magnetron sputtering (Sputter), or electroless plating (Electroless plating).

[0033] Figures 1 to 7 It is a schematic cross-sectional view of the structure for preparing a silicon photonics wafer with metal bumps according to the present utility model. Figure 8 It is a schematic flow chart of the method for forming wafer bumps of the silicon photonics wafer according to the present utility model. Please also refer to Figure 1 and Figure 8 , first, a silicon photonics wafer substrate is provided (step 41). In one embodiment, a silicon photonics wafer has a substrate 10, and one or more aluminum pads 12 and light guiding grooves 14 are distributed on a first surface 11 of the substrate 10. The light guiding grooves 14 can be used for setting optical fibers later, and their shapes can be V-shaped, U-shaped, trapezoidal or other shapes suitable for placing and fixing optical fibers, and the aluminum pads 12 can be used for bonding or / and conduction. Secondly, a first protective layer 16 (passivation layer) covers the first surface 11, and the first protective layer 16 exposes partial surfaces of the light guiding grooves 14 and the aluminum pads 12. By way of example but not limitation, the first protective layer 16 can be one or more layers of silicon nitride (Si3N4) or silicon dioxide (SiO2).

[0034] Next, refer to Figure 2 and Figure 8, a sub - spherical metal layer is conformally formed (step 43). In one embodiment, a sub - spherical metal layer 22 is conformally formed on the first surface 11 in a suitable manner, and the sub - spherical metal layer 22 covers the light - guiding grooves 14 and aluminum pads 12 exposed by the first protective layer 16, wherein the side walls of the light - guiding grooves 14 are covered by the sub - spherical metal layer 22. Secondly, the sub - spherical metal layer 22, by way of example but not limitation, conformally forms one or more metal layers, such as titanium / copper (Ti / Cu), on the substrate 10 by physical vapor deposition (PVD) or sputtering. The thickness of the formed sub - spherical metal layer 22 can be in the range of 600 to 1300 nanometers. For example, in the titanium / copper alloy, titanium is in the range of 100 to 300 nanometers and copper can be in the range of 500 to 800 nanometers.

[0035] Next, referring to Figure 3 and Figure 8 , a second protective structure is formed on the light - guiding grooves of the silicon - photonics wafer substrate (step 45). In one embodiment, a second protective structure 24 is formed above the light - guiding grooves 14 of the substrate 10, and the second protective structure 24 covers the light - guiding grooves 14 to make the light - guiding grooves 14 a closed space. One of the technical features of the present invention is to protect the light - guiding grooves 14 from the influence of subsequent processes by forming the second protective structure 24. Generally, a silicon - photonics wafer has light - guiding grooves. Compared with other structures / constructions of the silicon - photonics wafer, the light - guiding grooves have a larger depth. In subsequent processes, such as lithography etching, there may be problems such as incomplete coating of the photoresist layer or incomplete removal resulting in residues, or the formation of metal side plating. Therefore, the present invention solves the above problems by covering the light - guiding grooves 14 with the second protective structure 24 like a top cover. By way of example but not limitation, a dry film with a thickness of about 40 micrometers (um) is coated on the first surface 11. The dry film contacts the sub - spherical metal layer 22 on the first surface 11, and then the second protective structure 24 is formed by appropriate methods such as lithography, exposure, and etching.

[0036] Next, referring to Figure 4 and Figure 8 , a patterned first photoresist layer is formed on the first surface. The patterned first photoresist layer covers the second protective structure and exposes a part of the sub - spherical metal layer (step 46). In one embodiment, a first photoresist layer is first covered on the first surface 11, wherein the first photoresist layer covers the second protective structure 24 and the sub - spherical metal layer 22. Then, through appropriate methods such as lithography, exposure, and etching, part of the first photoresist layer is removed to expose a part of the sub - spherical metal layer 22. The sub - spherical metal layer 22 exposed by the patterned first photoresist layer 26 is at the position 13 directly above the aluminum pad 12. Therefore, the present invention provides a wafer protection structure in a wafer bump of a silicon - photonics wafer as Figure 4As shown, this wafer protection structure can protect the silicon photon wafer from damage during the formation of wafer bumps, and at the same time avoid the formation of defects that are not easily detected in the optical guiding groove 14.

[0037] Next, referring to Figure 5 and Figure 8 , a bump member layer is sequentially formed on the exposed under-bump metal layer (step 47). In one embodiment, through a method such as plating, a bump 32 and a bump metal layer 34 are sequentially formed on the under-bump metal layer 22 at the position 13 directly above the aluminum pad 12, where the bump 32 can be copper metal, alloy or compound, and the bump metal layer 34 can be nickel / gold, nickel / gold / tin, nickel / tin / silver metal, alloy or compound.

[0038] Next, referring to Figure 6 , Figure 7 and Figure 8 , the patterned first photoresist layer, the second protection structure and the under-bump metal layer are sequentially removed (step 49). In one embodiment, through appropriate methods such as stripping, the patterned first photoresist layer 26 and the second protection structure 24 are sequentially or simultaneously removed, and then the exposed under-bump metal layer 22 is removed through appropriate methods such as metal wet etching. Therefore, after the steps of removing the patterned first photoresist layer, the second protection structure and the under-bump metal layer, only the part of the under-bump metal layer 22 between the aluminum pad 12 and the bump 32 will be retained, forming a silicon photon wafer with metal bumps.

[0039] According to the above, the process for fabricating wafer bumps of a silicon photon wafer includes: providing a silicon photon wafer substrate, the silicon photon wafer substrate including an optical guiding groove and aluminum pads distributed on a first surface, and a first protective layer (passivation layer) covering the first surface and exposing part of the surfaces of the optical guiding groove and the aluminum pads; conformally forming an under-bump metal layer on the first surface, the under-bump metal layer covering the optical guiding groove and the aluminum pads exposed by the first protective layer; forming a second protection structure on the optical guiding groove; forming a patterned first photoresist layer on the first surface, the patterned first photoresist layer covering the second protection structure and exposing part of the under-bump metal layer on the aluminum pad; forming a bump structure layer on the exposed under-bump metal layer; and removing the patterned first photoresist layer, the second protection structure and part of the under-bump metal layer.

[0040] The embodiments described above are only to illustrate the technical idea and characteristics of the present utility model. The purpose is to enable those skilled in the art to understand the content of the present utility model and implement it accordingly. It should not be used to limit the patent scope of the present utility model. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present utility model should still be covered within the patent scope of the present utility model.

Claims

1. A wafer protection structure in a wafer bumping process for fabricating a silicon photonics wafer, characterized in that Including: A first protective layer covers a first surface of a silicon photonics wafer substrate. It is characterized in that the silicon photonics wafer substrate includes an optical guiding groove and an aluminum pad distributed on the first surface, and the first protective layer exposes partial surfaces of the optical guiding groove and the aluminum pad; A under-bump metal layer is disposed on the first protective layer, the optical guiding groove and the aluminum pad; A second protection structure is disposed on the optical guiding groove and contacts a part of the under-bump metal layer; and A patterned first photoresist layer is disposed on the first surface, the patterned first photoresist layer covers the second protection structure and exposes a part of the under-bump metal layer on the aluminum pad.

2. The wafer protection structure in the wafer bump process for fabricating a silicon photonics wafer as claimed in claim 1, wherein The first protective layer includes a silicon nitride or a silicon dioxide layer, and the second protection structure is formed by a dry film.

3. The wafer protection structure in the wafer bumping process for fabricating a silicon photonics wafer as claimed in claim 1 or 2, wherein, The under-bump metal layer includes a titanium / copper alloy with a thickness in the range of 600 to 1300 nanometers.

4. The wafer protection structure in the wafer bump process for fabricating a silicon photonics wafer as claimed in claim 1 or 2 or 3, wherein, The second protection structure includes a dry film with a thickness of 40 micrometers.

5. The wafer protection structure in the wafer bumping process for fabricating a silicon photonics wafer as claimed in claim 1 or 2 or 3, characterized in that, The second protection structure is located at a directly above position of the optical guiding groove.

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