Differential sampling calculation circuit composed of operational amplifiers
By using ordinary high-precision resistors and differential sampling operational amplifiers in the power supply voltage sampling circuit, the circuit vulnerability caused by ultra-high-precision voltage divider resistance is solved, and stable and efficient output voltage sampling and circuit protection are achieved.
Patent Information
- Application Number
- CN202421690385.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-07-17
AI Technical Summary
In existing power supply voltage sampling circuits, the use of ultra-high-precision voltage divider resistors leads to easy damage to the circuit, and the sampling signal error amplifier and other components may be damaged when the output voltage is abnormal.
Ordinary high-precision resistors are used to replace the ultra-high-precision voltage-dividing resistors, and the difference between the differential sampling operational amplifier and the reference voltage is amplified. The output voltage divider is not directly connected to the sampling signal error amplifier, and the pull-up resistor is combined with a pull-up resistor to protect the output end of the sampling signal error amplifier.
It realizes stable and efficient output voltage sampling, protects the sampling signal error amplifier and other circuit components, and avoids circuit damage.
Smart Images
Figure CN223219076U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of differential sampling circuits, in particular to a differential sampling calculation circuit composed of an operational amplifier. Background Art
[0002] Currently, module power supply output voltage sampling uses a voltage divider method. This method, characterized by its simplicity, reliability, and minimal component count, is widely used in various power supply voltage sampling circuits. However, in practical circuits, to ensure that the output voltage is closer to the desired value, the voltage divider resistor must possess extremely high precision and be directly connected to the sampling signal error amplifier. Consequently, in practical applications, if the output voltage becomes abnormally high or the voltage divider resistor shorts, it can damage the sampling signal error amplifier in the circuit and even other components in the power supply, affecting its proper operation. Utility Model Content
[0003] In the existing power supply voltage sampling circuit, the voltage division method is adopted, which not only requires the configuration of ultra-high-precision voltage-dividing resistors, but also when the output voltage of the circuit becomes abnormally high or the voltage-dividing resistor is short-circuited, it will cause damage to the sampling error amplifier in the circuit, or cause damage to other components in the power supply. The utility model provides a differential sampling circuit composed of an operational amplifier, in which the voltage-dividing resistors use ordinary high-precision resistors instead of ultra-high-precision voltage-dividing resistors, and the output voltage division is not directly connected to the sampling signal error amplifier, so that more stable and efficient output voltage sampling can be achieved. At the same time, by using a pull-up resistor at the output end of the differential sampling operational amplifier, the output level of the error operational amplifier can be controlled when the power supply is protected.
[0004] The technical solution is as follows: a differential sampling calculation circuit composed of an operational amplifier, which includes a sampling signal error amplifier IC1, characterized in that: a differential sampling circuit is provided between the sampling signal error amplifier IC1 and the positive terminal VO+ and the negative terminal VO- of the output voltage, the differential sampling circuit includes a differential sampling operational amplifier IC2, the non-inverting input terminal of the differential sampling operational amplifier IC2 is connected to one end of a resistor R10, one end of a resistor R12, one end of a capacitor C8, and one end of a capacitor C4, the other end of the resistor R10 is connected to the positive terminal VO+ of the output voltage in sequence through resistors R9 and R8, the other end of the resistor R12 is connected to the other end of the capacitor C8 and then grounded, the inverting input terminal of the sampling signal error amplifier IC1 is connected to one end of a resistor R2, one end of a capacitor C2, one end of a resistor R6, and the other end of the capacitor C4, the other end of the resistor R6 is connected to the negative terminal VO- of the output voltage in sequence through resistors R5 and R4, the differential sampling operational amplifier I The output end of C2 is connected to the other end of capacitor C2, the other end of resistor R2, one end of pull-up resistor R3, one end of resistor R7, and one end of resistor R11. The other end of pull-up resistor R3 is connected to auxiliary source S5V. The other end of resistor R11 is connected to one end of capacitor C5. The other end of capacitor C5 is connected to the other end of resistor R7 and then to the inverting input end of sampling signal error amplifier IC1, one end of resistor R1, and one end of capacitor C1. The other end of resistor R1 is connected to one end of capacitor C3. The output end of sampling signal error amplifier IC1 is connected to the other end of capacitor C3. The other end of capacitor C1 is connected to an external main control chip via an optocoupler or a transistor. The non-inverting input end of sampling signal error amplifier IC1 is connected to reference voltage VRFF and the source of MOS transistor Q1. The gate of MOS transistor Q1 is connected to the enable end, and the drain of MOS transistor Q1 is grounded. Resistors R2, R5, and R6 serve as sampling resistors, and are selected to have a resistance value in the kilo-ohm range with an accuracy of ±1%.
[0005] It is further characterized in that: the sampling signal error amplifier IC1 adopts the LMV321 sampling signal error amplifier chip, the differential sampling operational amplifier IC2 adopts the SGM8965A operational amplifier chip, and the resistance values of the resistors R2, R5, and R6 correspond to the same resistance values of the resistors R12, R9, and R10 respectively.
[0006] After adopting the above structure, by configuring the values of the three sampling resistors and fine-tuning the ohm-level resistance of resistors R4 and R8, the difference between the differential sampling value output by the differential sampling operational amplifier IC2 and the reference voltage VRFF is amplified, and then transmitted to the main control chip through an external optocoupler or transistor, thereby controlling the output duty cycle of the main control chip, and ultimately stabilizing the output voltage at the expected value. The voltage divider resistors use ordinary high-precision resistors instead of ultra-high-precision voltage divider resistors, and are not directly connected to the sampling signal error amplifier, so that more stable and efficient output voltage sampling can be achieved; at the same time, by using the pull-up resistor R3 at the output end of the differential sampling operational amplifier, the output level of the sampling signal error amplifier IC1 can be controlled when power protection occurs. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 This is a circuit diagram of the utility model. DETAILED DESCRIPTION
[0008] like Figure 1As shown, a differential sampling calculation circuit composed of operational amplifiers includes a sampling signal error amplifier IC1. The sampling signal error amplifier IC1 adopts the LMV321 sampling signal error amplifier chip. A differential sampling circuit is provided between the sampling signal error amplifier IC1 and the positive terminal VO+ and the negative terminal VO- of the output voltage. The differential sampling circuit includes a differential sampling operational amplifier IC2. The differential sampling operational amplifier IC2 adopts the SGM8965A operational amplifier chip, which has the characteristics of high speed, low noise, and rail-to-rail. The non-inverting input terminal of the differential sampling operational amplifier IC2 is connected to one end of the resistor R10, one end of the resistor R12, one end of the capacitor C8, and one end of the capacitor C4. The other end of the resistor R10 is connected to the positive end VO+ of the output voltage through the resistor R9 and the resistor R8 in sequence. The other end of the resistor R12 is connected to the other end of the capacitor C8 and then grounded. The inverting input terminal of the sampling signal error amplifier IC1 is connected to one end of the resistor R2, one end of the capacitor C2, one end of the resistor R6, and the other end of the capacitor C4. The other end of the resistor R6 is connected to the negative end VO- of the output voltage through the resistor R5 and the resistor R4 in sequence. The output terminal of the differential sampling operational amplifier IC2 is connected to the other end of the capacitor C2, the other end of the resistor R2, one end of the pull-up resistor R3, one end of the resistor R7, and one end of the resistor R11. The other end of the pull-up resistor R3 is connected to the auxiliary source S 5V, the other end of the resistor R11 is connected to one end of the capacitor C5, the other end of the capacitor C5 is connected to the other end of the resistor R7, and then connected to the inverting input end of the sampling signal error amplifier IC1, one end of the resistor R1, and one end of the capacitor C1. The other end of the resistor R1 is connected to one end of the capacitor C3. The output end of the sampling signal error amplifier IC1 is connected to the other end of the capacitor C3, and the other end of the capacitor C1 is connected to the external main control chip through an optocoupler or a transistor. The non-inverting input end of the sampling signal error amplifier IC1 is connected to the reference voltage VRFF and the source of the MOS tube Q1. The gate of the MOS tube Q1 is connected to the enable end, and the drain of the MOS tube Q1 is grounded. When the power supply is protected under certain specific conditions, the enable end of the MOS tube Q1 is high, and the reference voltage VRFF will be pulled to a low level by the MOS tube Q1.
[0009] During operation, the differential sampling operational amplifier IC2's output voltage differential is amplified by the difference between the sampling signal error amplifier IC1 and the reference voltage VREF. The amplified value is then transmitted to the external control chip via an optocoupler or transistor, which controls the chip's output duty cycle, ultimately stabilizing the output voltage at the desired value. The sampling resistors R2, R5, and R6 have values corresponding to those of R12, R9, and R10, respectively. Resistors with ±1% accuracy in the kilo-ohm range are typically used. By configuring the values of the three sampling resistors and fine-tuning the ohm-level resistors R4 and R8, the output voltage can be brought closer to the desired value. Furthermore, due to the presence of the differential sampling operational amplifier IC2, even if the output voltage is too high or the sampling resistors short-circuit, the subsequent sampling signal error amplifier IC1 will not be damaged, effectively protecting the control chip and other circuits. This differential sampling circuit, constructed using op amps, avoids direct connection of the output voltage divider to the sampling signal error amplifier, enabling efficient output voltage sampling while ensuring overall circuit safety. When the power supply is protected under certain conditions, the reference voltage VREF is pulled low and the module has no output voltage. The positive and negative input terminals of the sampling signal error amplifier IC1 are both low, and the output terminal level will be uncertain. At this time, the output terminal of the differential sampling operational amplifier IC2 is connected to the auxiliary source S5V through the pull-up resistor R3, which is equivalent to injecting a very small voltage into the negative input terminal of the sampling signal error amplifier IC1, so that the output terminal of the sampling signal error amplifier IC1 remains low.
[0010] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by anyone familiar with the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A differential sampling calculation circuit composed of an operational amplifier, comprising a sampling signal error amplifier IC1, characterized in that: A differential sampling circuit is provided between the sampling signal error amplifier IC1 and the positive terminal VO+ and the negative terminal VO- of the output voltage. The differential sampling circuit includes a differential sampling operational amplifier IC2. The non-inverting input terminal of the differential sampling operational amplifier IC2 is connected to one end of a resistor R10, one end of a resistor R12, one end of a capacitor C8, and one end of a capacitor C4. The other end of the resistor R10 is connected to the positive terminal VO+ of the output voltage through resistors R9 and R8 in sequence. The other end of the resistor R12 is connected to the other end of the capacitor C8 and then grounded. The inverting input terminal of the sampling signal error amplifier IC1 is connected to one end of a resistor R2, one end of a capacitor C2, one end of a resistor R6, and the other end of the capacitor C4. The other end of the resistor R6 is connected to the negative terminal VO- of the output voltage through resistors R5 and R4 in sequence. The output terminal of the differential sampling operational amplifier IC2 is connected to the other end of the capacitor C2 and the other end of the resistor R2. , one end of a pull-up resistor R3, one end of a resistor R7, and one end of a resistor R11. The other end of the pull-up resistor R3 is connected to an auxiliary source S5V. The other end of the resistor R11 is connected to one end of a capacitor C5. The other end of the capacitor C5 is connected to the other end of the resistor R7 and then to the inverting input of the sampling signal error amplifier IC1, one end of the resistor R1, and one end of the capacitor C1. The other end of the resistor R1 is connected to one end of the capacitor C3. The output of the sampling signal error amplifier IC1 is connected to the other end of the capacitor C3, and the other end of the capacitor C1 is connected to an external main control chip via an optocoupler or a transistor. The non-inverting input of the sampling signal error amplifier IC1 is connected to a reference voltage VRFF and the source of the MOS transistor Q1. The gate of the MOS transistor Q1 is connected to the enable terminal, and the drain of the MOS transistor Q1 is grounded. The resistors R2, R5, and R6 serve as sampling resistors, and are selected to be resistors with a precision of ±1% and a resistance in the kilo-ohm range.
2. The differential sampling calculation circuit composed of an operational amplifier according to claim 1, characterized in that: The sampling signal error amplifier IC1 adopts the LMV321 sampling signal error amplifier chip, the differential sampling operational amplifier IC2 adopts the SGM8965A operational amplifier chip, and the resistance values of the resistors R2, R5, and R6 correspond to the same resistance values of the resistors R12, R9, and R10 respectively.