Multi-channel switching circuit, chip and electronic equipment

Abstract

The embodiment of the utility model provides a multi-channel switching circuit, a chip and electronic equipment, the multi-channel switching circuit comprises at least two channel modules, each channel module comprises an input port, a switch unit and an output port, the first end of the switch unit is connected to the input port, the second end of the switch unit is connected to the output port, and the first end of the switch unit is connected to the input port. The third end of the switch unit is connected to a voltage dividing node which divides voltage with the input port; and the switching module comprises at least one switching unit, each switching unit is connected between any two access modules, the control end of the switching unit is connected to the first voltage dividing node, the first end of the switching unit is connected to the second voltage dividing node, and the second end of the switching unit is grounded. According to the invention, automatic switching of multiple access modules is realized, and manual operation and master control are not needed.

Description

Technical Field

[0001] The present application relates to the field of circuit switch technology, and in particular to a multi-channel switching circuit, chip, and electronic device. Background Art

[0002] Currently, there are two main approaches to multi-channel power switching. One involves single-pole double-throw (SPDT) or single-pole multiple-throw (SPMT) switching, which requires manual operation. The other involves a master control chip controlling power path switching, which requires software implementation and requires power to be supplied to the master control chip before path switching can be controlled.

[0003] Single-pole double-throw (SPDT) or single-pole multiple-throw (SPMT) switching solutions require manual operation, which is cumbersome in the era of intelligent devices. Controlling power path switching through a master control chip requires both a master control chip and software control. Furthermore, the control solution may fail due to a power failure to the master control chip. Utility Model Content

[0004] In view of the above problems, embodiments of the present application provide a multi-channel switching circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a multi-channel switching circuit, comprising:

[0006] At least two path modules, each path module comprising an input port, a switch unit, and an output port, wherein a first end of the switch unit is connected to the input port, a second end of the switch unit is connected to the output port, and a third end of the switch unit is connected to a voltage dividing node with the input port;

[0007] A switching module, the switching module comprising at least one switching unit, each of the switching units being connected between any two of the passage modules, a control end of the switching unit being connected to a first voltage-dividing node, a first end of the switching unit being connected to a second voltage-dividing node, and a second end of the switching unit being grounded;

[0008] Among them, the first voltage dividing node is the voltage dividing node of the path module with the first conduction priority among any two path modules, and the second voltage dividing node is the voltage dividing node of the path module with the second conduction priority among any two path modules; the first conduction priority is higher than the second conduction priority.

[0009] In a second aspect, an embodiment of the present application further provides a chip comprising the above-mentioned multi-channel switching circuit.

[0010] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a device body and the above-mentioned chip disposed in the device body.

[0011] The multi-path switching circuit, chip, and electronic device provided in the embodiments of the present application include at least two path modules, the path module includes an input port, a switch unit, and an output port, the first end of the switch unit is connected to the input port, the second end of the switch unit is connected to the output port, and the third end of the switch unit is connected to a voltage-dividing node with a voltage divided by the input port; the switching module includes at least one switching unit, each switching unit is connected between any two path modules, the control end of the switching unit is connected to the first voltage-dividing node, the first end of the switching unit is connected to the second voltage-dividing node, and the second end of the switching unit is grounded; wherein the first voltage-dividing node is the voltage-dividing node of the path module with the first conduction priority in any two path modules , the second voltage-dividing node is the voltage-dividing node of the path module with the second conduction priority in any two path modules; the first conduction priority is higher than the second conduction priority; through the above method, it is realized that when only the input port of one path module receives a signal, it automatically switches to the output signal of the path module; when the input ports of multiple path modules receive signals, it automatically switches to the output signal of the path module with the highest conduction priority in the path module receiving the signal; when the path module outputting the signal stops receiving the signal, it automatically switches to the output signal of the path module with the highest conduction priority in the path module currently receiving the signal, thereby realizing automatic switching of multiple path modules, without the need for manual operation and master control, and is suitable for all scenarios requiring path switching. The chip and electronic device provided by the embodiment of the present application, including the above-mentioned multi-path switching circuit, realize automatic switching of multiple path modules, without the need for manual operation and master control, and is suitable for all scenarios requiring path switching.

[0012] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic structural diagram of a multi-channel switching circuit provided in an embodiment of the present application is shown.

[0015] Figure 2 A schematic structural diagram of a multi-channel switching circuit provided in an embodiment of the present application is shown.

[0016] Figure 3 A schematic structural diagram of a path module in a multi-path switching circuit provided in an embodiment of the present application is shown.

[0017] Figure 4 A schematic structural diagram of a first path module in a multi-path switching circuit provided in an embodiment of the present application is shown.

[0018] Figure 5 A schematic structural diagram of a second path module in a multi-path switching circuit provided in an embodiment of the present application is shown.

[0019] Figure 6 A schematic structural diagram of a third path module in a multi-path switching circuit provided in an embodiment of the present application is shown.

[0020] Figure 7 A schematic structural diagram of a first switching unit in a multi-channel switching circuit provided in an embodiment of the present application is shown.

[0021] Figure 8 A schematic structural diagram of a second switching unit in a multi-channel switching circuit provided in an embodiment of the present application is shown.

[0022] Figure 9 A schematic structural diagram of a third switching unit in a multi-channel switching circuit provided in an embodiment of the present application is shown.

[0023] Figure 10 A schematic diagram of the structure of the chip provided in an embodiment of the present application is shown.

[0024] Figure 11 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0026] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0027] In the description of this application, words such as "first", "second", and "third" are only used for the purpose of distinguishing the description and cannot be understood as indicating or implying relative importance or order.

[0028] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, the terms "including," "comprising," "having," and their variations in this specification all mean "including but not limited to," unless otherwise specifically stated.

[0029] It should be noted that, in the embodiment of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0030] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0031] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the drain, and the second electrode / second end is the source.

[0032] Please refer to Figure 1The multi-path switching circuit 100 of the embodiment of the present application includes a path module 10 and a switching module 20. There are at least two path modules 10, and the path module 10 includes a switch unit 11, an input port 12, and an output port 13. The first end of the switch unit 11 is connected to the input port 12, the second end of the switch unit 11 is connected to the output port 13, and the third end of the switch unit 11 is connected to the voltage dividing node 14, which divides the voltage with the input port 12. The switching module 20 includes at least one switching unit 21. Each switching unit 21 is connected between any two path modules 10. The control end of the switching unit 21 is connected to the first voltage dividing node, the first end of the switching unit 21 is connected to the second voltage dividing node, and the second end of the switching unit 21 is grounded. The first voltage dividing node is the voltage dividing node 14 of the path module 10 with the first conduction priority among any two path modules 10, and the second voltage dividing node is the voltage dividing node 14 of the path module 10 with the second conduction priority among the two path modules 10. The first conduction priority is higher than the second conduction priority. In other words, the first voltage dividing node is the voltage dividing node 14 of the path module 10 with a higher conduction priority among any two path modules 10 , and the second voltage dividing node is the voltage dividing node 14 of the path module 10 with a lower conduction priority among the two path modules 10 .

[0033] In the multi-path switching circuit 100, when the input ports 12 of multiple path modules 10 receive a signal, the voltage divider node 14 of the path module 10 with the third conduction priority among the multiple path modules 10 receiving the signal is at a first level, where the third conduction priority is higher than the first conduction priority. In other words, when the input ports 12 of the multiple path modules 10 receive a signal, the voltage divider node 14 of the path module 10 with the highest conduction priority among the multiple path modules 10 receiving the signal is at the first level. The switching module 20 is configured to control the voltage divider nodes 14 of the remaining path modules 10 to a second level, where the path module 10 with the voltage divider node 14 at the first level is turned on, while the remaining path modules 10 are turned off.

[0034] Exemplarily, the first level may be a high level, and the second level may be a low level.

[0035] With respect to a single switching unit 21, when the voltage-dividing node 14 of a higher-priority path module 10 is at the first level and the voltage-dividing node 14 of a lower-priority path module 10 is at the first level, the switching module 20 turns on, causing the voltage-dividing node 14 of the lower-priority path module 10 to be pulled down to the second level. When the voltage-dividing node 14 of a higher-priority path module 10 is at the first level and the voltage-dividing node 14 of a lower-priority path module 10 is at the second level, the switching module 20 turns on, causing the voltage-dividing node 14 of the lower-priority path module 10 to maintain the second level. When the voltage-dividing node 14 of a higher-priority path module 10 is at the second level, the switching module 20 turns off, regardless of whether the voltage-dividing node 14 of the lower-priority path module 10 is at the first or second level, without affecting the voltage-dividing node 14 of the lower-priority path module 10.

[0036] The embodiment of the present application realizes that when only the input port 12 of one path module 10 receives a signal, it automatically switches to the path module 10 to be turned on. When the input ports 12 of multiple path modules 10 receive signals, the path module 10 with the highest turn-on priority among the multiple path modules 10 is controlled to be turned on. When the turned-on path module 10 stops receiving signals, it automatically switches to the next path module 10 to be turned on. The next path module 10 is the path module 10 with the highest turn-on priority among the path modules 10 currently receiving signals, thereby realizing automatic switching of multiple path modules 10 without the need for manual operation and master control, and is suitable for all scenarios requiring path switching. The electronic device provided by the embodiment of the present application includes the above-mentioned multi-path switching circuit 100, which realizes automatic switching of multiple path modules 10 without the need for manual operation and master control, and is suitable for all scenarios requiring path switching.

[0037] In this embodiment, the signal can be an analog signal or a digital signal. For example, the signal can be a power supply voltage signal. The multi-channel switching circuit 100 can be used to implement multi-channel power supply switching. When only one power supply is powered, the multi-channel switching circuit 100 can automatically switch to that power supply for power supply. When multiple power supplies are connected simultaneously, the multi-channel switching circuit 100 can automatically switch to the power supply with the highest conduction priority for power supply. If the power supply currently supplying power is disconnected, the multi-channel switching circuit 100 can automatically switch to the next power supply for power supply. The next power supply is the power supply with the highest conduction priority among the currently powered power supplies.

[0038] For example, please refer to Figure 2The multi-path switching circuit 100 includes a first path module 10a, a second path module 10b, and a third path module 10c, with conduction priorities decreasing in sequence. The switching module 20 includes a first switching unit 21a, a second switching unit 21b, and a third switching unit 21c. The first switching unit 21a is connected between the first path module 10a and the second path module 10b, the second switching unit 21b is connected between the first path module 10a and the third path module 10c, and the third switching unit 21c is connected between the first path module 10b and the third path module 10c. When the first path module 10a receives a signal, regardless of whether the second path module 10b and the third path module 10c receive a signal, the first switching unit 21a turns off the second path module 10b, and the second switching unit 21b turns off the third path module 10c, leaving only the first path module 10a conducting and outputting a signal. When the first pathway module 10a does not receive a signal, and the second pathway module 10b does, regardless of whether the third pathway module 10c receives a signal, the third switching unit 21c switches the third pathway module 10c off, leaving only the second pathway module 10b switched on and outputting a signal. When neither the first pathway module 10a nor the second pathway module 10b receives a signal, and the third pathway module 10c receives a signal, the third pathway module 10b switches on and outputs a signal. This achieves automatic switching of multiple pathway modules 10. When multiple pathway modules 10 receive signals, only the pathway module 10 with the highest priority switches on to output a signal. This eliminates the need for manual operation or master control, making it suitable for all scenarios requiring pathway switching.

[0039] It is understandable that in other embodiments, the multi-path switching circuit 100 may also include two path modules 10, or four path modules 10, or more path modules 10, which will not be described in detail here.

[0040] In some embodiments, see Figure 3The switch unit 11 includes a first sub-switch unit 111 and a second sub-switch unit 112. The first end of the first sub-switch unit 111 is connected to the input port 12, and the second end of the first sub-switch unit 111 is connected to the output port 13. The first end of the second sub-switch unit 112 is connected to the control end of the first sub-switch unit 111, the second end of the second sub-switch unit 112 is grounded, and the control end of the second sub-switch unit 112 is connected to the voltage dividing node 14. When the voltage dividing node 14 is at a first level, the second sub-switch unit 112 is turned on, pulling down the level of the control end of the first sub-switch unit 111, causing the first sub-switch unit 111 to be turned on. The signal received by the input port 12 of the path module 10 passes through the turned-on first sub-switch unit 111 and is output to the output port 13. When the voltage-dividing node 14 is at the second level, the second sub-switch unit 112 is turned off, maintaining the voltage level at the control terminal of the first sub-switch unit 111 at the first level, thereby keeping the first sub-switch unit 111 turned off. Even if the input port 12 of the path module 10 receives a signal, the received signal cannot pass through the first sub-switch unit 111 and output the signal at the output port 13. Even if multiple path modules 10 receive signals, the switching module 20 ensures that only the path module 10 with the highest priority among the path modules 10 receiving the signal has its voltage-dividing node 14 at the first level. In other words, only the path module 10 with the highest priority is turned on. This eliminates the need for manual operation or master control, and allows output signals according to the preset conduction priority, making it suitable for all scenarios requiring path switching.

[0041] In some embodiments, see Figures 4 to 6 , the first sub-switch unit 111 includes one or more first transistors connected in series. The second sub-switch unit 112 includes a second transistor. The second end of the second transistor is connected to the control end of the first transistor, the first end of the second transistor is grounded, and the control end of the second transistor is connected to the voltage dividing node 14. When the voltage dividing node 14 is at a first level, the second transistor is turned on, thereby lowering the level of the control end of the first transistor, turning on the first transistor, and the signal is output via the input port 12, the first transistor 111 and the output port 13 in sequence. When the voltage dividing node 14 is at a second level, the second transistor 112 is turned off, so that the control end of the first transistor 111 remains at the first level, thereby keeping the first transistor 111 turned off. Even if the input port 12 receives a signal, the output port 13 cannot output a signal.

[0042] Exemplarily, the first transistor may be a PMOS transistor, and the second transistor may be an NMOS transistor.

[0043] As an optional implementation, please refer to Figures 4 to 6The first sub-switch unit 111 includes two first transistors. The first end of one of the first transistors is connected to the input port 12, and the second end is connected to the second end of the other first transistor. The first end of the other first transistor is connected to the output port 13. The control ends of the two first transistors are connected to the first end of the second sub-switch unit 112, thereby implementing an anti-backfeed function and preventing the signal from being fed back from the output port 13 to the input port 12.

[0044] In some embodiments, see Figures 4 to 6 The path module 10 further includes a first voltage divider unit 15 and a second voltage divider unit 16. One end of the first voltage divider unit 15 is connected to the input port 12, and the other end of the first voltage divider unit 15 is connected to the voltage divider node 14. One end of the second voltage divider unit 16 is connected to the voltage divider node 14, and the other end of the second voltage divider unit 16 is grounded.

[0045] For example, please refer to Figures 4 to 6 The first voltage divider unit 15 can be a first resistor, and the second voltage divider unit 16 can be a second resistor. One end of the first resistor is connected to the input port 12, the other end of the first resistor is connected to one end of the second resistor, and the other end of the second resistor is grounded. The voltage divider node 14 is located between the first resistor and the second resistor. When the input port 12 does not receive a signal, since the other end of the second resistor is grounded, the voltage level of the voltage divider node 14 can be pulled down by the second resistor, thereby maintaining the voltage divider node 14 at the second level, ensuring that the switch unit 11 is turned off and the path module 10 is not conductive.

[0046] In some embodiments, the input port 12 of each path module 10 is used to receive different signals. Since the multi-path switching circuit 100 can realize automatic switching of the multi-path path modules 10, the multi-path automatic switching circuit 100 can also switch between multiple different input signals.

[0047] For example, please refer to Figure 4 The input port 12 of the first path module 10a can be used to receive the first power supply voltage signal 5V0. Figure 5 The input port 12 of the second path module 10b can be used to receive the second power supply voltage signal VBUS1. Figure 6 The input port 12 of the third path module 10c can be used to receive the third power supply voltage signal VBUS2, thereby realizing multi-channel power switching.

[0048] As an optional implementation, please refer to Figures 7 to 9 The switching unit 21 includes a third transistor, and the turn-on voltage of the third transistor is lower than the turn-on voltage of the second transistor, which can prevent the third transistor from interfering with the switching of the conduction state of the second transistor.

[0049] Exemplarily, the third transistor may be an NMOS transistor.

[0050] In some embodiments, the output ports 13 of all the path modules 10 are connected to a common port, so that one output port can output signals from different sources.

[0051] In some embodiments, at least one path module 10 further includes a delay unit 17, a first end of the delay unit 17 being connected to a first end of the switch unit 11, and a second end of the delay unit 17 being connected to a control end of the switch unit 11, to ensure that when multiple path modules 10 receive signals simultaneously, when the signal received by the path module 10 that is outputting a signal is disconnected, the path module 10 can be shut down in time, and the path module 10 with the next conduction priority can be turned on normally.

[0052] In one embodiment, the delay unit 17 may include a capacitor, a first end of the capacitor is connected to the control end of the switch unit 11, and a second end of the capacitor is connected to the control end of the switch unit 11, to ensure that when multiple path modules 10 receive signals at the same time, when the signal received by the path module 10 that is outputting the signal is disconnected, the path module 10 can be turned off in time, and the path module 10 with the next conduction priority can be turned on normally.

[0053] It is understandable that only some of the passage modules 10 may include the delay unit 17 , or all of the passage modules 10 may include the delay unit 17 . The delay unit 17 may be configured according to actual needs and will not be described in detail here.

[0054] For some examples, see Figures 4 to 9The multi-path switching circuit 100 includes three path modules 10: a first path module 10a, a second path module 10b, and a third path module 10c, with descending conduction priority. The first path module 10a receives a first power supply voltage signal 5V0, the second path module 10b receives a second power supply voltage signal VBUS1, and the third path module 10c receives a third power supply voltage signal VBUS2. The output terminals of the first, second, and third path modules 10a, 10b, and 10c are all connected to a common port. The first sub-switch unit 111 of the first path module 10a includes a first transistor Q1 and a first transistor Q2, and the second sub-switch unit 112 includes a second transistor Q3, the control terminal of which is connected to a voltage divider node 14a. The first sub-switch unit 111 of the second path module 10b includes a first transistor Q4 and a first transistor Q5, and the second sub-switch unit 112 includes a second transistor Q6, the control terminal of which is connected to a voltage divider node 14b. The first sub-switch unit 111 of the third path module 10c includes a first transistor Q7 and a first transistor Q8. The second sub-switch unit 112 includes a second transistor Q9, whose control terminal is connected to the voltage dividing node 14c. The switching module 20 includes three switching units 21: a first switching unit 21a connecting the first path module 10a and the second path module 10b, a second switching unit 21b connecting the first path module 10a and the third path module 10c, and a third switching unit 21c connecting the second path module 10b and the third path module 10c. The first switching unit 21a includes a third transistor Q10, whose control terminal is connected to the voltage dividing node 14a and whose first terminal is connected to the voltage dividing node 14b. The second switching unit 21b includes a third transistor Q11, whose control terminal is connected to the voltage dividing node 14a and whose first terminal is connected to the voltage dividing node 14c. The third switching unit 21c includes a third transistor Q12, a control terminal of the third transistor Q12 connected to the voltage dividing node 14b, and a first terminal of the third transistor Q12 connected to the voltage dividing node 14c. All first transistors are PMOS transistors, and all second transistors and all third transistors are NMOS transistors.

[0055] When the first path module 10a receives the first power supply voltage signal, regardless of whether the second path module 10b and the third path module 10c receive signals, the voltage dividing node 14a is at the first level, controlling the second transistor Q3 to conduct. At this time, the first sub-switch unit 111 composed of the first transistor Q1 and the first transistor Q2 is in the on state. Since the voltage dividing node 14a is at the first level, the third transistor Q10 and the third transistor Q11 are turned on, causing the voltage dividing node 14b and the voltage dividing node 14c to both be at the second level, and the second path module 10b and the third path module 10c to be turned off. Therefore, when the first path module 10a receives the first power supply voltage signal, the first path module 10a outputs the signal.

[0056] When the second pathway module 10b receives the second power supply voltage signal and the first pathway module 10a receives no signal, regardless of whether the third pathway module 10c receives a signal, the voltage-dividing node 14b is at the first level, controlling the second transistor Q6 to conduct. At this point, the first sub-switch unit 111, consisting of the first transistors Q4 and Q5, is in the on state. Since the voltage-dividing node 14b is at the first level, the third transistor Q12 is turned on, causing the voltage-dividing node 14c to be at the second level, and the third pathway module 10c is turned off. Furthermore, since the input port 12 of the first pathway module 10a is left floating, the voltage-dividing node 14a is grounded via the second resistor R2. Therefore, the voltage-dividing node 14a is at the second level, and the first pathway module 10a is turned off. Therefore, when the second pathway module 10b receives the second power supply voltage signal and the first pathway module 10a receives no signal, the second pathway module 10b outputs the signal.

[0057] When only the third pathway module 10c receives the third power supply voltage signal and the first pathway module 10a and the second pathway module 10b receive no signals, the voltage dividing node 14c reaches the first level, controlling the second transistor Q9 to conduct. At this point, the first sub-switch unit 111, composed of the first transistors Q7 and Q8, is in the on state. Since the input port 12 of the first pathway module 10a is left floating, the voltage dividing node 14a is grounded via the second resistor R2. Therefore, the voltage dividing node 14a reaches the second level, and the first pathway module 10a is turned off. Since the input port 12 of the second pathway module 10b is left floating, the voltage dividing node 14b is grounded via the second resistor R5. Therefore, the voltage dividing node 14b reaches the second level, and the second pathway module 10b is turned off. Therefore, when only the third pathway module 10c receives the third power supply voltage signal and the first pathway module 10a and the second pathway module 10b receive no signals, the third pathway module 10c outputs the signal.

[0058] When the first, second, and third pathway modules 10a, 10b, and 10c receive their respective power supply voltage signals, the first pathway module 10a turns on, while the second and third pathway modules 10b, 10c turn off, with the first pathway module 10a outputting the signal. If the second pathway module 10b is disconnected from the second power supply voltage signal and / or the third pathway module 10c is disconnected from the third power supply voltage signal, the first pathway module 10a remains on. If the first pathway module 10a is disconnected from the first power supply voltage signal, the first sub-switch unit 111 of the first pathway module 10a turns off, automatically switching to the first sub-switch unit 111 of the second pathway module 10b turning on, with the second pathway module 10b outputting the signal. If the first pathway module 10a is disconnected from the first power supply voltage signal and the second pathway module 10b is disconnected from the second power supply voltage signal, the first sub-switch unit 111 of the first pathway module 10a turns off, automatically switching to the first sub-switch unit 111 of the third pathway module 10c turning on, with the third pathway module 10c outputting the signal.

[0059] When only the second pathway module 10b and the third pathway module 10c receive their respective corresponding power supply voltage signals, and the first pathway module 10a receives no signal, the first sub-switch unit 111 of the second pathway module 10b turns on, while the first sub-switch unit 111 of the first pathway module 10a and the first sub-switch unit 111 of the third pathway module 10c turn off, and the second pathway module 10b outputs the signal. If the second pathway module 10b is disconnected from the second power supply voltage signal, the first sub-switch unit 111 of the second pathway module 10b turns off, automatically switching to the first sub-switch unit 111 of the third pathway module 10c turning on, and the third pathway module 10c outputs the signal. If the third pathway module 10c is disconnected from the third power supply voltage signal, the first sub-switch unit 111 of the second pathway module 10b remains on, and the second pathway module 10b still outputs the signal.

[0060] For example, please refer to Figure 6 A delay unit 17 including a capacitor is connected between the first terminal and the control terminal of the first sub-switch unit 111 of the third pathway module 10c. When the output ports 13 of all pathway modules 10 are simultaneously connected to a common port, if the second pathway module 10b and the third pathway module 10c each receive their corresponding power supply voltage signals and the second pathway module 10b is disconnected from the second power supply voltage signal, the capacitor ensures that the first sub-switch unit 111 of the second pathway module 10b is promptly turned off, while the first sub-switch unit 111 of the third pathway module 10c remains turned on normally.

[0061] Specifically, without delay unit 17, when second path module 10b is disconnected from the second power supply voltage signal, the common port begins to drop due to load. However, when it drops to a certain level, first sub-switch unit 111 of third path module 10c enters a partially conductive state because Vgs is less than 0V. At this time, first sub-switch unit 111 of second path module 10b fails to shut down in time, and voltage-dividing node 14b remains at the first level. Under the action of switching unit 21, voltage-dividing node 14c reaches the second level, causing first sub-switch unit 111 of third path module 10c to remain in a partially conductive state and unable to conduct normally. However, in this example, a capacitor serving as delay unit 17 is connected between the first terminal and the control terminal of first sub-switch unit 111 of third path module 10c. Due to the time delay of the capacitor, before the first sub-switch unit 111 of the third path module 10c is turned on, the first sub-switch unit 111 of the second path module 10b is turned off first, the voltage dividing node 14b becomes the second level, and the voltage dividing node 14c can be pulled high normally, so that the first sub-switch unit 111 of the third path module 10c is turned on.

[0062] Please refer to Figure 10 The present application also provides a chip 200, see Figure 10 As shown, the chip 200 includes the multi-channel switching circuit 100. An integrated circuit (IC) is also called a chip, which can be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip.

[0063] The chip of this embodiment realizes that when only the input port 12 of one path module 10 receives a signal, it automatically switches to the path module 10 to output the signal; when the input ports 12 of multiple path modules 10 receive signals, it automatically switches to the path module 10 with the highest conduction priority among the path modules 10 receiving the signal to output the signal; when the path module 10 outputting the signal stops receiving the signal, it automatically switches to the path module 10 with the highest conduction priority among the path modules 10 currently receiving the signal to output the signal, thereby realizing automatic switching of multiple path modules 10 without the need for manual operation or master control, and is suitable for all scenarios requiring path switching.

[0064] Please refer to Figure 11The embodiment of the present application also provides an electronic device 300, which includes a device body and a multi-channel switching circuit 100 as described above, which is provided in the device body. The electronic device 300 can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central console, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sale) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0065] The electronic device 300 provided in the embodiment of the present application includes the above-mentioned chip 200, which realizes that when only the input port 12 of one path module 10 receives a signal, it automatically switches to the path module 10 to output the signal; when the input ports 12 of multiple path modules 10 receive signals, it automatically switches to the path module 10 with the highest conduction priority among the path modules 10 receiving the signal to output the signal; when the path module 10 outputting the signal stops receiving the signal, it automatically switches to the path module 10 with the highest conduction priority among the path modules 10 currently receiving the signal to output the signal, thereby realizing automatic switching of multiple path modules 10 without the need for manual operation or master control, and is suitable for all scenarios requiring path switching.

[0066] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A multi-channel switching circuit, characterized in that: include: At least two path modules, each path module comprising an input port, a switch unit, and an output port, wherein a first end of the switch unit is connected to the input port, a second end of the switch unit is connected to the output port, and a third end of the switch unit is connected to a voltage dividing node with the input port; A switching module, the switching module comprising at least one switching unit, each of the switching units being connected between any two of the passage modules, a control end of the switching unit being connected to a first voltage-dividing node, a first end of the switching unit being connected to a second voltage-dividing node, and a second end of the switching unit being grounded; Among them, the first voltage dividing node is the voltage dividing node of the path module with the first conduction priority among any two path modules, and the second voltage dividing node is the voltage dividing node of the path module with the second conduction priority among any two path modules; the first conduction priority is higher than the second conduction priority.

2. The multi-channel switching circuit according to claim 1, wherein: When the input ports of the plurality of the path modules receive signals, the voltage dividing node of the path module with the third conduction priority among the plurality of path modules receiving the signals is at a first level, wherein the third conduction priority is higher than the first conduction priority; The switching module is used to control the voltage division nodes of the remaining path modules to be at a second level, wherein the path module with the voltage division node at the first level is turned on, and the remaining path modules are turned off.

3. The multi-channel switching circuit according to claim 1, wherein: The switch unit includes a first sub-switch unit and a second sub-switch unit; The first end of the first sub-switch unit is connected to the input port, and the second end of the first sub-switch unit is connected to the output port; The first end of the second sub-switch unit is connected to the control end of the first sub-switch unit, the second end of the second sub-switch unit is grounded, and the control end of the second sub-switch unit is connected to the voltage dividing node; When the voltage division node is at a first level, the second sub-switch unit is turned on to turn on the first sub-switch unit; When the voltage dividing node is at a second level, the second sub-switch unit is turned off to turn off the first sub-switch unit.

4. The multi-channel switching circuit according to claim 3, wherein: The first sub-switch unit includes one or more first transistors connected in series; The second sub-switch unit includes a second transistor.

5. The multi-channel switching circuit according to claim 4, wherein: The switching unit includes a third transistor, and a turn-on voltage of the third transistor is lower than a turn-on voltage of the second transistor.

6. The multi-channel switching circuit according to claim 3, wherein: The first sub-switch unit includes two first transistors; The first end of one of the first transistors is connected to the input port, and the second end is connected to the second end of another first transistor. The first end of another first transistor is connected to the output port, and the control ends of the two first transistors are connected to the first end of the second sub-switch unit.

7. The multi-channel switching circuit according to claim 1, wherein: The passage module further includes a first voltage dividing unit and a second voltage dividing unit; One end of the first voltage dividing unit is connected to the input port, and the other end is connected to the voltage dividing node; One end of the second voltage dividing unit is connected to the voltage dividing node, and the other end is grounded.

8. The multi-channel switching circuit according to claim 1, wherein: The input port of each of the path modules is used to receive different signals.

9. The multi-channel switching circuit according to claim 1, wherein: The output ports of all the pathway modules are connected to a common port.

10. The multi-channel switching circuit according to claim 1, wherein: At least one of the passage modules further includes a delay unit, a first end of the delay unit is connected to the first end of the switch unit, and a second end of the delay unit is connected to the control end of the switch unit.

11. A chip, characterized in that: The chip includes the multi-channel switching circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The device comprises a device body and the chip according to claim 11 arranged in the device body.

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